CN209312753U - A kind of semiconductor stack encapsulation bonding wire bonding press welding structure - Google Patents

A kind of semiconductor stack encapsulation bonding wire bonding press welding structure Download PDF

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Publication number
CN209312753U
CN209312753U CN201822238718.0U CN201822238718U CN209312753U CN 209312753 U CN209312753 U CN 209312753U CN 201822238718 U CN201822238718 U CN 201822238718U CN 209312753 U CN209312753 U CN 209312753U
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China
Prior art keywords
layer
chip
layer chip
semiconductor stack
substrate
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Active
Application number
CN201822238718.0U
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Chinese (zh)
Inventor
杨林峰
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Hitech Semiconductor Wuxi Co Ltd
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Hitech Semiconductor Wuxi Co Ltd
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Priority to CN201822238718.0U priority Critical patent/CN209312753U/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The utility model discloses a kind of semiconductor stack encapsulation bonding wires to be bonded press welding structure, including first layer chip, second layer chip, second layer chip is arranged on first layer chip, primer layer is equipped between the first layer chip and second layer chip, primer layer separates first layer chip and second layer chip, first layer chip is located on substrate, base lower surface is coated with anti-welding paint layer, copper post is implanted on anti-welding paint layer, copper post setting is multiple to be evenly distributed on anti-welding paint layer bottom surface, each copper post front end is implanted into tin ball, the both ends of the first layer chip and second layer chip pass through gold thread respectively and the interface of chip and the interface of substrate are bonded, the structure further includes envelope package casing, the package casing is equipped with pin interfaces and is connected to external circuitry, lead is connected to by gold thread with chip circuit, the stack manner of this structure is easy to operate, bonding is convenient, Securely, stable structure.

Description

A kind of semiconductor stack encapsulation bonding wire bonding press welding structure
Technical field
The utility model belongs to technical field of semiconductors field more particularly to a kind of semiconductor stack encapsulation bonding wire bonding pressure Welding structure.
Background technique
Semiconductor chip packaging refers to using membrane technology and subtle processing technology, by chip and other element in frame or base It is laid out on plate, pastes fixed and connection, draw connecting terminal and by plastic, dielectric encapsulating is fixed, and is constituted whole three-dimensional The technique of structure.This concept is that the encapsulation of narrow sense defines.More broadly encapsulation refers to dress engineering, and packaging body is connect admittedly with substrate It is fixed, the system or electronic equipment being assembled into, and ensure the engineering of whole system comprehensive performance.Two definition of front are combined Get up to constitute the encapsulation concept of broad sense.
Application No. is CN201510210887.1, the applyings date are as follows: 20150429, a kind of title are as follows: semiconductor packages work In the patent of skill, a kind of semiconductor packaging process, including front process, last part technology are disclosed, the front process includes: crystalline substance Piece grinding back surface, chip cutting, ultraviolet light etching, the cleaning of wafer plasma body, silicon printing, wafer solidification, die bonding, lead Bonding checks；The last part technology includes plastic packaging, laser marking, rear solidification, solder ball, cutting separation, checks, conveying, this envelope It fills technique and is directed to light and portable electronic product, it is practical, it encapsulates in process and carries out multiple checks, reduce bad products, Improve production efficiency.
Summary of the invention
The technical issues of the utility model is solved is to provide a kind of semiconductor stack encapsulation bonding wire bonding press welding structure.
The purpose of the utility model can be achieved through the following technical solutions:
A kind of semiconductor stack encapsulation bonding wire bonding press welding structure, including first layer chip 6, second layer chip 8, the second layer Chip 8 is arranged on first layer chip 6, and primer layer 7, primer layer 7 are equipped between the first layer chip 6 and second layer chip 8 Separating first layer chip 6 and second layer chip 8, first layer chip 6 are located on substrate 4,4 lower surface of substrate is coated with anti-welding paint layer 3, Be implanted into copper post 2 on anti-welding paint layer 3, copper post 2 be arranged it is multiple be evenly distributed on anti-welding 3 bottom surface of paint layer, each 2 front end of copper post is implanted into tin The both ends of ball 1, the first layer chip 6 and second layer chip 8 pass through gold thread 9 the interface of chip and the interface key of substrate respectively It closes, the structure further includes envelope package casing 10, and the package casing 10 is equipped with pin interfaces and is connected to external circuitry, gold thread 9 Lead is connected to chip circuit.
Preferably, first layer chip 6 is pasted on substrate 4 by epoxy resin layer 5.
Preferably, the epoxy resin layer 5 with a thickness of 50 microns.
Preferably, the first layer chip 6 is identical with the thickness of second layer chip 8.
Preferably, the first layer chip 6 and second layer chip 8 with a thickness of 125 microns.
Preferably, the substrate 4 with a thickness of 200 microns.
Preferably, the primer layer 7 with a thickness of 63 microns.
The utility model has the beneficial effects that
The stack manner of this structure is easy to operate, and bonding is convenient, securely, stable structure.
Detailed description of the invention
Fig. 1 is the structural schematic diagram that a kind of semiconductor stack encapsulates that bonding wire is bonded press welding structure.
Specific embodiment
In conjunction with shown in attached drawing, the technical solution of the utility model is further described:
A kind of semiconductor stack encapsulation bonding wire bonding press welding structure, including first layer chip 6, second layer chip 8, the second layer Chip 8 is arranged on first layer chip 6, and primer layer 7, primer layer 7 are equipped between the first layer chip 6 and second layer chip 8 Separating first layer chip 6 and second layer chip 8, first layer chip 6 are located on substrate 4,4 lower surface of substrate is coated with anti-welding paint layer 3, Be implanted into copper post 2 on anti-welding paint layer 3, copper post 2 be arranged it is multiple be evenly distributed on anti-welding 3 bottom surface of paint layer, each 2 front end of copper post is implanted into tin The both ends of ball 1, the first layer chip 6 and second layer chip 8 pass through gold thread 9 the interface of chip and the interface key of substrate respectively It closes, the structure further includes envelope package casing 10, and the package casing 10 is equipped with pin interfaces and is connected to external circuitry, gold thread 9 Lead is connected to chip circuit.
In the present embodiment, it is preferred that first layer chip 6 is pasted on substrate 4 by epoxy resin layer 5.
In the present embodiment, it is preferred that the epoxy resin layer 5 with a thickness of 50 microns.
In the present embodiment, it is preferred that the first layer chip 6 is identical with the thickness of second layer chip 8.
In the present embodiment, it is preferred that the first layer chip 6 and second layer chip 8 with a thickness of 125 microns.
In the present embodiment, it is preferred that the substrate 4 with a thickness of 200 microns.
In the present embodiment, it is preferred that the primer layer 7 with a thickness of 63 microns.
To the adhesive treated between chip and substrate so that after it has better adhesive property, with High Purity Gold bundle of lines chip Interface and substrate interface bonding, the electrode of chip and extraneous circuit communication, lead is used for and extraneous circuit communication, gold Line gets up the circuit connection of lead and chip, and substrate is used to chip being pasted onto substrate for carrying chip, epoxy resin layer On, plastic shell can then play fixed and protective effect.
Finally, it should be noted that above embodiments are only to illustrate rather than limit the technical solution of the utility model, although The utility model is described in detail referring to above-described embodiment, those skilled in the art should understand that: still may be used To be modified or replaced equivalently to the utility model, without departing from the spirit and scope of the utility model, and appended right It is required that being intended to these modifications fallen into the spirit and scope of the utility model or equivalent replacement.

Claims (7)

1. a kind of semiconductor stack encapsulation bonding wire is bonded press welding structure, including first layer chip (6), second layer chip (8), special Sign is:
Second layer chip (8) is arranged on first layer chip (6), sets between the first layer chip (6) and second layer chip (8) Have primer layer (7), primer layer (7) separates first layer chip (6) and second layer chip (8), first layer chip (6) are located at substrate (4) on, substrate (4) lower surface is coated with anti-welding paint layer (3), is implanted into copper post (2) on anti-welding paint layer (3), and copper post (2) setting is multiple Even to be distributed in anti-welding paint layer (3) bottom surface, each copper post (2) front end is implanted into tin ball 1, the first layer chip (6) and second layer core The both ends of piece (8) pass through gold thread (9) respectively and the interface of chip and the interface of substrate are bonded, and the structure further includes that envelope encapsulation is outer Shell (10), the package casing (10) are equipped with pin interfaces and are connected to external circuitry, and gold thread (9) connects lead and chip circuit It is logical.
2. semiconductor stack encapsulation bonding wire as described in claim 1 is bonded press welding structure, it is characterised in that: first layer chip (6) it is pasted on substrate (4) by epoxy resin layer (5).
3. semiconductor stack encapsulation bonding wire as claimed in claim 2 is bonded press welding structure, it is characterised in that: the epoxy resin Layer (5) with a thickness of 50 microns.
4. semiconductor stack encapsulation bonding wire as claimed in claim 3 is bonded press welding structure, it is characterised in that: the first layer core Piece (6) is identical with the thickness of second layer chip (8).
5. semiconductor stack encapsulation bonding wire as claimed in claim 4 is bonded press welding structure, it is characterised in that: the first layer core Piece (6) and second layer chip (8) with a thickness of 125 microns.
6. semiconductor stack encapsulation bonding wire as claimed in claim 5 is bonded press welding structure, it is characterised in that: the substrate (4) With a thickness of 200 microns.
7. semiconductor stack encapsulation bonding wire as claimed in claim 6 is bonded press welding structure, it is characterised in that: the primer layer (7) with a thickness of 63 microns.
CN201822238718.0U 2018-12-28 2018-12-28 A kind of semiconductor stack encapsulation bonding wire bonding press welding structure Active CN209312753U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201822238718.0U CN209312753U (en) 2018-12-28 2018-12-28 A kind of semiconductor stack encapsulation bonding wire bonding press welding structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201822238718.0U CN209312753U (en) 2018-12-28 2018-12-28 A kind of semiconductor stack encapsulation bonding wire bonding press welding structure

Publications (1)

Publication Number Publication Date
CN209312753U true CN209312753U (en) 2019-08-27

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Country Link
CN (1) CN209312753U (en)

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