CN113540005A - Wafer level packaging structure and packaging method thereof - Google Patents
Wafer level packaging structure and packaging method thereof Download PDFInfo
- Publication number
- CN113540005A CN113540005A CN202110786682.3A CN202110786682A CN113540005A CN 113540005 A CN113540005 A CN 113540005A CN 202110786682 A CN202110786682 A CN 202110786682A CN 113540005 A CN113540005 A CN 113540005A
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- CN
- China
- Prior art keywords
- wafer
- packaging
- adapter plate
- shaped
- wafer level
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Dicing (AREA)
Abstract
The invention discloses a wafer level packaging structure and a packaging method thereof. The invention takes a single wafer as an operation unit, the adapter plate is pasted and bonded, and glue is filled, thus realizing a simplified wafer-level packaging structure. The invention changes the wafer packaging process which needs scribing reduction, mounting, plastic packaging, grinding, fan-out circuit and cutting into the steps of manufacturing the step adapter plate, wafer-level mounting, routing and cutting through the step conductive adapter plate, thereby reducing the packaging cost and the packaging flow.
Description
Technical Field
The invention belongs to the field of chip packaging, and particularly relates to a wafer level packaging structure and a packaging method thereof.
Background
For the requirements of package miniaturization and large-scale package, the conventional Fan-out or Fan-in packaging structure has a long flow, and the structure is provided, so that the packaging flow is greatly shortened, and the cost is optimized.
Disclosure of Invention
The present invention is directed to overcome the above-mentioned deficiencies, and provides a wafer level package structure and a packaging method thereof, which reduces the packaging cost and reduces the packaging process.
In order to achieve the above object, a wafer level package structure includes a step interposer, wherein the step interposer is mounted on a wafer, and the interposer is connected to the wafer through a bonding wire.
And colloid is filled outside the bonding wire.
The adapter plate is attached to the wafer through the DAF adhesive film.
The adapter plate is attached to the wafer through glue.
A packaging method of a wafer level packaging structure comprises the following steps:
s1, attaching the step-shaped adapter plate on the wafer by taking the single wafer as an operation unit;
s2, electrically communicating the wafer with the step-shaped adapter plate through the bonding wire;
and S3, completing the packaging after cutting.
In S1, the step adapter plate is mounted on the wafer by the DAF adhesive film.
In S1, the step adapter plate is attached to the wafer by glue.
In S2, after the wafer is electrically connected to the step adapter plate, the bonding wires are filled with a sealant.
Compared with the prior art, the wafer level packaging structure has the advantages that the stepped adapter plate is pasted on the wafer, and the wafer is connected with the stepped adapter plate through the bonding wire.
The invention takes a single wafer as an operation unit, attaches the step-shaped adapter plate on the wafer, and realizes a simplified wafer-level packaging structure through routing bonding and glue filling. The invention can realize the wafer packaging process of reducing marking, mounting, plastic packaging, grinding, fan-out circuits and cutting by mounting the stepped conductive adapter plate instead of manufacturing the stepped adapter plate, mounting the stepped conductive adapter plate at the wafer level, routing and cutting, thereby reducing the packaging cost and the packaging flow.
Drawings
FIG. 1 is a schematic structural view of the present invention;
FIG. 2 is a schematic view of a wafer;
FIG. 3 is a schematic view of a stepped adapter plate;
FIG. 4 is a schematic view of a step adapter plate for attaching a DAF adhesive film or spot glue;
FIG. 5 is a schematic diagram of the structure after the bonding wire is arranged;
the wafer comprises a wafer 1, a wafer 2, a step-shaped adapter plate 3, a DAF adhesive film 4, a bonding wire 5 and a colloid.
Detailed Description
The invention is further described below with reference to the accompanying drawings.
Referring to fig. 1, a wafer level package structure includes a wafer 1, a step interposer 2 is attached to the wafer 1, and the wafer 1 is connected to the step interposer 2 through a bonding wire 4.
The bonding wires 4 are filled with colloid 5.
Further, the step-shaped adapter plate 2 is attached to the wafer 1 through the DAF adhesive film 3.
Further, the step adapter plate 2 is attached to the wafer 1 by glue.
Referring to fig. 1 to 5, a method for packaging a wafer level package structure includes the following steps:
s1, taking the single wafer 1 as an operation unit, and attaching the step-shaped adapter plate 2 to the wafer 1 through the DAF glue film 3 or the glue;
s2, electrically communicating the wafer 1 with the step-shaped adapter plate 2 through the bonding wires 4, and filling the bonding wires 4 with glue 5;
and S3, completing the packaging after cutting.
The invention can realize the wafer packaging process of reducing scratch, mounting, plastic packaging, grinding, fan-out circuit and cutting by mounting the step-shaped conductive adapter plate 2 instead of the steps of adapter plate manufacturing, wafer-level mounting, routing and cutting, thereby reducing the packaging cost and the packaging flow.
The step-shaped adapter plate substrate achieves the routing, bonding and switching functions, routing of the ultra-WB routing process capability is electrically communicated through the routing from the chip to the adapter plate, and glue filling is carried out to form a packaging finished product.
Claims (8)
1. A wafer level packaging structure is characterized by comprising a wafer (1), wherein a step-shaped adapter plate (2) is attached to the wafer (1), and the step-shaped adapter plate (2) is connected to the wafer (1) through a bonding wire (4).
2. The wafer level package structure of claim 1, wherein the bonding wires (4) are filled with a sealant (5).
3. The wafer level package structure of claim 1, wherein the step-shaped interposer (2) is attached to the wafer (1) through a DAF adhesive film (3).
4. The wafer level package structure as claimed in claim 1, wherein the step-shaped interposer (2) is attached to the wafer (1) by glue.
5. The method of claim 1, further comprising the steps of:
s1, taking the single wafer (1) as an operation unit, and attaching the step-shaped adapter plate (2) on the single wafer (1);
s2, electrically connecting the wafer (1) and the step adapter plate (2) through the bonding wire (4);
and S3, completing the packaging after cutting.
6. The method of claim 5, wherein in step 1, the step-shaped interposer (2) is attached to the wafer (1) via DAF adhesive film (3).
7. The method for packaging a wafer level package structure as claimed in claim 5, wherein in step 1, the step-shaped interposer (2) is attached to the wafer (1) by glue.
8. The method as claimed in claim 5, wherein in step 2, the bonding wires (4) are filled with the sealant (5) after the wafer (1) is electrically connected to the step-shaped interposer (2).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110786682.3A CN113540005A (en) | 2021-07-12 | 2021-07-12 | Wafer level packaging structure and packaging method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110786682.3A CN113540005A (en) | 2021-07-12 | 2021-07-12 | Wafer level packaging structure and packaging method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113540005A true CN113540005A (en) | 2021-10-22 |
Family
ID=78127587
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110786682.3A Pending CN113540005A (en) | 2021-07-12 | 2021-07-12 | Wafer level packaging structure and packaging method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113540005A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114242685A (en) * | 2021-12-01 | 2022-03-25 | 展讯通信（上海）有限公司 | Double-sided packaging assembly and forming method thereof |
-
2021
- 2021-07-12 CN CN202110786682.3A patent/CN113540005A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114242685A (en) * | 2021-12-01 | 2022-03-25 | 展讯通信（上海）有限公司 | Double-sided packaging assembly and forming method thereof |
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