CN206417858U - MEMS chip encapsulating structure - Google Patents
MEMS chip encapsulating structure Download PDFInfo
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- CN206417858U CN206417858U CN201621402964.XU CN201621402964U CN206417858U CN 206417858 U CN206417858 U CN 206417858U CN 201621402964 U CN201621402964 U CN 201621402964U CN 206417858 U CN206417858 U CN 206417858U
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- mems chip
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Abstract
The utility model provides a kind of MEMS chip encapsulating structure, including：Through hole and interconnection line are provided with substrate, the substrate；MEMS chip, the front of the MEMS chip has functional areas and multiple weld pads positioned at functional areas periphery, the weld pad is electrically connected with the functional areas, and the MEMS chip is arranged at the front of the substrate and in the through hole, and the weld pad is electrically connected with the interconnection line；Asic chip, is covered on the through hole and positioned at the back side of the substrate, the asic chip is electrically connected with the interconnection line.MEMS chip encapsulating structure size is reduced, the integrated level of MEMS chip encapsulation is improved and is easy to MEMS chip to be electrically connected with the circuit of other yardsticks.
Description
Technical field
The utility model is related to semiconductor die package field, more particularly to MEMS (Micro Electro
Mechanical systems, MEMS) chip encapsulating structure.
Background technology
MEMS (Micro Electro Mechanical systems, MEMS) technology is built upon micron/receive
21 century cutting edge technology in rice technical foundation, refers to micrometer/nanometer material is designed, processed, manufactured, measures and controlled
Technology.Mechanical component, optical system, driving part, electric-control system can be integrated into the microsystem of an integral unit by it.
MEMS can not only gather, handle with sending information or instruction, additionally it is possible to according to acquired information independence or root
Taken action according to outside instruction.It uses the manufacturing process that microelectric technique and micro-processing technology are combined, and produces various
Excellent performance, cheap, miniaturization sensor, actuator, driver and micro-system, relative to traditional machinery, they
It is smaller, thickness is thinner, and the automating of system, intelligent and reliability level are higher.The application field phase of MEMS
When wide, the market demand is powerful, just falls over each other the focus of research and development as industry.
Due to MEMS chip size and routine millimeter or centimetre functional module between there is very big difference, therefore
Need to realize mutual transmission of the electric signal in the intermodule of different scale by encapsulating, in recent years, MEMS package technology is obtained
Very big progress, occurs in that numerous MEMS package technologies.
Utility model content
The problem of the utility model is solved is to provide MEMS chip encapsulating structure and method for packing, reduction MEMS chip envelope
Assembling structure size, improves the integrated level of MEMS chip encapsulation and is easy to MEMS chip to be electrically connected with the circuit of other yardsticks.
The utility model provides a kind of MEMS chip encapsulating structure, including：Be provided with substrate, the substrate through hole and
Interconnection line；MEMS chip, the front of the MEMS chip has functional areas and multiple weld pads positioned at functional areas periphery, described
Weld pad is electrically connected with the functional areas, and the MEMS chip is arranged at the front of the substrate and in the through hole, described
Weld pad is electrically connected with the interconnection line；Asic chip, is covered on the through hole and positioned at the back side of the substrate, described
Asic chip is electrically connected with the interconnection line.
It is preferred that, the front of the MEMS chip is provided with capping, and the capping has host cavity, and the host cavity is covered
The functional areas.
It is preferred that, the capping exposure weld pad, the substrate front side is provided with the first weldering of interconnection line electrical connection
Pad, the weld pad is electrically connected with first weld pad by metal wire.
It is preferred that, the encapsulating structure also includes plastic packaging layer, the plastic packaging layer filling through hole and the cladding MEMS
Chip and the metal wire.
It is preferred that, the back side of the substrate is provided with solder-bump, and the solder-bump is electrically connected with the interconnection line,
The solder-bump is used to electrically connect with external circuit.
It is preferred that, the height of the solder-bump is higher than the height of the asic chip.
It is preferred that, the asic chip upside-down mounting is on the substrate.
It is preferred that, the asic chip is electrically connected by soldered ball or metal projection with the interconnection line.
It is preferred that, the material of the substrate is silicon base or ceramics or glass substrate or pcb board.
The beneficial effects of the utility model are reduction MEMS chip encapsulating structure sizes, improve the integrated of MEMS chip encapsulation
Spend and be easy to MEMS chip to be electrically connected with the circuit of other yardsticks.
Brief description of the drawings
Fig. 1 is the utility model preferred embodiment MEMS chip encapsulating structure schematic diagram.
Fig. 2 is to Fig. 7 the utility model preferred embodiment MEMS chip method for packing schematic diagrames.
Embodiment
Embodiment of the present utility model is described in detail below with reference to accompanying drawing.But these embodiments are simultaneously
The utility model is not limited, structure, method or function that one of ordinary skill in the art is made according to these embodiments
On conversion be all contained in protection domain of the present utility model.
It should be noted that the purpose for providing these accompanying drawings is to help to understand embodiment of the present utility model, and
It should not be construed as improperly limiting of the present utility model.For the sake of becoming apparent from, size is not necessarily to scale shown in figure,
It may make and amplify, reduce or other changes.In addition, the three dimensions of length, width and depth should be included in actual fabrication
Size.In addition, fisrt feature described below second feature it " on " structure can be formed including the first and second features
For the embodiment directly contacted, embodiment of the other feature formation between the first and second features can also be included, so
First and second features may not be direct contact.
Fig. 1 is refer to, is the utility model preferred embodiment MEMS chip encapsulating structure schematic diagram, MEMS chip encapsulation knot
Structure includes：Substrate 1, with front and the back side relative to each other, is provided with through hole 13 and interconnection line (figure on substrate 1
In)；MEMS chip 2, with front and the back side relative to each other, the front of MEMS chip 2 has functional areas 211 and positioned at work(
Multiple weld pads 212 on the energy periphery of area 211, weld pad 212 is electrically connected with functional areas 211, and MEMS chip 2 is arranged at the front of substrate 1
And in through hole 13, weld pad 212 is electrically connected with interconnection line；Asic chip 3, is covered on through hole 13 and positioned at substrate 1
The back side, asic chip 3 is electrically connected with the interconnection line.
By the way that MEMS chip 2 is placed in the through hole 13 of substrate 1, reduces MEMS chip 2 and gather envelope with asic chip 3
The size of the encapsulating structure of dress, improves the integrated level of encapsulating structure.
It is provided with MEMS chip 2 in capping 23, capping 23 and is provided with host cavity 230, capping 23 is covered in MEMS chip 2
Front on, host cavity 230 covers functional areas 211, be MEMS chip 2 functional areas 211 build sealed environment.
In the present embodiment, the material of capping 23 is glass or silicon.Capping 23 passes through viscose or metal bonding mode
Covered with the front of MEMS chip 2.It can be vacuumized during both cover or realization is filled with host cavity 230
Gas required for the function of MEMS chip 2 is filled with electric insulation material, such as gel-like, oils in host cavity 230.
In the present embodiment, weld pad 212 is not contained among host cavity 230, and outside capping 23, in this way, side
Just weld pad 212 is electrically connected with interconnection line using routing technique formation metal wire.
The first weld pad 111 electrically connected with interconnection line, weld pad 212 and first are provided with the first surface 11 of substrate 1
Weld pad 111 is electrically connected by metal wire 24.
The material of metal wire 24 is one or more of combinations in gold, copper, aluminium, tungsten, or includes above-mentioned one or more
Metal alloy including material.
Plastic packaging layer 25 fills through hole 13 and cladding MEMS chip 2 and metal wire 24.
Plastic packaging layer 25 material for epoxy resin or plastic packaging glue etc. can for plastic packaging material.
Solder-bump 121 is provided with the back side of substrate 1, solder-bump 121 is electrically connected with interconnection line, solder-bump
121 are used to electrically connect with external circuit.
In the present embodiment, the height of solder-bump 121 is more than the height of asic chip 3.In this way, solder-bump 121 with
When the external circuit board is electrically connected, between the externally-located circuit board of asic chip 3 and substrate 1, the work of protection asic chip 3 is played
With.
The upside-down mounting of asic chip 3 is on the back side of substrate 1.Specifically, setting metal coupling (bump) on asic chip 3
31, there is the second weld pad 122, it is electric that the weld pad 122 of metal coupling 31 and second presses (bonding) on the second surface 12 of substrate 1
Connection.
Underfill 32 is provided with the chip of asic chip 3.
In the present embodiment, the first weld pad 111 and the second weld pad 122 can be the exposed pin of the interconnection line of substrate 1.
The material of substrate 1 is silicon base or ceramics or glass substrate or pcb board.
The preferred embodiment of the utility model one provides a kind of MEMS chip method for packing.Comprise the following steps：
Step 1, Fig. 2 is refer to there is provided substrate 1 and forms solder-bump 121 at the back side of substrate 1.
Substrate 1 has is provided with interconnection line (not illustrated in Fig. 3) on front and the back side relative to each other, substrate 1；Base
It is provided with the first weld pad 111 electrically connected with interconnection line, the second surface 12 of substrate 1 and sets on the first surface 11 of plate 1
Have and the second weld pad 122 is electrically connected with interconnection line.Through hole 13 is provided with substrate 1.Multiple latticed arrangements of substrate 1 form big base
Plate, large substrates can be integrally formed, and be separated multiple substrates 1 each other by cutting technique in subsequent technique.
Solder-bump 121 is electrically connected with interconnection line, and solder-bump 121 is used to electrically connect with external circuit.Solder-bump
121 can be BGA types, and silk-screen printing technique using solder alloy or by planting ball technique or by electroplating technology shape
Into.BGA (ball grid array) interconnection be generally by welding or partial melting metal ball to it is being formed on bond pad, for it is right
Deng the round conductor of conductor formation contact physically and electrically.Alternatively, SMT interconnection can be conducting metal post (such as copper).
Step 2, refer to Fig. 3, using reverse installation process on the back side of substrate 1 upside-down mounting asic chip 3 and asic chip 3 covers
It is placed on through hole 13.
Metal coupling (bump) 31 is set on asic chip 3, and the weld pad 122 of metal coupling 31 and second is pressed (bonding)
Electrical connection.Or the weld pad 122 of asic chip 3 and second passes through ball bond.
Step 3, Fig. 4 is refer to, underfill 32 is formed on asic chip 3 using underfill adhesive process.
Step 4, Fig. 5 is refer to there is provided MEMS chip, and MEMS chip 2 is arranged at the front of substrate 1 and is placed on
In through hole 13.
MEMS chip 2 has front and the back side relative to each other, and the front of MEMS chip 2 has functional areas 211 and position
Multiple weld pads 212 in the periphery of functional areas 211.
There is provided and host cavity 230 is provided with capping 23, capping 23, capping 23 is covered on the front of MEMS chip 2, is housed
Chamber 230 covers functional areas 211.Weld pad 212 is not contained among host cavity 230, and outside capping 23.
In the present embodiment, the material of capping 23 is silicon, and MEMS chip 2 can use the work of wafer scale with covering for capping 23
Skill, i.e. MEMS chip wafer are covered with cover wafer, and MEMS chip wafer is by the latticed arrangement of multiple MEMS chips, cover wafer
By the latticed arrangement of multiple cappings with host cavity, then cover wafer is caused to expose weld pad 212 using etching technics, so
Cutting is carried out afterwards forms the structure that single MEMS chip is covered with capping 23.
Step 5, Fig. 6 is refer to, because asic chip 3 has been covered on through hole 13 and is located at the back side of substrate 1, because
This, MEMS chip 2 can be using asic chip 3 as loading plate, then, using routing technique formation metal wire 24, metal wire 24
Two ends electrically connected respectively with the weld pad 111 of weld pad 212 and first.
Step 6, Fig. 7 is refer to, plastic packaging layer 25 is formed on the front of substrate 1 using plastic package process, plastic packaging layer 25 is filled
Through hole 13 and cladding MEMS chip 2 and metal wire 24.
In the present embodiment, the also cladding capping 23 of plastic packaging layer 25 simultaneously forms flat top surface.
Plastic packaging layer material for epoxy resin or plastic packaging glue etc. can for plastic packaging material.
Finally, MEMS chip encapsulating structure as shown in Figure 1 is formed by cutting technique.
The utility model uses the technology for being fanned out to (fan-out) wafer-class encapsulation WLP types, and it allows to manufacture component
Do not limited by die size.The encapsulation is realized on silicon unlike being handled with traditional WLP, but comes from artificial chip
Shaped support.During the starting stage of technique, the stripping and slicing component from chip (such as silicon wafer) is changed into artificial or reconstruct
Carrier.
It should be understood that, although the present specification is described in terms of embodiments, but not each embodiment only includes one
Individual independent technical scheme, this narrating mode of specification is only that for clarity, those skilled in the art will should say
Bright book is as an entirety, and the technical scheme in each embodiment may also be suitably combined to form those skilled in the art can
With the other embodiment of understanding.
The a series of tool described in detail only for feasibility embodiment of the present utility model of those listed above
Body illustrates that they are simultaneously not used to limit protection domain of the present utility model, all to be made without departing from the utility model skill spirit
Equivalent implementations or change should be included within protection domain of the present utility model.
Claims (9)
1. a kind of MEMS chip encapsulating structure, it is characterised in that including：
Through hole and interconnection line are provided with substrate, the substrate；
MEMS chip, the front of the MEMS chip has functional areas and multiple weld pads positioned at functional areas periphery, the MEMS
Chip is arranged at the front of the substrate and in the through hole, and the weld pad is electrically connected with the interconnection line；ASIC cores
Piece, is covered on the through hole and positioned at the back side of the substrate, the asic chip is electrically connected with the interconnection line.
2. MEMS chip encapsulating structure according to claim 1, it is characterised in that the front of the MEMS chip is provided with
Capping, the capping has host cavity, and the host cavity covers the functional areas.
3. MEMS chip encapsulating structure according to claim 2, it is characterised in that the capping exposes the weld pad, institute
The first weld pad that substrate front side is provided with interconnection line electrical connection is stated, the weld pad is electrically connected with first weld pad by metal wire
Connect.
4. MEMS chip encapsulating structure according to claim 3, it is characterised in that the encapsulating structure also includes plastic packaging
Layer, the plastic packaging layer filling through hole and the cladding MEMS chip and the metal wire.
5. MEMS chip encapsulating structure according to claim 1, it is characterised in that the back side of the substrate is provided with welding
Projection, the solder-bump is electrically connected with the interconnection line, and the solder-bump is used to electrically connect with external circuit.
6. MEMS chip encapsulating structure according to claim 5, it is characterised in that the height of the solder-bump is higher than institute
State the height of asic chip.
7. MEMS chip encapsulating structure according to claim 1, it is characterised in that the asic chip upside-down mounting is in the base
On plate.
8. MEMS chip encapsulating structure according to claim 7, it is characterised in that the asic chip by soldered ball or
Metal projection is electrically connected with the interconnection line.
9. MEMS chip encapsulating structure according to claim 1, it is characterised in that the material of the substrate be silicon base or
Person's ceramics or glass substrate or pcb board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621402964.XU CN206417858U (en) | 2016-12-20 | 2016-12-20 | MEMS chip encapsulating structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621402964.XU CN206417858U (en) | 2016-12-20 | 2016-12-20 | MEMS chip encapsulating structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206417858U true CN206417858U (en) | 2017-08-18 |
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ID=59575554
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201621402964.XU Active CN206417858U (en) | 2016-12-20 | 2016-12-20 | MEMS chip encapsulating structure |
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| Country | Link |
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| CN (1) | CN206417858U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106744646A (en) * | 2016-12-20 | 2017-05-31 | 苏州晶方半导体科技股份有限公司 | MEMS chip encapsulating structure and method for packing |
-
2016
- 2016-12-20 CN CN201621402964.XU patent/CN206417858U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106744646A (en) * | 2016-12-20 | 2017-05-31 | 苏州晶方半导体科技股份有限公司 | MEMS chip encapsulating structure and method for packing |
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