CN206040621U - Semiconductor chip encapsulation structure - Google Patents
Semiconductor chip encapsulation structure Download PDFInfo
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- CN206040621U CN206040621U CN201620571708.7U CN201620571708U CN206040621U CN 206040621 U CN206040621 U CN 206040621U CN 201620571708 U CN201620571708 U CN 201620571708U CN 206040621 U CN206040621 U CN 206040621U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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Abstract
The utility model provides a semiconductor chip encapsulation structure, this packaging structure includes: a semiconductor chip has first surface and the second surface carried on the back mutually each other, the first surface has a plurality of first weld pads, the 2nd semiconductor chip has the third surface and the fourth surface of carrying on the back mutually each other, the third surface has a plurality of second weld pads, a semiconductor chip with the 2nd semiconductor chip counterpoint pressfitting, the first surface with the third surface each other relatively just first weld pad with the position one -to -one of second weld pad, the position that corresponds first weld pad on the second surface has the through -hole, the through -hole pierces through first weld pad and the second weld pad, perhaps, the through -hole pierces through first weld pad just the bottom of through -hole exposes the second weld pad, have conducting structure in the through -hole, make first weld pad with second weld pad electricity is connected. Realize that semiconductor chip and semiconductor chip directly interconnect.
Description
Technical field
This utility model is related to technical field of semiconductors, more particularly to the encapsulation technology of semiconductor chip.
Background technology
In recent years, advanced packaging started appearance in IC manufacturings, and such as multi-chip module (MCM) is exactly to incite somebody to action
Multiple IC chips are packaged by function combinations, and particularly three-dimensional (3D) encapsulation breaks through the concept of traditional planar package first,
Packaging efficiency up to more than 200%.It makes to stack multiple chips in single package body, realizes the multiplication of memory capacity,
Industry is referred to as laminated type 3D encapsulation；Secondly, chip direct interconnection, interconnection length are significantly shortened by it, and signal transmission is obtained more
It is fast and be disturbed less；Moreover, it by it is multiple difference in functionalitys chip-stacked together, make single package body realize more work(
Can, so as to form System on Chip/SoC encapsulation new approaches；Finally, using 3D encapsulate chip it is also low in energy consumption, speed is fast the advantages of, this
The size and weight of electronics and IT products is made to reduce decades of times.Possess unrivaled technical advantage just because of 3D encapsulation,
The packaged type for making this new possesses wide development space.
Modal bare dies stacking 3D encapsulation first by the qualified chip back-off of growth salient point and is welded on film substrate,
The material of this film substrate is ceramics or expoxy glass, has conductor wiring thereon, and also there is interconnection solder joint inside, and both sides also have outer
Portion interconnects solder joint, and multiple film substrates are carried out closed assembly interconnection again then.
The technological process of multi-chip module (MCM) lamination is basically identical with the technological process of bare dies stacking.Except above-mentioned side
Using outside interconnection mode, lamination 3D encapsulation also has various interconnection modes to the welding of edge conductor, and such as wire bonding laminated chips are exactly
A kind of employing Wire Bonding Technology realizes lamination interconnection, and the scope of application of the method is wider.Additionally, lamination interconnection process is also
There are the modes such as lamination carrier band, folded flexible circuitry.Lamination carrier band is to realize that IC is interconnected with tape automated bonding (TAB), can be further
It is divided into printed circuit board (PCB) (PCB) lamination TAB and lead frame TAB.Folded flexible circuitry mode is that bare chip is arranged on soft first
On property material, then folded, so as to form the packing forms of 3-D stacks.
MEMS (Micro Electro Mechanical System MEMS), be merged silicon micromachined,
Various process technologies such as LIGA and precision optical machinery processing, and the microsystem constituted using modern information technologies.Complete microcomputer
The one that electric system is made up of the part such as microsensor, microactrator, signal processing and control circuit, communication interface and power supply
The microdevice system of change.The acquisition of information, process and execution are integrated, composition has multi-functional microsystem,
It is integrated in large scale system, so as to the automatization that system is significantly increased, intelligent and reliability level.Along system and
Product miniaturization, intellectuality, integrated developing direction, it is contemplated that MEMS can bring a skill to human society
Art revolution.Through the development of more than ten years, MEMS chip is quite ripe, but, many chips but do not obtain practical application,
Its main cause is exactly not solve the problems, such as encapsulation.Traditional MEMS package mode is Metal Packaging and ceramic package, not only body
Product is big, and cost is also very high, often accounts for the 50～80% of whole MEMS cost, limits MEMS technology in Price Sensitive
The application in the high consumer electronics market of degree.
With the miniaturization of semi-conductor industry electronic device and the increase of circuit integration density, chip size packages technology
(CSP) developed rapidly, its package dimension is similar to die size.Definition of the U.S. JEDEC to CSP be：Core
Piece package area is referred to as CSP less than or equal to the encapsulation of chip area 120%.With traditional encapsulation technology such as wire bonding,
Automatically band carries combined techniqueses (TAB), flip-chip etc. and compares, and CSP has advantages below：1. the microminiature of near chip size is sealed
Dress；2. protect bare chip；3. it is electric, hot excellent；4. packaging density is high；5. it is easy to test；6. it is easy to weld, install and repair more
Change.Chip size packages directly can be packaged on a single chip, it is also possible to after being packaged on full wafer wafer, then
The wafer cutting for having encapsulated obtains encapsulating chip, and size of the chip for encapsulating with nude film on X/Y directions is completely the same.It is latter
The mode of kind is referred to as crystal wafer chip dimension encapsulation (WLCSP).
Crystal wafer chip dimension encapsulation is typically divided the weld pad of periphery arrangement on semiconductor chip by redistribution process
A large amount of metal soldered balls that cloth is arranged into face battle array, sometimes referred to as solder bump.Due to it be first packaged on full wafer wafer and
Test, then cuts again, thus has more obvious advantage：It is that technique process optimizes significantly first, wafer is directly entered encapsulation
Operation；And traditional handicraft will be carried out cutting, be classified to wafer before encapsulation；All integrated circuits are once encapsulated, and mark work
Directly carry out on wafer, packaging and testing are once completed, and are different from traditional packaging technology；Production cycle and cost decline to a great extent.
How size that multi-chip integrate encapsulation is reduced？How packaging cost that multi-chip integrate encapsulation is reduced？How will
Wafer level packaging is applied in the integration encapsulation of multi-chip？Become those skilled in the art and bite technical problem to be solved.
Utility model content
The problem that this utility model is solved is to provide the stacked package of a kind of new semiconductor chip and semiconductor chip
Structure, further increases integrated level, the size for reducing encapsulating structure and packaging cost.
This utility model provides a kind of semiconductor chip package, and the encapsulating structure includes：First semiconductor chip,
With first surface away from one another and second surface, the first surface has multiple first weld pads；Second semiconductor core
Piece, with the 3rd surface away from one another and the 4th surface, the 3rd surface has multiple second weld pads；Described the first half
Conductor chip is pressed with the second semiconductor chip para-position, and the first surface is relative to each other and described with the 3rd surface
First weld pad is corresponded with the position of second weld pad；On the second surface, the position of the first weld pad of correspondence has logical
Hole；The through hole penetrates first weld pad and second weld pad, or, the through hole penetrates first weld pad and institute
State the second weld pad described in the bottom-exposed of through hole；There is in the through hole conductive structure, first weld pad and described second is made
Weld pad is electrically connected.
Preferably, the first surface is provided with the first functional areas, and the plurality of first weld pad is located at first function
Around area；3rd surface is provided with the second functional areas, and the plurality of second weld pad is located at the week of second functional areas
Enclose；Support unit is provided between the first surface and the 3rd surface, the first surface is made with the 3rd surface
Between formed interval.
Preferably, the material of the support unit is photoresists.
Preferably, first semiconductor chip has the first substrate, and first substrate is arranged with first weld pad
There is in first substrate and between first substrate and first weld pad passivation layer；The through hole includes that first leads to
Hole and the second through hole connected with the first through hole；The first through hole penetrates first substrate；Second through hole
Penetrate the passivation layer, first weld pad and second weld pad, or, second through hole penetrate the passivation layer,
First weld pad and second via bottoms exposure, second weld pad.
Preferably, the side wall and the second surface of the first through hole has insulating barrier, and the conductive structure is located at
On the insulating barrier.
Preferably, the conductive structure includes：Wiring layer again, the wiring layer again be formed at the side wall of the through hole and
Bottom simultaneously extends to the second surface, and the wiring layer again is electrically connected with first weld pad, the second weld pad；Positioned at described logical
Solder mask on hole and the second surface, the solder mask cover described in wiring layer again；It is provided with out on the solder mask
Mouthful, the opening on the second surface, wiring layer again described in the open bottom exposure；Weldering is provided with the opening
Projection is connect, the solder-bump is electrically connected with the wiring layer again.
Preferably, the material of the insulating barrier is photoresists or silica membrane.
Preferably, first weld pad includes at least two metal layers, and the metal level is electrically connected with adjacent metal level,
There is between metal level and metal level dielectric layer.
Preferably, there is on first weld pad perforate, the position of the perforate is corresponding with the position of the first through hole,
The perforate penetrates the metal level and the dielectric layer, is filled with dielectric material in the perforate.
The beneficial effects of the utility model are by Wafer level packaging is applied to semiconductor chip and semiconductor core
In the interconnection package of piece, semiconductor chip and semiconductor chip direct interconnection is realized, multi-chip is folded in eliminating background technology
The support plate (such as film substrate) used is needed in layer encapsulation, is reduced packaging cost, is improve integrated level, reduces package dimension
And reduce packaging cost.
Description of the drawings
Fig. 1 is the structural representation of the first wafer of this utility model preferred embodiment and the second wafer；
Fig. 2 is the structural representation that the first wafer of this utility model preferred embodiment and the second Wafer alignment are pressed；
Fig. 3 is the thinning structural representation of the first wafer of this utility model preferred embodiment；
Fig. 4 is the structural representation that this utility model preferred embodiment forms through hole；
Fig. 4 (a) is the structural representation that this utility model preferred embodiment forms groove and cutting groove；
Fig. 4 (b) is the structural representation that this utility model preferred embodiment forms hole in groove；
Fig. 5 (a) is preferable to carry out the structural representation of the first weld pad for utility model；
Fig. 5 (b) is the structural representation that this utility model preferred embodiment forms insulating barrier；
Fig. 5 (c) is the structural representation that this utility model preferred embodiment forms the second through hole；
Structural representations of the Fig. 6 (a) for another the first weld pad of embodiment of this utility model；
Fig. 6 (b) is the structural representation of another embodiment Etch Passivation of this utility model and the first weld pad；
Fig. 6 (c) is the structural representation that support unit is punched in another embodiment laser boring of this utility model；
Fig. 6 (d) is the structural representation that another embodiment of this utility model forms insulating barrier；
Fig. 7 is the structural representation that this utility model preferred embodiment forms again wiring layer；
Fig. 8 is the structural representation that this utility model preferred embodiment is cut along cutting groove；
Fig. 9 is the structural representation that this utility model preferred embodiment forms solder mask；
Figure 10 is the structural representation that this utility model preferred embodiment forms solder-bump；
Figure 11 is this utility model single finished product encapsulating structure schematic diagram.
Specific embodiment
Specific embodiment of the present utility model is described in detail below with reference to accompanying drawing.But these embodiments are simultaneously
This utility model is not limited, structure, method or function that one of ordinary skill in the art is made according to these embodiments
On conversion be all contained in protection domain of the present utility model.
It should be noted that the purpose for providing these accompanying drawings is to contribute to understanding embodiment of the present utility model, and
Should not be construed as and improperly limit to of the present utility model.For the sake of becoming apparent from, shown in figure, size is not necessarily to scale,
May make and amplify, reduce or other changes.Additionally, should the three dimensions comprising length, width and depth in actual fabrication
Size.In addition, fisrt feature described below second feature it " on " structure can be formed including the first and second features
For the embodiment of directly contact, it is also possible to be formed in the embodiment between the first and second features including other feature, so
First and second features may not be directly contact.
This utility model provides a kind of method for packing of two semiconductor chip interconnection packages and encapsulating structure, develops
The semiconductor chip of wafer scale and the encapsulation technology of semiconductor chip interconnection package, realize two and half using silicon hole technique and lead
The direct interconnection of body chip, and the company of semiconductor chip and semiconductor chip in prior art, is realized by substrate joining interconnection
Logical, this utility model eliminates substrate, the integrated level that improve encapsulating structure, the size for reducing encapsulating structure, simplifies envelope
Dress technique, has saved packaging cost.
Fig. 1-Figure 10 is refer to, is the method for packing schematic diagram that two wafer level semiconductor chips realize interconnection package.
Realize that two wafer level semiconductor chip interconnection packages are comprised the steps of：
Refer to Fig. 1, there is provided the first wafer 10, the first wafer 10 has first surface 101 away from one another and the second table
Face 102, the first wafer 10 have the first semiconductor chip 1 of multiple latticed arrangements, and each first semiconductor chip 1 has
One the first functional areas 100 and multiple first weld pads 11 being centered around around the first functional areas 100, the first functional areas 100 with
And first weld pad 11 be located on first surface 101, between each first semiconductor chip 1 and the first adjacent semiconductor chip 1
With Cutting Road, convenient follow-up cutting is separated；The second wafer 20 is provided, the second wafer 20 has the 3rd surface away from one another
203 and the 4th surface 204, the second wafer 20 has the second semiconductor chip 2 of multiple latticed arrangements, each second quasiconductor
Chip 2 has second functional areas 200 and multiple second weld pads 22 being centered around around the second functional areas 200, the second work(
Can area 200 and the second weld pad 22 be located on the 3rd surface 203, each second semiconductor chip 2 and the second adjacent quasiconductor
There is between chip 2 Cutting Road, convenient follow-up cutting is separated.
Fig. 2 is refer to, the first wafer 10 and 20 para-position of the second wafer are pressed, first surface 101 and the 3rd surface 203 is made
Toward each other, and the first weld pad 11 and the second weld pad 22 position correspond.
In order to avoid the para-position pressing of two wafers makes the first functional areas 100 or the second functional areas 200 suffer that touching is ruined
Damage, before by two Wafer alignment pressings, form support unit 30 on first surface 101 or the 3rd surface 203.
In the present embodiment, the material of support unit 30 is photoresists, is formed at first surface by exposure imaging technique
On 101 or on the 3rd surface 203.
Support unit 30 is latticed, each the first functional areas 100 (or second functional areas 200) one net of correspondence
Lattice.After the first wafer 10 and 20 para-position of the second wafer pressing, support unit 30 is located between the two, makes first surface 101
Interval is formed between the 3rd surface 203.
First wafer 10, the second wafer 20 and support unit 30 are surrounded and form multiple annular seal spaces, each sealing intracavity
With first functional areas 100 and second functional areas 200.Support unit 30 is located at the first weld pad 11 and the second weld pad
Between 22.
Fig. 3 is refer to, the second surface 102 of the first wafer 10 is ground so that the thickness of the first wafer 10 is subtracted by D
It is little to d, the convenient etching through hole on the first wafer 10.
Then, on second surface 102, the position of the first weld pad 11 of correspondence forms through hole 12, and through hole 12 penetrates the first weld pad
11, and 12 the second weld pad of bottom-exposed 22 of through hole.
In another embodiment of the present utility model, through hole 12 penetrates the first weld pad 11, and, through hole 12 penetrates the second weld pad
22。
Fig. 4 is refer to, the first wafer 10 has the first substrate 13, and the first weld pad 11 is formed in the first substrate 13, first
The material of substrate 13 is silicon, has passivation layer 14, using etching technics first between the first substrate 13 and the first weld pad 11
The first through hole 121 for penetrating the first substrate 13,121 bottom-exposed passivation layer 14 of first through hole is formed in substrate 13.
The cross sectional shape of first through hole 121 can be inverted trapezoidal type hole or step type hole.
In the present embodiment, the cross sectional shape of first through hole 121 is step type hole, refer to Fig. 4 (a)-Fig. 4 ()
Fig. 4 (a) is refer to, the groove 1211 of inverted ladder type, multiple first weld pads 11 are shaped as by etching technics Formation cross-section
The lower section of groove 1211 is arranged in, the depth of groove 1211 is less than the thickness d of the first wafer.In the present embodiment, in etching groove 1211
While also synchronously etched cutting groove 1213.
Fig. 4 (b) is refer to, multiple independent holes 1212, the position in hole 1212 are formed in groove 1211 by etching technics
Correspond with the position of the first weld pad 11, the bottom-exposed passivation layer 14 in hole 1212.
Fig. 5 (a) is refer to, is subregional enlarged diagram in the middle part of Fig. 4.In the present embodiment, the first weld pad 11 include to
Few two metal layers, each metal level are electrically connected with adjacent metal level, and, there is between metal level and metal level dielectric layer.
Fig. 5 (b) is refer to, it is after the step of performing Fig. 4, logical in second surface 102 and first using coating process
Insulating barrier 15 is formed on the side wall in hole 121 and bottom, and the material of insulating barrier can be photoresists.
Fig. 5 (c) is refer to, after the step of performing Fig. 5 (b), the second through hole 122 is formed using laser boring technique,
Second through hole 122 punches passivation layer 14, the first weld pad 11, support unit 30, and second weld pad of bottom-exposed of the second through hole 122
22。
In another embodiment of the present utility model, the second through hole 122 punches the second weld pad 22.
Fig. 6 (a) is refer to, is subregional enlarged diagram in the middle part of Fig. 4.In the present embodiment, the first weld pad 11 include to
Few two metal layers, each metal level are electrically connected with adjacent metal level, and, there is between metal level and metal level dielectric layer.
There is on first weld pad 11 perforate 111 for penetrating the first weld pad 11, the position of perforate 111 is corresponding with the position of first through hole 121,
Perforate 111 penetrates all metal levels, is filled with dielectric material in perforate 111.
Fig. 6 (b) is refer to, the position using correspondence perforate on etching technics Etch Passivation 14 and the first weld pad 11 is straight
To exposure support unit 30.
In another embodiment of the present utility model, using correspondence on etching technics Etch Passivation 14, the first weld pad 11
The position of perforate, support unit 30 simultaneously expose the second weld pad 22.
Refer to Fig. 6 (c), perform Fig. 6 (b) the step of after, using laser boring technique punch support unit 30 and
Expose the second weld pad 22.
In another embodiment of the present utility model, after the step of performing Fig. 6 (b), punched using laser boring technique
Support unit 30 and punch the second weld pad 22.
Fig. 6 (d) is refer to, using pecvd process on the second surface 102 of the first wafer 10 and first through hole 121
Side wall forms insulating barrier 15.The material of insulating barrier 15 is silica membrane.
Refer to Fig. 7, wiring layer 16 again formed using RDL techniques, then wiring layer 16 be formed at through hole 12 side wall and
Bottom simultaneously extends to second surface 102, realizes again wiring layer 16 and electrically connects with the first weld pad 11 and the second weld pad 22.
Fig. 8 is refer to, is cut along cutting groove 1213 using cutting technique, formed and precut groove 1214, with pre-cut
Cut during groove 1214 cuts support unit 30 but do not penetrate support unit 30.
Fig. 9 is refer to, solder mask 17, solder mask 17 are formed in second surface 102 and through hole 12 using coating process
Material be the green paint of welding resistance.And opening 18 is formed on solder mask 17 using exposure imaging technique, opening 18 is located at the first wafer
On 10 second surface 102, be open 18 bottom-exposed wiring layer 16 again.
Figure 10 is refer to, and solder-bump 19, solder-bump 19 and wiring layer again is formed in opening 18 using ball technique is planted
16 electrical connections.
Figure 11 is refer to, after the encapsulation of wafer scale, is cut along precut groove 1214 using cutting technique, until
The second wafer 20 is cut through, and the interconnection package for the first single semiconductor chip 1 being obtained with the second single semiconductor chip 2 is tied
Structure, encapsulating structure include：First semiconductor chip 1, with first surface 101 away from one another and second surface 102, first
There are on surface 101 first functional areas 100 and multiple first weld pads 11 around the first functional areas 100；Second semiconductor core
Piece 2, with the 3rd surface 203 away from one another and the 4th surface 204, on the 3rd surface 203 have the second functional areas 200 with
And around multiple second weld pads of the second functional areas 200；First semiconductor chip 1 and 2 para-position of the second semiconductor chip pressing, the
One surface 101 and 203 relative to each other and the first weld pad 11 and the second weld pad 22 position of the 3rd surface correspond；Second surface
On 102, the position of the first weld pad 11 of correspondence has through hole 12；Through hole 12 penetrates the bottom-exposed of the first weld pad 11 and through hole 12
Two weld pads 22；There is in through hole 12 conductive structure, the first weld pad 11 is electrically connected with the second weld pad 22.
In another embodiment of the present utility model, through hole 12 penetrates the first weld pad 11 and penetrates the second weld pad 22.
In order to prevent the 200 touched abrasion of the first functional areas 100 or the second functional areas, in first surface 101 and the 3rd
Support unit 30 is provided between surface 203, makes to form interval between first surface 101 and the 3rd surface 203.
Preferably, the material of support unit 30 is photoresists.
First semiconductor chip 1 has the first substrate 13, and the first weld pad 11 is arranged in the first substrate 13 and the first substrate
13 and first have passivation layer 14 between weld pad 11.
The second through hole 122 that through hole 12 is included first through hole 121 and connected with first through hole 121；First through hole 121 is worn
Saturating first substrate 13；Second through hole 122 penetrates passivation layer 14, the first weld pad 11, and 122 the second weld pad of bottom-exposed of the second through hole
22。
In another embodiment of the present utility model, the second through hole 122 penetrates passivation layer 14, the first weld pad 11 and second
Weld pad 22.
The second surface 102 of the side wall of first through hole 121 and the first semiconductor chip 1 has insulating barrier 15, conductive knot
Structure is located on insulating barrier 15.
Conductive structure includes：
Wiring layer 16, then wiring layer again 16 are formed at the side wall of through hole 12 and bottom and extend to second surface 102, then
Wiring layer 16 is electrically connected with the first weld pad 11, the second weld pad 22；
Solder mask 17 on through hole 12 and second surface 102, solder mask 17 cover wiring layer 16 again；
It is provided with opening 18 on solder mask 17, opening 18 is located on second surface 102,18 bottom-exposeds of opening wiring layer again
16；
Solder-bump 19 is provided with opening 18, solder-bump 19 is electrically connected with wiring layer 16 again.
The material of insulating barrier 15 is photoresists or silica membrane or anti-welding green paint.
First weld pad 11 includes at least two metal layers, and in the present embodiment, the first weld pad 11 includes at least two metal layers,
Each metal level is electrically connected with adjacent metal level, and, there is between metal level and metal level dielectric layer 110.
In another embodiment of the present utility model, there is on the first weld pad 11 perforate for penetrating the first weld pad 11, perforate
Position it is corresponding with the position of first through hole 121, perforate penetrates all metal levels, in perforate be filled with dielectric material.
It should be understood that, although this specification is been described by according to embodiment, but not each embodiment only includes one
Individual independent technical scheme, this narrating mode of description is only that those skilled in the art will should say for clarity
Bright book as an entirety, the technical scheme in each embodiment can also Jing it is appropriately combined, forming those skilled in the art can
With the other embodiment for understanding.
Those listed above is a series of to describe the tool for being only for feasibility embodiment of the present utility model in detail
Body illustrates that they are simultaneously not used to limit protection domain of the present utility model, all to be made without departing from this utility model skill spirit
Equivalent implementations or change are should be included within protection domain of the present utility model.
Claims (9)
1. a kind of semiconductor chip package, it is characterised in that the encapsulating structure includes：
First semiconductor chip, with first surface away from one another and second surface, the first surface has multiple
One weld pad；
Second semiconductor chip, with the 3rd surface away from one another and the 4th surface, the 3rd surface has multiple
Two weld pads；
First semiconductor chip is pressed with the second semiconductor chip para-position, the first surface and the 3rd surface
Relative to each other and first weld pad is corresponded with the position of second weld pad；
On the second surface, the position of the first weld pad of correspondence has through hole；
The through hole penetrates first weld pad and second weld pad, or, the through hole penetrate first weld pad and
Second weld pad described in the bottom-exposed of the through hole；
There is in the through hole conductive structure, first weld pad is electrically connected with second weld pad.
2. semiconductor chip package according to claim 1, it is characterised in that the first surface is provided with first
Functional areas, the plurality of first weld pad are located at around first functional areas；
3rd surface is provided with the second functional areas, and the plurality of second weld pad is located at around second functional areas；
Support unit is provided between the first surface and the 3rd surface, the first surface is made with the 3rd surface
Between formed interval.
3. semiconductor chip package according to claim 2, it is characterised in that the material of the support unit is sense
Optical cement.
4. semiconductor chip package according to claim 1, it is characterised in that first semiconductor chip has
First substrate, first substrate are arranged in first substrate with first weld pad and first substrate and described
There is between one weld pad passivation layer；
The second through hole that the through hole is included first through hole and connected with the first through hole；
The first through hole penetrates first substrate；
Second through hole penetrates the passivation layer, first weld pad and second weld pad, or, second through hole
Penetrate the passivation layer, first weld pad and second via bottoms and expose second weld pad.
5. semiconductor chip package according to claim 4, it is characterised in that the side wall of the first through hole and
The second surface has insulating barrier, and the conductive structure is located on the insulating barrier.
6. semiconductor chip package according to claim 1, it is characterised in that the conductive structure includes：
Wiring layer again, the wiring layer again are formed at the side wall of the through hole and bottom and extend to the second surface, institute
State again wiring layer to electrically connect with first weld pad, the second weld pad；
Solder mask on the through hole and the second surface, the solder mask cover described in wiring layer again；
Opening is provided with the solder mask, the opening is located on the second surface, described in the open bottom exposure again
Wiring layer；
Solder-bump is provided with the opening, and the solder-bump is electrically connected with the wiring layer again.
7. semiconductor chip package according to claim 5, it is characterised in that the material of the insulating barrier is photosensitive
Glue or silica membrane.
8. semiconductor chip package according to claim 4, it is characterised in that first weld pad includes at least two
Layer metal level, the metal level are electrically connected with adjacent metal level, have dielectric layer between metal level and metal level.
9. semiconductor chip package according to claim 8, it is characterised in that have on first weld pad and open
Hole, the position of the perforate are corresponding with the position of the first through hole, and the perforate penetrates the metal level and the medium
Layer, is filled with dielectric material in the perforate.
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| CN201620571708.7U CN206040621U (en) | 2016-06-15 | 2016-06-15 | Semiconductor chip encapsulation structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105977222A (en) * | 2016-06-15 | 2016-09-28 | 苏州晶方半导体科技股份有限公司 | Semiconductor chip packaging structure and packaging method |
| CN107176586A (en) * | 2017-07-06 | 2017-09-19 | 苏州晶方半导体科技股份有限公司 | A kind of encapsulating structure and method for packing of MEMS chip and ASIC |
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2016
- 2016-06-15 CN CN201620571708.7U patent/CN206040621U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105977222A (en) * | 2016-06-15 | 2016-09-28 | 苏州晶方半导体科技股份有限公司 | Semiconductor chip packaging structure and packaging method |
| CN105977222B (en) * | 2016-06-15 | 2019-09-17 | 苏州晶方半导体科技股份有限公司 | Semiconductor chip package and packaging method |
| CN107176586A (en) * | 2017-07-06 | 2017-09-19 | 苏州晶方半导体科技股份有限公司 | A kind of encapsulating structure and method for packing of MEMS chip and ASIC |
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