CN106024766A - High-stack wafer system level packaging structure and preparation method - Google Patents
High-stack wafer system level packaging structure and preparation method Download PDFInfo
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- CN106024766A CN106024766A CN201610567785.XA CN201610567785A CN106024766A CN 106024766 A CN106024766 A CN 106024766A CN 201610567785 A CN201610567785 A CN 201610567785A CN 106024766 A CN106024766 A CN 106024766A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The invention relates to a high-stack wafer system level packaging structure and a preparation method. The high-stack wafer system level packaging structure comprises a first packaging structure obtained by cutting a wafer-level chip size package, and at least one second packaging structure stacked on the first packaging structure, wherein the first packaging structure comprises a wafer chip and a first functional chip which is plastically encapsulated on the wafer chip through a wafer chip plastic-sealing body, a wafer chip connecting ball is arranged on the wafer chip plastic-sealing body, the second packaging structure comprises a PCB substrate and a second functional chip, a substrate connecting ball is arranged on a substrate plastic-sealing body, and a lower layer signal connecting line and a lower layer signal connecting port are arranged on the back side of the PCB substrate. The second packaging structure is aligned with the wafer chip connecting ball of the first packaging structure through the lower layer signal connecting port, and the second packaging structure can be stacked on the first packaging structure through surface mounting process. The high-stack wafer system level packaging structure is compact in structure, large in system capacity and wide in application scope, a multi-chip packaging structure is realized, and the packaging production efficiency is effectively improved.
Description
Technical field
The present invention relates to a kind of encapsulating structure and preparation method, especially a kind of high stacking wafer system-in-package structure and preparation method, belong to the technical field of semiconductor packages.
Background technology
Wafer stage chip encapsulation (WL-CSP) technology be full wafer wafer is packaged test after again cutting obtain the technology of single finished product chip, the chip size after encapsulation is consistent with nude film.Wafer stage chip encapsulation technology changes conventional package, such as ceramic leadless chip carrier, organic leadless chip carrier and the pattern of digital camera modular, has complied with that market is the lightest to microelectronic product, thin, short, little and low priceization requirement.Chip size after wafer stage chip encapsulation technology has reached to be highly miniaturized, and chip cost is along with the reduction of chip size and the increase of wafer size and significant reduction.Wafer stage chip encapsulation technology be IC can be designed, technology that wafer manufacture, packaging and testing, basic plate manufacture integrate, be focus and the trend of future development in current encapsulation field.
Stacked package is a kind of good way realizing miniaturization with high integration degree.In stacked package, encapsulation in encapsulation (PiP) with encapsulation outer package (PoP) more and more important to Packaging Industry, particularly mobile phone apply because this technology stackable go out highdensity logical device.PoP product has two encapsulation, a top being encapsulated in another, two encapsulation is combined with soldered ball.Logic element and memory components are integrated in different encapsulation by this encapsulation respectively, and such as, mobile phone just uses PoP encapsulation to come integrated application processor and memory.PoP encapsulation overcomes the major defect of crystal grain stacking, and such as supply chain problem, production yield loss, crystal grain profit be low and some other problem.
There is the advantages such as low cost, package dimension be less, the motility being mixed and matched logic and assembling of multiple memory due to PoP encapsulation, in industry, the demand to PoP encapsulation is constantly increasing, but prior art its size after finally having encapsulated is identical with chip size, its technique and encapsulating structure determine it and can only be packaged single-chip, cannot be carried out the encapsulation of multi-chip, more cannot realize the stacked package of multiple packaging body.Therefore, its range is extremely limited, and market is single.
Summary of the invention
It is an object of the invention to overcome the deficiencies in the prior art, it is provided that a kind of high stacking wafer system-in-package structure and preparation method, its compact conformation, achieving the encapsulating structure of multi-chip, power system capacity is big, can be effectively improved encapsulation production efficiency, wide accommodation, safe and reliable.
The technical scheme provided according to the present invention, described high stacking wafer system-in-package structure, including the first encapsulating structure obtained by cutting crystal wafer level chip package, described first encapsulating structure is stacked with at least one second encapsulating structure；
Described first encapsulating structure includes chip wafer and by the chip wafer plastic-sealed body plastic packaging the first functional chip on described chip wafer, described first functional chip mates electrical connection with chip wafer, arranges chip wafer is drawn the chip wafer connection ball connected on described chip wafer plastic-sealed body；
Second encapsulating structure includes PCB substrate and by the substrate plastic-sealed body plastic packaging the second functional chip in described PCB substrate front, described second functional chip mates electrical connection with PCB substrate, described substrate plastic-sealed body arranges the substrate electrically connected with the second functional chip and PCB substrate and is connected ball, arrange lower layer signal connecting line and the lower layer signal connection opening that lower layer signal connecting line is exposed at the back side of described PCB substrate, described lower layer signal connecting line is connected ball electrical connection with substrate；
The chip wafer that second encapsulating structure connects opening and the first encapsulating structure by lower layer signal connects ball alignment, and by surface mount process, the second encapsulating structure is stacked on the first encapsulating structure.
When first encapsulating structure is stacked with multiple second encapsulating structure, the substrate that second encapsulating structure above connects opening the second encapsulating structure adjacent with lower section by lower layer signal connects ball alignment, and makes two the second adjacent encapsulating structures be stacked into one by surface mount process.
The chip wafer pad being provided for connecting chip wafer pad redistribution on described chip wafer connects redistribution layer, and the first functional chip is gone between by the first functional chip and chip wafer pad connects redistribution layer and electrically connects with chip wafer；
Chip wafer connects ball and connects redistribution layer electrically connect with chip wafer by connecting the wafer plastic-sealed body packed column in redistribution layer, chip wafer plastic-sealed body and chip wafer pad on the wafer plastic-sealed body on chip wafer plastic-sealed body.
Described PCB substrate is provided with upper layer signal connecting line, and described upper layer signal connecting line connects post by the conducting in PCB substrate and electrically connects with lower layer signal connecting line, and the second functional chip is electrically connected with upper layer signal connecting line by the second functional chip lead-in wire,
Substrate is connected ball and is electrically connected with lower layer signal connecting line by the substrate plastic-sealed body packed column connecting in redistribution layer, substrate plastic-sealed body on the substrate plastic-sealed body on substrate plastic-sealed body, upper layer signal connecting line and conducting connection post.
The preparation method of a kind of high stacking wafer system-in-package structure, described preparation method comprises the steps:
The first encapsulating structure that step 1, offer are obtained by cutting crystal wafer level chip package, described first encapsulating structure includes chip wafer and by the chip wafer plastic-sealed body plastic packaging the first functional chip on described chip wafer, described first functional chip mates electrical connection with chip wafer, arranges chip wafer is drawn the chip wafer connection ball connected on described chip wafer plastic-sealed body；
Step 2, provide at least one second encapsulating structure, second encapsulating structure includes PCB substrate and by the substrate plastic-sealed body plastic packaging the second functional chip in described PCB substrate front, described second functional chip mates electrical connection with PCB substrate, described substrate plastic-sealed body arranges the substrate electrically connected with the second functional chip and PCB substrate and is connected ball, arrange lower layer signal connecting line and the lower layer signal connection opening that lower layer signal connecting line is exposed at the back side of described PCB substrate, described lower layer signal connecting line is connected ball electrical connection with substrate；
Step 3, lower layer signal of being passed through by the second encapsulating structure connect the chip wafer of opening and the first encapsulating structure and connect ball alignment, and by surface mount process, the second encapsulating structure are stacked on the first encapsulating structure.
When first encapsulating structure is stacked with multiple second encapsulating structure, the substrate that second encapsulating structure above connects opening the second encapsulating structure adjacent with lower section by lower layer signal connects ball alignment, and makes two the second adjacent encapsulating structures be stacked into one by surface mount process.
In step 1, the process obtaining the first encapsulating structure comprises the steps:
A, offer full wafer wafer, described full wafer wafer has the chip wafer of some desired structures, each chip wafer is respectively provided with the chip wafer for inputting, exporting and connects pad；
B, arrange on described chip wafer chip wafer pad connect redistribution layer, described chip wafer pad connect redistribution layer be connected with chip wafer pad electrically connect；
C, the first passivation layer is set on above-mentioned chip wafer, the chip wafer pad that described first passivation layer covers in the corresponding surface of chip wafer and part connects in redistribution layer, to obtain so that chip wafer pad connects the first passivation layer opening that redistribution layer end is exposed；
D, being provided above the first functional chip at above-mentioned chip wafer, described first functional chip is positioned between the first passivation layer opening；
E, by the first above-mentioned functional chip by the first functional chip lead-in wire and corresponding chip wafer pad connection redistribution layer electrical connection；
F, above-mentioned chip wafer is carried out plastic packaging, obtain gland chip wafer plastic-sealed body on the first functional chip and chip wafer；
G, above-mentioned chip wafer plastic-sealed body is holed, to obtain through chip wafer plastic-sealed body and the wafer plastic-sealed body through hole corresponding with the first passivation layer opening；
H, above-mentioned wafer plastic-sealed body through hole is carried out plating fill, to obtain filling up the wafer plastic-sealed body packed column of wafer plastic-sealed body through hole, described wafer plastic-sealed body packed column be connected with chip wafer pad redistribution layer electrically connect；
I, connection redistribution layer is set on wafer plastic-sealed body on above-mentioned chip wafer plastic-sealed body, described wafer plastic-sealed body connects redistribution layer and electrically connects with wafer plastic-sealed body packed column；
J, the second passivation layer is set on above-mentioned chip wafer plastic-sealed body, described second passivation layer covers and connects in redistribution layer on the wafer plastic-sealed body of chip wafer plastic-sealed body and part, to obtain so that connecting the second passivation layer opening that redistribution layer end is exposed on wafer plastic-sealed body；
K, utilize above-mentioned second passivation layer opening, chip wafer is connected ball bonding on wafer plastic-sealed body, connects the end of redistribution layer；
L, above-mentioned full wafer wafer is carried out cutting separate, to obtain the first required encapsulating structure.
In step 2, the preparation process of the second encapsulating structure comprises the steps:
PCB substrate needed for S1, offer, symmetrical upper layer signal connecting line is set in the front of described PCB substrate, being the lower layer signal connecting line of corresponding distribution at the setting of the back side of PCB substrate and upper layer signal connecting line, described lower layer signal connecting line connects post by the conducting in PCB substrate and corresponding upper layer signal connecting line electrically connects；
The front of PCB substrate arranges substrate upper strata passivation layer, the back side of PCB substrate arranges substrate underlying passivation layer, substrate upper strata passivation layer covers the corresponding front of PCB substrate and the upper layer signal connecting line of part, connects opening with the upper layer signal obtained so that upper layer signal connecting line desired zone exposes；Substrate underlying passivation layer covers the corresponding back side of PCB substrate and the lower layer signal connecting line of part, connecting opening with the lower layer signal obtained so that lower layer signal connecting line desired zone exposes, described lower layer signal connects opening and connects opening with upper layer signal in the most corresponding distribution；
S2, arranging the second functional chip in the front of above-mentioned PCB substrate, described second functional chip is gone between by the second functional chip and upper layer signal connects opening and electrically connects with upper layer signal connecting line；
S3, above-mentioned PCB substrate is carried out plastic packaging, obtain gland substrate plastic-sealed body on the second functional chip and PCB substrate；
S4, above-mentioned substrate plastic-sealed body is holed, to obtain through substrate plastic-sealed body and to connect, with upper layer signal, the substrate plastic-sealed body through hole that opening is corresponding；
S5, above-mentioned substrate plastic-sealed body through hole is carried out plating fill, to obtain filling up the substrate plastic-sealed body packed column of substrate plastic-sealed body through hole, described substrate plastic-sealed body packed column electrically connects with upper layer signal connecting line；
S6, connection redistribution layer is set on substrate plastic-sealed body on aforesaid substrate plastic-sealed body, connect the center gland of redistribution layer on described substrate plastic-sealed body on substrate plastic-sealed body packed column, substrate plastic-sealed body connects redistribution layer and electrically connects with substrate plastic-sealed body packed column；
S7, arranging the 3rd passivation layer on aforesaid substrate plastic-sealed body, described 3rd passivation layer covers and connects in redistribution layer on the substrate plastic-sealed body of substrate plastic-sealed body and part, so that connecting the 3rd passivation layer opening that redistribution layer end is exposed on substrate plastic-sealed body；
S8, utilize above-mentioned 3rd passivation layer opening, aforesaid substrate plastic-sealed body connects welding substrate in redistribution layer and connects ball.
It is stannum ball that described substrate connects ball.
Advantages of the present invention: the first encapsulating structure utilizes WLCSP packaged type to realize the encapsulating structure of multi-chip, second encapsulating structure is stacked on the first encapsulating structure, make the encapsulating structure size obtained little, equivalently-sized with chip wafer, improve capacity and the production efficiency of encapsulating structure, reduction packaging cost, wide accommodation, safe and reliable.
Accompanying drawing explanation
Fig. 1 is the structural representation of the present invention.
Fig. 2 ~ Figure 14 be the present invention the first encapsulating structure be embodied as process sequence diagram, wherein
Fig. 2 provides the sectional view of full wafer wafer for the present invention.
Fig. 3 is the sectional view that the present invention obtains chip wafer pad connection redistribution layer.
Fig. 4 is the sectional view after the present invention obtains the first passivation layer and the first passivation layer opening.
Fig. 5 is the sectional view after the present invention installs the first functional chip.
Fig. 6 is that the present invention the first functional chip passes through the sectional view after the first functional chip lead-in wire is connected redistribution layer connection with chip wafer pad.
Fig. 7 is the sectional view after the present invention obtains chip wafer plastic-sealed body.
Fig. 8 is the sectional view after the present invention obtains wafer plastic-sealed body through hole.
Fig. 9 is the sectional view after the present invention obtains wafer plastic-sealed body packed column.
Figure 10 is the sectional view that the present invention obtains after connecting redistribution layer on wafer plastic-sealed body.
Figure 11 is the sectional view after the present invention obtains the second passivation layer and the second passivation layer opening.
Figure 12 is that the present invention welds the sectional view after chip wafer connects ball.
Figure 13 is the schematic diagram that full wafer wafer is cut by the present invention.
Figure 14 is the sectional view after the present invention cuts isolated the first encapsulating structure.
Figure 15 ~ Figure 22 be the present invention obtain the second encapsulating structure be embodied as process sequence diagram, wherein
Figure 15 provides the sectional view of PCB substrate for the present invention.
Figure 16 is the sectional view after the present invention installs the second functional chip in PCB substrate.
Figure 17 is the sectional view after the present invention obtains substrate plastic-sealed body.
Figure 18 is the sectional view after the present invention obtains substrate plastic-sealed body through hole.
Figure 19 is the sectional view after the present invention obtains substrate plastic-sealed body packed column.
Figure 20 is the sectional view that the present invention obtains after connecting redistribution layer on substrate plastic-sealed body.
Figure 21 is the sectional view after the present invention obtains the 4th passivation layer and the 4th passivation layer opening.
Figure 22 is the sectional view after the present invention obtains the second encapsulating structure.
Figure 23 is that multiple second encapsulating structure of the present invention is stacked on the sectional view on the first encapsulating structure.
Figure 24 is that the present invention obtains the sectional view after encapsulating structure connects ball.
nullDescription of reference numerals: 1-full wafer wafer、2-chip wafer、3-chip wafer connects pad、4-chip wafer pad connects redistribution layer、5-the first passivation layer、6-the first passivation layer opening、7-the first functional chip、8-the first functional chip weld layer、9-the first functional chip goes between、10-chip wafer plastic-sealed body、11-wafer plastic-sealed body through hole、12-wafer plastic-sealed body packed column、Redistribution layer is connected on 13-wafer plastic-sealed body、14-the second passivation layer、15-the second passivation layer opening、16-chip wafer connects ball、17-PCB substrate、18-conducting connects post、19-upper layer signal connecting line、20-substrate upper strata passivation layer、21-upper layer signal connects opening、22-lower layer signal connecting line、23-substrate underlying passivation layer、24-lower layer signal connects opening、25-the second functional chip、26-the second functional chip weld layer、27-the second functional chip goes between、28-substrate plastic-sealed body、29-substrate plastic-sealed body through hole、30-substrate plastic-sealed body packed column、Redistribution layer is connected on 31-substrate plastic-sealed body、32-the 4th passivation layer、33-the 4th passivation layer opening、34-substrate connects ball、35-encapsulating structure connects ball、100-the first encapsulating structure and 200-the second encapsulating structure.
Detailed description of the invention
Below in conjunction with concrete drawings and Examples, the invention will be further described.
As shown in Fig. 2 and Figure 24: in order to achieve the encapsulating structure of multi-chip, improve power system capacity and encapsulation production efficiency, the present invention includes the first encapsulating structure 100 obtained by cutting crystal wafer level chip package, and described first encapsulating structure 100 is stacked with at least one second encapsulating structure 200；
Described first encapsulating structure 100 includes chip wafer 2 and by chip wafer plastic-sealed body 10 plastic packaging the first functional chip 7 on described chip wafer 2, described first functional chip 7 mates electrical connection with chip wafer 2, arranges chip wafer 2 is drawn the chip wafer connection ball 16 connected on described chip wafer plastic-sealed body 10；
Second encapsulating structure 200 includes PCB substrate 17 and by substrate plastic-sealed body 28 plastic packaging the second functional chip 25 in described PCB substrate 17 front, described second functional chip 25 mates electrical connection with PCB substrate 17, described substrate plastic-sealed body 28 arranges the substrate electrically connected with the second functional chip 25 and PCB substrate 17 and is connected ball 34, arrange lower layer signal connecting line 22 and the lower layer signal connection opening 24 that lower layer signal connecting line 22 is exposed at the back side of described PCB substrate 17, described lower layer signal connecting line 22 is connected ball 34 and electrically connects with substrate；
Second encapsulating structure 200 is connected ball 16 by lower layer signal connection opening 24 with the chip wafer of the first encapsulating structure 100 and is directed at, and by surface mount process, the second encapsulating structure 200 is stacked on the first encapsulating structure 100.
Specifically, first encapsulating structure 100 is obtained by cutting crystal wafer level chip package, first functional chip 7 is passed through chip wafer plastic-sealed body 10 plastic packaging on chip wafer 2, the coupling realized between the first functional chip 7 and chip wafer 2 is connected, finally, connect ball 16 by chip wafer can the first functional chip 7 and chip wafer 2 be drawn, it is simple to the connection with the second encapsulating structure 200 coordinates.Owing to the first encapsulating structure 100 is obtained by cutting crystal wafer level chip package, by chip wafer plastic-sealed body 10 plastic packaging, i.e. on the basis of WL-CSP, it is achieved that the encapsulating structure of multi-chip.The particular type of chip wafer the 2, first functional chip 7 and function type all can carry out selection as required and determine, specially known to those skilled in the art, here is omitted.
The concrete form of PCB substrate 17, the type etc. of the second functional chip 25 all can carry out selection as required and determine, second functional chip 25 passes through substrate plastic-sealed body 28 plastic packaging in PCB substrate 17, connect ball 34 by substrate can the input and output of the second functional chip 25 be drawn, by the lower layer signal connecting line 22 at PCB substrate 17 back side and lower layer signal connect opening 24 for the coordinating of the first encapsulating structure 100.The lower layer signal connection opening 24 of the second encapsulating structure 200 is connected ball 16 with the chip wafer of the first encapsulating structure 100 and is directed at, and after the second encapsulating structure 200 being stacked on the first encapsulating structure 100 by surface mount process (SMT), lower layer signal connecting line 22 is connected between ball 16 electrical connection with chip wafer, it is thus possible to realize chip wafer 2, between first functional chip 7 and the second functional chip 25, coupling connects, the ability of the aspects such as the data process needed for realization, whole stack package structure, the connection of ball 34 and external circuit can be connected by substrate, i.e. realize the input with external circuit, output.After second encapsulating structure 200 is stacked on the first encapsulating structure 100 by surface mount process, the stack package structure size obtained is little, equivalently-sized with chip wafer 2, and production efficiency is high, wide accommodation.
Further, when first encapsulating structure 100 is stacked with multiple second encapsulating structure 200, the substrate connection ball 34 that second encapsulating structure 200 above connects opening 24 second encapsulating structure 200 adjacent with lower section by lower layer signal is directed at, and makes two the second adjacent encapsulating structures 200 be stacked into one by surface mount process.
In the embodiment of the present invention, multiple second encapsulating structure 200 can be stacked on first encapsulating structure 100, when stacking multiple second encapsulating structure 200, the second encapsulating structure 200 being below neighbouring first encapsulating structure 100 is directly stacked upon on the first encapsulating structure 100 by surface mount process, it is stacked with between remaining second encapsulating structure 200, is stacked with between two the most adjacent the second encapsulating structures 200.When the second encapsulating structure 200 is stacked with, below utilization, the substrate of the second encapsulating structure 200 connects ball 34 and is connected opening 24 with the lower layer signal of top the second encapsulating structure 200 and is directed at, and again with surface mount process, two the second adjacent encapsulating structures 200 is stacked with.Multiple second encapsulating structure 200 heap poststacks, utilize the substrate of the top the second encapsulating structure 200 to connect ball 34 and are connected with external circuit, the input needed for i.e. and realizing between external circuit and fan-out capability.
Further, being provided on described chip wafer 2 chip wafer connects the chip wafer pad connection redistribution layer 4 that pad 3 redistributes, the first functional chip 7 connects redistribution layer 4 by the first functional chip lead-in wire 9 and chip wafer pad and electrically connects with chip wafer 2；
Chip wafer connects ball 16 and connects redistribution layer 4 electrically connect with chip wafer 2 by connecting the wafer plastic-sealed body packed column 12 in redistribution layer 13, chip wafer plastic-sealed body 10 and chip wafer pad on the wafer plastic-sealed body on chip wafer plastic-sealed body 10.
In the embodiment of the present invention, chip wafer connects pad 3 for realizing the input between chip wafer 2 and external circuit and output, connect redistribution layer 4 by chip wafer pad and can change the input of chip wafer 2, output link position, i.e. connect redistribution layer 4 by chip wafer pad and simply change the position of chip wafer connection pad 3, functions to chip wafer 2 etc. are unaffected, connect redistribution layer 4 by chip wafer pad and be connected the electrical connection between pad 3 with chip wafer, it is easy to chip wafer 2 coordinate with the connection of the first functional chip 7 grade, it is specially known to those skilled in the art, here is omitted.
First functional chip 7 is positioned at the top of chip wafer 2, utilizes the first functional chip lead-in wire 9 and chip wafer pad to connect redistribution layer 4 and electrically connects with chip wafer 2.Chip wafer connects ball 16 and is positioned on chip wafer plastic-sealed body 10, the electrical connection of ball 16 and chip wafer 2 is connected in order to realize chip wafer, need to arrange connection redistribution layer 13 on wafer plastic-sealed body on chip wafer plastic-sealed body 10, and wafer plastic-sealed body packed column 12 is set in chip wafer plastic-sealed body 10, chip wafer connects ball 16 and electrically connects with chip wafer 2, the signal of chip wafer 2 and the first functional chip 7 can be inputted or be exported.
Further, described PCB substrate 17 is provided with upper layer signal connecting line 19, described upper layer signal connecting line 19 connects post 18 by the conducting in PCB substrate 17 and electrically connects with lower layer signal connecting line 22, second functional chip 25 is electrically connected with upper layer signal connecting line 19 by the second functional chip lead-in wire 27
Substrate is connected ball 34 and is electrically connected with lower layer signal connecting line 22 by the substrate plastic-sealed body packed column 30 connecting in redistribution layer 31, substrate plastic-sealed body 28 on the substrate plastic-sealed body on substrate plastic-sealed body 28, upper layer signal connecting line 19 and conducting connection post 18.
In the embodiment of the present invention, it is connected cooperation with the second functional chip 25 by the PCB substrate 17 of multiple structure, lower layer signal connecting line 22 connects the electrical connection of post 18 and upper layer signal connecting line 19 by conducting, it is thus possible to the signal of the second functional chip 25 is connected post 18 by upper layer signal connecting line 19, conducting be drawn out to lower layer signal connecting line 22, it is simple to follow-up encapsulation connects and coordinates.
As shown in Figure 14, Figure 22, Figure 23 and Figure 24, above-mentioned high stacking wafer system-in-package structure can be realized by following technology arrangement, and specifically, described preparation method comprises the steps:
The first encapsulating structure 100 that step 1, offer are obtained by cutting crystal wafer level chip package, described first encapsulating structure 100 includes chip wafer 2 and by chip wafer plastic-sealed body 10 plastic packaging the first functional chip 7 on described chip wafer 2, described first functional chip 7 mates electrical connection with chip wafer 2, arranges chip wafer 2 is drawn the chip wafer connection ball 16 connected on described chip wafer plastic-sealed body 10；
As shown in Fig. 2 ~ Figure 14, the process obtaining the first encapsulating structure 100 comprises the steps:
A, offer full wafer wafer 1, described full wafer wafer 1 has the chip wafer 2 of some desired structures, each chip wafer 2 is respectively provided with the chip wafer for inputting, exporting and connects pad 3；
As shown in Figure 2, it is provided that full wafer wafer 1 on prepared required chip wafer 2, the process specifically preparing chip wafer 2 is that known to those skilled in the art, here is omitted.In like manner, the concrete structure etc. of chip wafer 2 all can select as required.The chip wafer 2 prepared is respectively provided with the chip wafer for inputting, exporting and connects pad 3, connect pad 3 by chip wafer to be connected with outside circuit, input between energy realization and external circuit and output, usually, chip wafer connection pad 3 is positioned at the position of chip wafer 2 center；With chip wafer 2 situation in full wafer wafer 1 in Fig. 2, isolated by chip boundary between adjacent chip wafer 2.
B, arranging chip wafer pad connect redistribution layer 4 on described chip wafer 2, described chip wafer pad connects redistribution layer 4 and is connected pad 3 with chip wafer and electrically connects；
As shown in Figure 3, owing to chip wafer connects the distributing position of pad 3, need for the ease of follow-up connection, chip wafer 2 arranges chip wafer pad and connects redistribution layer 4, chip wafer pad connects redistribution layer 4 and covers on chip wafer connection pad 3, and stretch out, thus improve chip wafer and connect the join domain of pad 3.In order to adapt to input and output needs, two chip wafer pads connection redistribution layer 4 are set and are connected the connection cooperation of pad 3 respectively with chip wafer, the process specifically arranging chip wafer pad connection redistribution layer 4 is that known to those skilled in the art, here is omitted.
C, the first passivation layer 5 is set on above-mentioned chip wafer 2, the chip wafer pad that described first passivation layer 5 covers in the corresponding surface of chip wafer 2 and part connects in redistribution layer 4, to obtain so that chip wafer pad connects the first passivation layer opening 6 that redistribution layer 4 end is exposed；
As shown in Figure 4, cover chip wafer 2 by the first passivation layer 5 and be not provided with the region of chip bonding pad connection redistribution layer 4, the chip wafer pad of the first passivation layer 5 covering part connects redistribution layer 4, the first passivation layer opening 6 can be obtained, usually, the first passivation layer opening 6 is positioned at the end of chip wafer pad connection redistribution layer 4；Concrete preparation the first passivation layer 5 and the process obtaining the first passivation layer opening 6 are that known to those skilled in the art, here is omitted.
D, being provided above the first functional chip 7 at above-mentioned chip wafer 2, described first functional chip 7 is positioned between the first passivation layer opening 6；
As it is shown in figure 5, the first functional chip 7 is welded on the purpose above chip wafer 2 by the first functional chip weld layer 8, the first functional chip weld layer 8 is utilized to realize the fixing of the first functional chip 7 and heat radiation；The specific constructive form of the first functional chip 7 can select as required, and here is omitted.
E, above-mentioned first functional chip 7 is electrically connected with corresponding chip wafer pad connection redistribution layer 4 by the first functional chip lead-in wire 9；
As shown in Figure 6, the first functional chip 7 connects redistribution layer 4 with corresponding chip wafer pad respectively by two first functional chip lead-in wires 9 and electrically connects, thus realizes the signal interconnection between the first functional chip 7 and chip wafer 2.
F, above-mentioned chip wafer 2 is carried out plastic packaging, obtain gland chip wafer plastic-sealed body 10 on the first functional chip 7 and chip wafer 2；
As it is shown in fig. 7, by disposable plastic packaging, can obtain chip wafer plastic-sealed body 10, chip wafer plastic-sealed body 10 gland is on chip wafer 2, thus by the first functional chip 7 plastic packaging such as grade in chip wafer plastic-sealed body 10；The process that concrete plastic packaging obtains chip wafer plastic-sealed body 10 is that known to those skilled in the art, here is omitted.
G, above-mentioned chip wafer plastic-sealed body 10 is holed, to obtain through chip wafer plastic-sealed body 10 and the wafer plastic-sealed body through hole 11 corresponding with the first passivation layer opening 6；
As shown in Figure 8, laser drilling process can be used to hole in chip wafer plastic-sealed body 10, obtain wafer plastic-sealed body through hole 11, the first passivation layer opening 6 can be made to expose by wafer plastic-sealed body through hole 11, but wafer plastic-sealed body through hole 11 will not make the first functional chip lead-in wire 9 be connected the joint portion of redistribution layer 4 with chip wafer pad.
H, above-mentioned wafer plastic-sealed body through hole 11 is carried out plating fill, to obtain filling up the wafer plastic-sealed body packed column 12 of wafer plastic-sealed body through hole 11, described wafer plastic-sealed body packed column 12 is connected redistribution layer 4 with chip wafer pad and electrically connects；
As it is shown in figure 9, wafer plastic-sealed body packed column 12 can be copper post, it is that known to those skilled in the art, here is omitted that filling obtains the detailed process of wafer plastic-sealed body packed column 12.
I, connection redistribution layer 13 is set on wafer plastic-sealed body on above-mentioned chip wafer plastic-sealed body 10, described wafer plastic-sealed body connects redistribution layer 13 and electrically connects with wafer plastic-sealed body packed column 12；
As shown in Figure 10, the process of connection redistribution layer 13 on wafer plastic-sealed body that arranges on chip wafer plastic-sealed body 10 is known to those skilled in the art, and on wafer plastic-sealed body, connection redistribution layer 13 gland is on wafer plastic-sealed body packed column 12, and is outwards symmetrically extended.
J, the second passivation layer 14 is set on above-mentioned chip wafer plastic-sealed body 10, described second passivation layer 14 covers and connects in redistribution layer 13 on the wafer plastic-sealed body of chip wafer plastic-sealed body 10 and part, to obtain so that connecting the second passivation layer opening 15 that redistribution layer 13 end is exposed on wafer plastic-sealed body；
As shown in figure 11, the second passivation layer 14 covers the region surface being not provided with on wafer plastic-sealed body connecting redistribution layer 13 at chip wafer plastic-sealed body 10, unlapped wafer plastic-sealed body connects redistribution layer 13 and forms the second passivation layer opening 15；
K, utilize above-mentioned second passivation layer opening 15, chip wafer is connected ball 16 and is welded on wafer plastic-sealed body the end connecting redistribution layer 13；
As shown in figure 12, it is stannum ball that chip wafer connects ball 16, by conventional welding procedure so that chip wafer connects ball 16 and is connected being welded and fixed of redistribution layer 13 with on wafer plastic-sealed body.
L, above-mentioned full wafer wafer 1 is carried out cutting separate, to obtain the first required encapsulating structure 100.
As shown in Figure 13 and Figure 14, after above-mentioned technique completes, by conventional cutting technique, full wafer wafer 1 is cut, thus obtain the first encapsulating structure 100, thus on the basis of WL-CSP, it is achieved that the encapsulating structure of multi-chip, improves production efficiency.
Step 2, at least one second encapsulating structure 200 is provided, second encapsulating structure 200 includes PCB substrate 17 and by substrate plastic-sealed body 28 plastic packaging the second functional chip 25 in described PCB substrate 17 front, described second functional chip 25 mates electrical connection with PCB substrate 17, described substrate plastic-sealed body 28 arranges the substrate electrically connected with the second functional chip 25 and PCB substrate 17 and is connected ball 34, lower layer signal connecting line 22 and the lower layer signal connection opening 24 that lower layer signal connecting line 22 is exposed are set at the back side of described PCB substrate 17, described lower layer signal connecting line 22 is connected ball 34 and electrically connects with substrate；
As shown in Figure 15 ~ Figure 22, the preparation process of the second encapsulating structure 100 comprises the steps:
PCB substrate 17 needed for S1, offer, in the front of described PCB substrate 17, symmetrical upper layer signal connecting line 19 is set, arranging at the back side of PCB substrate 17 and the upper layer signal connecting line 19 lower layer signal connecting line 22 in corresponding distribution, described lower layer signal connecting line 22 is electrically connected with corresponding upper layer signal connecting line 19 by the connection post 18 that turns in PCB substrate 17；
The front of PCB substrate 17 arranges substrate upper strata passivation layer 20, the back side of PCB substrate 17 arranges substrate underlying passivation layer 23, substrate upper strata passivation layer 20 covers the corresponding front of PCB substrate 17 and the upper layer signal connecting line 19 of part, connects opening 21 with the upper layer signal obtained so that upper layer signal connecting line 19 desired zone exposes；Substrate underlying passivation layer 23 covers the corresponding back side of PCB substrate 17 and the lower layer signal connecting line 22 of part, connecting opening 24 with the lower layer signal obtained so that lower layer signal connecting line 19 desired zone exposes, described lower layer signal connects opening 24 and connects opening 21 with upper layer signal in the most corresponding distribution；
As shown in figure 15, by the technological means that the art is conventional, upper layer signal connecting line 19, substrate upper strata passivation layer 20, upper layer signal connection opening 21, lower layer signal connecting line 22, substrate underlying passivation layer 23 and lower layer signal can be prepared and connect opening 24 and be connected post 18 with conducting.
S2, arranging the second functional chip 25 in the front of above-mentioned PCB substrate 17, described second functional chip 25 connects opening 21 by the second functional chip lead-in wire 27 and upper layer signal and electrically connects with upper layer signal connecting line 19；
As shown in figure 16, second functional chip 25 is welded on by the second functional chip weld layer 26 top of PCB substrate 17, fixing and the effect of heat radiation can be realized by the second functional chip weld layer 26, second functional chip 25 is positioned at upper layer signal and connects between opening 21, can realize the electrical connection corresponding with upper layer signal connecting line 19 by the second functional chip lead-in wire 27.
S3, above-mentioned PCB substrate 17 is carried out plastic packaging, obtain gland substrate plastic-sealed body 28 on the second functional chip 25 and PCB substrate 17；
As shown in figure 17, substrate plastic-sealed body 28 gland in PCB substrate 17, with by the second functional chip 25 plastic packaging such as grade in substrate plastic-sealed body 28.
S4, above-mentioned substrate plastic-sealed body 28 is holed, to obtain through substrate plastic-sealed body 28 and to connect, with upper layer signal, the substrate plastic-sealed body through hole 29 that opening 21 is corresponding；
As shown in figure 18, utilize laser drilling process, obtain substrate plastic-sealed body through hole 29, upper layer signal can be made to connect opening 21 by substrate plastic-sealed body through hole 29 and expose.
S5, above-mentioned substrate plastic-sealed body through hole 29 is carried out plating fill, to obtain filling up the substrate plastic-sealed body packed column 30 of substrate plastic-sealed body through hole 29, described substrate plastic-sealed body packed column 30 electrically connects with upper layer signal connecting line 19；
As shown in figure 19, by electroplating technology, substrate plastic-sealed body packed column 30 can be obtained.
S6, connection redistribution layer 31 is set on substrate plastic-sealed body on aforesaid substrate plastic-sealed body 28, on described substrate plastic-sealed body, the center gland of connection redistribution layer 31 is on substrate plastic-sealed body packed column 30, substrate plastic-sealed body connects redistribution layer 31 and electrically connects with substrate plastic-sealed body packed column 30；
As shown in figure 20, utilize the technological means that the art is conventional, connection redistribution layer 31 on substrate plastic-sealed body can be prepared, connect redistribution layer 31 on substrate plastic-sealed body and cover on substrate plastic-sealed body packed column 30, and stretch out in the both sides of substrate plastic-sealed body packed column 30, it is corresponding that following lower layer signal connects opening 24.
S7, the 3rd passivation layer 32 is set on aforesaid substrate plastic-sealed body 28, described 3rd passivation layer 32 covers and connects in redistribution layer 31 on the substrate plastic-sealed body of substrate plastic-sealed body 28 and part, so that connecting the 3rd passivation layer opening 32 that redistribution layer 31 end is exposed on substrate plastic-sealed body；
As shown in figure 21, the position of described 3rd passivation layer opening 32 connects the position of opening 24 in the most corresponding with lower layer signal, i.e. the 3rd passivation layer opening 32 is positioned at lower floor and washes the surface connecting opening 24, in order to the connection between follow-up two adjacent second encapsulating structures 200 coordinates.
S8, utilize above-mentioned 3rd passivation layer opening 32, aforesaid substrate plastic-sealed body connects welding substrate in redistribution layer 31 and connects ball 34.
As shown in figure 22, described substrate connects ball 34 is stannum ball；After welding substrate connects ball 34, obtain the second encapsulating structure 200.
Step 3, the second encapsulating structure 200 is connected opening 24 by lower layer signal it is connected ball 16 with the chip wafer of the first encapsulating structure 100 and is directed at, and by surface mount process, the second encapsulating structure 200 is stacked on the first encapsulating structure 100.
As shown in Figure 23 and Figure 24, the second encapsulating structure 200 can be made to be stacked on the first encapsulating structure 100 by surface mount process.When being stacked with multiple second encapsulating structure 200 on the first encapsulating structure 100, the substrate connection ball 34 that second encapsulating structure 200 above connects opening 24 second encapsulating structure 200 adjacent with lower section by lower layer signal is directed at, and makes two the second adjacent encapsulating structures 200 be stacked into one by surface mount process.
The present invention the first encapsulating structure 100 utilizes WLCSP packaged type to realize the encapsulating structure of multi-chip, second encapsulating structure 200 is stacked on the first encapsulating structure 100, make the encapsulating structure size obtained little, equivalently-sized with chip wafer 2, improve capacity and the production efficiency of encapsulating structure, reduction packaging cost, wide accommodation, safe and reliable.
Claims (9)
1. a high stacking wafer system-in-package structure, is characterized in that: include the first encapsulating structure (100) obtained by cutting crystal wafer level chip package, described first encapsulating structure (100) is stacked with at least one second encapsulating structure (200)；
Described first encapsulating structure (100) includes chip wafer (2) and by chip wafer plastic-sealed body (10) plastic packaging the first functional chip (7) on described chip wafer (2), described first functional chip (7) mates electrical connection with chip wafer (2), arranges chip wafer (2) is drawn chip wafer connection ball (16) connected on described chip wafer plastic-sealed body (10)；
Second encapsulating structure (200) includes PCB substrate (17) and by substrate plastic-sealed body (28) plastic packaging the second functional chip (25) in described PCB substrate (17) front, described second functional chip (25) mates electrical connection with PCB substrate (17), the substrate electrically connected with the second functional chip (25) and PCB substrate (17) is above set described substrate plastic-sealed body (28) and is connected ball (34), lower layer signal connecting line (22) and lower layer signal connection opening (24) that lower layer signal connecting line (22) is exposed are set at the back side of described PCB substrate (17), described lower layer signal connecting line (22) is connected ball (34) electrical connection with substrate；
Second encapsulating structure (200) connects opening (24) by lower layer signal and is connected ball (16) alignment with the chip wafer of the first encapsulating structure (100), and by surface mount process, the second encapsulating structure (200) is stacked on the first encapsulating structure (100).
High stacking wafer system-in-package structure the most according to claim 1, it is characterized in that: when being stacked with multiple second encapsulating structure (200) on the first encapsulating structure (100), the substrate that second encapsulating structure (200) above connects opening (24) the second encapsulating structure (200) adjacent with lower section by lower layer signal connects ball (34) alignment, and makes two adjacent the second encapsulating structures (200) be stacked into one by surface mount process.
High stacking wafer system-in-package structure the most according to claim 1, it is characterized in that: be provided on described chip wafer (2) chip wafer connects chip wafer pad connection redistribution layer (4) that pad (3) redistributes, the first functional chip (7) connects redistribution layer (4) by the first functional chip lead-in wire (9) and chip wafer pad and electrically connects with chip wafer (2)；
Chip wafer connects ball (16) and connects redistribution layer (4) electrically connect with chip wafer (2) by connecting wafer plastic-sealed body packed column (12) in redistribution layer (13), chip wafer plastic-sealed body (10) and chip wafer pad on the wafer plastic-sealed body on chip wafer plastic-sealed body (10).
High stacking wafer system-in-package structure the most according to claim 1, it is characterized in that: described PCB substrate (17) is provided with upper layer signal connecting line (19), described upper layer signal connecting line (19) connects post (18) by the conducting in PCB substrate (17) and electrically connects with lower layer signal connecting line (22), second functional chip (25) is electrically connected with upper layer signal connecting line (19) by the second functional chip lead-in wire (27)
Substrate is connected ball (34) and is electrically connected with lower layer signal connecting line (22) by substrate plastic-sealed body packed column (30) connecting in redistribution layer (31), substrate plastic-sealed body (28) on the substrate plastic-sealed body on substrate plastic-sealed body (28), upper layer signal connecting line (19) and conducting connection post (18).
5. a preparation method for high stacking wafer system-in-package structure, is characterized in that, described preparation method comprises the steps:
The first encapsulating structure (100) that step 1, offer are obtained by cutting crystal wafer level chip package, described first encapsulating structure (100) includes chip wafer (2) and by chip wafer plastic-sealed body (10) plastic packaging the first functional chip (7) on described chip wafer (2), described first functional chip (7) mates electrical connection with chip wafer (2), arranges chip wafer (2) is drawn chip wafer connection ball (16) connected on described chip wafer plastic-sealed body (10)；
Step 2, at least one second encapsulating structure (200) is provided, second encapsulating structure (200) includes PCB substrate (17) and by substrate plastic-sealed body (28) plastic packaging the second functional chip (25) in described PCB substrate (17) front, described second functional chip (25) mates electrical connection with PCB substrate (17), the substrate electrically connected with the second functional chip (25) and PCB substrate (17) is above set described substrate plastic-sealed body (28) and is connected ball (34), lower layer signal connecting line (22) and lower layer signal connection opening (24) that lower layer signal connecting line (22) is exposed are set at the back side of described PCB substrate (17), described lower layer signal connecting line (22) is connected ball (34) electrical connection with substrate；
Step 3, lower layer signal of being passed through by the second encapsulating structure (200) connect opening (24) and are connected ball (16) alignment with the chip wafer of the first encapsulating structure (100), and by surface mount process, the second encapsulating structure (200) are stacked on the first encapsulating structure (100).
The preparation method of the highest stacking wafer system-in-package structure, it is characterized in that, when first encapsulating structure (100) is stacked with multiple second encapsulating structure (200), the substrate that second encapsulating structure (200) above connects opening (24) the second encapsulating structure (200) adjacent with lower section by lower layer signal connects ball (34) alignment, and makes two adjacent the second encapsulating structures (200) be stacked into one by surface mount process.
The preparation method of the highest stacking wafer system-in-package structure, is characterized in that, in step 1, the process obtaining the first encapsulating structure (100) comprises the steps:
A (), offer full wafer wafer (1), described full wafer wafer (1) has the chip wafer (2) of some desired structures, each chip wafer (2) is respectively provided with the chip wafer for inputting, exporting and connects pad (3)；
(b), arrange on described chip wafer (2) chip wafer pad connect redistribution layer (4), described chip wafer pad connect redistribution layer (4) be connected with chip wafer pad (3) electrically connect；
(c), the first passivation layer (5) is set on above-mentioned chip wafer (2), the chip wafer pad that described first passivation layer (5) covers on the corresponding surface of chip wafer (2) and part connects in redistribution layer (4), to obtain so that chip wafer pad connects the first passivation layer opening (6) that redistribution layer (4) end is exposed；
(d), be provided above the first functional chip (7) at above-mentioned chip wafer (2), described first functional chip (7) is positioned between the first passivation layer opening (6)；
(e), by above-mentioned the first functional chip (7) by the first functional chip lead-in wire (9) and corresponding chip wafer pad connection redistribution layer (4) electrical connection；
(f), above-mentioned chip wafer (2) is carried out plastic packaging, obtain gland chip wafer plastic-sealed body (10) on the first functional chip (7) and chip wafer (2)；
(g), above-mentioned chip wafer plastic-sealed body (10) is holed, to obtain through chip wafer plastic-sealed body (10) and wafer plastic-sealed body through hole (11) corresponding with the first passivation layer opening (6)；
(h), above-mentioned wafer plastic-sealed body through hole (11) is carried out plating fill, to obtain filling up wafer plastic-sealed body packed column (12) of wafer plastic-sealed body through hole (11), described wafer plastic-sealed body packed column (12) is connected redistribution layer (4) electrical connection with chip wafer pad；
(i), connection redistribution layer (13) on wafer plastic-sealed body is set on above-mentioned chip wafer plastic-sealed body (10), described wafer plastic-sealed body connects redistribution layer (13) and electrically connects with wafer plastic-sealed body packed column (12)；
(j), on above-mentioned chip wafer plastic-sealed body (10), the second passivation layer (14) is set, described second passivation layer (14) covers and connects in redistribution layer (13) on the wafer plastic-sealed body of chip wafer plastic-sealed body (10) and part, to obtain so that connecting the second passivation layer opening (15) that redistribution layer (13) end is exposed on wafer plastic-sealed body；
(k), utilize above-mentioned second passivation layer opening (15), chip wafer is connected ball (16) be welded on wafer plastic-sealed body connect redistribution layer (13) end；
(l), above-mentioned full wafer wafer (1) is carried out cutting separate, to obtain required the first encapsulating structure (100).
The preparation method of the highest stacking wafer system-in-package structure, is characterized in that, in step 2, the preparation process of the second encapsulating structure (100) comprises the steps:
(S1) PCB substrate (17) needed for, providing, symmetrical upper layer signal connecting line (19) is set in the front of described PCB substrate (17), arranging at the back side of PCB substrate (17) and the upper layer signal connecting line (19) the lower layer signal connecting line (22) in corresponding distribution, described lower layer signal connecting line (22) is by conducting connection post (18) in PCB substrate (17) and the electrical connection of corresponding upper layer signal connecting line (19)；
The front of PCB substrate (17) arranges substrate upper strata passivation layer (20), the back side of PCB substrate (17) arranges substrate underlying passivation layer (23), substrate upper strata passivation layer (20) covers the corresponding front of PCB substrate (17) and the upper layer signal connecting line (19) of part, connects opening (21) with the upper layer signal obtained so that upper layer signal connecting line (19) desired zone exposes；Substrate underlying passivation layer (23) covers the corresponding back side of PCB substrate (17) and the lower layer signal connecting line (22) of part, connecting opening (24) with the lower layer signal obtained so that lower layer signal connecting line (19) desired zone exposes, described lower layer signal connects opening (24) and connects opening (21) with upper layer signal in the most corresponding distribution；
(S2), in the front of above-mentioned PCB substrate (17) arranging the second functional chip (25), described second functional chip (25) connects opening (21) by the second functional chip lead-in wire (27) and upper layer signal and electrically connects with upper layer signal connecting line (19)；
(S3), above-mentioned PCB substrate (17) is carried out plastic packaging, obtain gland substrate plastic-sealed body (28) on the second functional chip (25) and PCB substrate (17)；
(S4), above-mentioned substrate plastic-sealed body (28) is holed, to obtain through substrate plastic-sealed body (28) and to connect, with upper layer signal, substrate plastic-sealed body through hole (29) that opening (21) is corresponding；
(S5), to above-mentioned substrate plastic-sealed body through hole (29) carrying out plating to fill, to obtain filling up substrate plastic-sealed body packed column (30) of substrate plastic-sealed body through hole (29), described substrate plastic-sealed body packed column (30) electrically connects with upper layer signal connecting line (19)；
(S6), arrange on aforesaid substrate plastic-sealed body (28) and on substrate plastic-sealed body, connect redistribution layer (31), on described substrate plastic-sealed body, the center gland of connection redistribution layer (31) is on substrate plastic-sealed body packed column (30), substrate plastic-sealed body connects redistribution layer (31) and electrically connects with substrate plastic-sealed body packed column (30)；
(S7), the 3rd passivation layer (32) is set on aforesaid substrate plastic-sealed body (28), described 3rd passivation layer (32) covers and connects in redistribution layer (31) on the substrate plastic-sealed body of substrate plastic-sealed body (28) and part, so that connecting the 3rd passivation layer opening (32) that redistribution layer (31) end is exposed on substrate plastic-sealed body；
(S8), utilize above-mentioned 3rd passivation layer opening (32), aforesaid substrate plastic-sealed body connects the upper welding substrate of redistribution layer (31) and connects ball (34).
The preparation method of the highest stacking wafer system-in-package structure, is characterized in that, it is stannum ball that described substrate connects ball (34).
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110021572A (en) * | 2018-01-10 | 2019-07-16 | 力成科技股份有限公司 | Stack encapsulation structure and its manufacturing method |
| CN110060993A (en) * | 2019-04-26 | 2019-07-26 | 胡志刚 | Multilayer chiop framework and connection method |
| CN111128979A (en) * | 2019-11-22 | 2020-05-08 | 中国电子科技集团公司第十三研究所 | Wafer-level 3D chip preparation method |
| CN117312066A (en) * | 2023-12-01 | 2023-12-29 | 成都电科星拓科技有限公司 | Method for realizing chip eutectic wafer, wafer and chip |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090127703A1 (en) * | 2007-11-20 | 2009-05-21 | Fujitsu Limited | Method and System for Providing a Low-Profile Semiconductor Assembly |
| CN102646668A (en) * | 2011-02-17 | 2012-08-22 | 三星电子株式会社 | Semiconductor package having tsv interposer and method of manufacturing same |
| CN103311192A (en) * | 2013-06-25 | 2013-09-18 | 华进半导体封装先导技术研发中心有限公司 | Thin-gap POP (Package on Package) type packaging structure and packaging method |
| CN104733403A (en) * | 2015-03-23 | 2015-06-24 | 华进半导体封装先导技术研发中心有限公司 | Wafer-level packaging structure and manufacturing method |
| CN105047617A (en) * | 2015-06-09 | 2015-11-11 | 华进半导体封装先导技术研发中心有限公司 | Integral stack packaging structure and manufacturing method thereof |
-
2016
- 2016-07-18 CN CN201610567785.XA patent/CN106024766B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090127703A1 (en) * | 2007-11-20 | 2009-05-21 | Fujitsu Limited | Method and System for Providing a Low-Profile Semiconductor Assembly |
| CN102646668A (en) * | 2011-02-17 | 2012-08-22 | 三星电子株式会社 | Semiconductor package having tsv interposer and method of manufacturing same |
| CN103311192A (en) * | 2013-06-25 | 2013-09-18 | 华进半导体封装先导技术研发中心有限公司 | Thin-gap POP (Package on Package) type packaging structure and packaging method |
| CN104733403A (en) * | 2015-03-23 | 2015-06-24 | 华进半导体封装先导技术研发中心有限公司 | Wafer-level packaging structure and manufacturing method |
| CN105047617A (en) * | 2015-06-09 | 2015-11-11 | 华进半导体封装先导技术研发中心有限公司 | Integral stack packaging structure and manufacturing method thereof |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110021572A (en) * | 2018-01-10 | 2019-07-16 | 力成科技股份有限公司 | Stack encapsulation structure and its manufacturing method |
| CN110021572B (en) * | 2018-01-10 | 2021-03-23 | 力成科技股份有限公司 | Stacked package structure and method for manufacturing the same |
| CN110060993A (en) * | 2019-04-26 | 2019-07-26 | 胡志刚 | Multilayer chiop framework and connection method |
| CN111128979A (en) * | 2019-11-22 | 2020-05-08 | 中国电子科技集团公司第十三研究所 | Wafer-level 3D chip preparation method |
| CN111128979B (en) * | 2019-11-22 | 2022-08-16 | 中国电子科技集团公司第十三研究所 | Wafer-level 3D chip preparation method |
| CN117312066A (en) * | 2023-12-01 | 2023-12-29 | 成都电科星拓科技有限公司 | Method for realizing chip eutectic wafer, wafer and chip |
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|---|---|
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