CN106024766B - Height stacks wafer system-in-package structure and preparation method - Google Patents
Height stacks wafer system-in-package structure and preparation method Download PDFInfo
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- CN106024766B CN106024766B CN201610567785.XA CN201610567785A CN106024766B CN 106024766 B CN106024766 B CN 106024766B CN 201610567785 A CN201610567785 A CN 201610567785A CN 106024766 B CN106024766 B CN 106024766B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The present invention relates to a kind of high stacking wafer system-in-package structure and preparation methods comprising the first encapsulating structure obtained by cutting crystal wafer grade chip package is stacked at least one second encapsulating structure on the first encapsulating structure；First encapsulating structure includes chip wafer and the first functional chip by chip wafer plastic-sealed body plastic packaging on the chip wafer, and chip wafer connected ball is arranged on chip wafer plastic-sealed body；Second encapsulating structure includes PCB substrate and the second functional chip, and substrate connection ball is arranged on substrate plastic-sealed body, and lower layer signal connecting line and lower layer signal connection opening is arranged at the back side of PCB substrate；Second encapsulating structure is aligned by lower layer signal connection opening with the chip wafer connected ball of the first encapsulating structure, and by surface mount process the second encapsulating structure is stacked on the first encapsulating structure.Structure of the invention is compact, realizes the encapsulating structure of multi-chip, and power system capacity is big, can effectively improve encapsulation production efficiency, wide adaptation range.
Description
Technical field
The present invention relates to a kind of encapsulating structure and preparation method, especially a kind of high stacking wafer system-in-package structure and
Preparation method belongs to the technical field of semiconductor packages.
Background technology
Wafer stage chip encapsulates（WL-CSP）Technology be to full wafer wafer be packaged test after cut to obtain again individually at
The technology of product chip, the chip size after encapsulation are consistent with bare die.Wafer stage chip encapsulation technology changes conventional package, such as ceramics
The pattern of leadless chip carrier, organic leadless chip carrier and digital-code camera module formula has been complied with market and has been produced to microelectronics
Product are increasingly light, thin, short, small and low priceization requires.It is miniature that chip size after wafer stage chip encapsulation technology has reached height
Change, chip cost significant reduction with the reduction of chip size and the increase of wafer size.Wafer stage chip encapsulation technology is
IC designs, wafer manufacture, packaging and testing, basic plate can be manufactured the technology integrated, be the heat in current encapsulation field
The trend of point and future development.
Stacked package is a kind of good way for realizing micromation with high integration degree.In stacked package, interior envelope is encapsulated
Dress（PiP）With encapsulation outer package（PoP）It is more and more important to Packaging Industry, especially mobile phone application, because this technology can heap
Fold out highdensity logical device.There are two encapsulation, a tops for being encapsulated in another to be sealed two with soldered ball for PoP products
Dress combines.Logic element and memory components are integrated in different encapsulation by this encapsulation respectively, for example, mobile phone just uses
PoP encapsulates to integrate application processor and memory.PoP encapsulation overcomes the major defect of crystal grain stacking, such as supply chain problem,
Production yield loss, crystal grain profit be low and some other problem.
Since PoP encapsulation has, at low cost, package dimension is smaller, multiple memory is mixed and matched logic and assembling
The advantages that flexibility, the interior demand to PoP encapsulation of industry are constantly increasing, but the prior art its size after the completion of last encapsulation
Identical as chip size, technique and encapsulating structure determine that it can only be packaged single-chip, can not carry out multi-chip
Encapsulation, it is even more impossible to realize the stacked package of multiple packaging bodies.Therefore, use scope is extremely limited, and market is single.
Invention content
The purpose of the present invention is overcoming the deficiencies in the prior art, a kind of high stacking wafer system in package knot is provided
Structure and preparation method, it is compact-sized, the encapsulating structure of multi-chip is realized, power system capacity is big, can effectively improve encapsulation production
Efficiency, wide adaptation range, securely and reliably.
According to technical solution provided by the invention, the high stacking wafer system-in-package structure, including pass through and cut crystalline substance
Justify the first encapsulating structure that grade chip package obtains, at least one second encapsulating structure is stacked on first encapsulating structure；
First encapsulating structure include chip wafer and by chip wafer plastic-sealed body plastic packaging in the chip wafer
On the first functional chip, the matching of first functional chip and chip wafer is electrically connected, on the chip wafer plastic-sealed body
The chip wafer connected ball that chip wafer is drawn to connection is set；
Second encapsulating structure include PCB substrate and by substrate plastic-sealed body plastic packaging in the PCB substrate positive second
Functional chip, second functional chip are electrically connected with PCB substrate matching, setting and the second function on the substrate plastic-sealed body
Chip and the substrate connection ball of PCB substrate electrical connection, are arranged lower layer signal connecting line at the back side of the PCB substrate and make
The lower layer signal connection opening that lower layer signal connecting line exposes is obtained, the lower layer signal connecting line is electrically connected with substrate connection ball；
Second encapsulating structure is aligned by lower layer signal connection opening with the chip wafer connected ball of the first encapsulating structure, and
By surface mount process so that the second encapsulating structure is stacked on the first encapsulating structure.
When being stacked with multiple second encapsulating structures on the first encapsulating structure, under the second encapsulating structure for being located above passes through
The substrate connection ball of layer signal connection opening second encapsulating structure adjacent with lower section is aligned, and is made by surface mount process
Two the second adjacent encapsulating structures stack integral.
Setting by the chip wafer pad of chip wafer connection pad redistribution for connecting weight on the chip wafer
Distribution layer, the first functional chip connect redistribution layer and chip wafer by the first functional chip lead and chip wafer pad
Electrical connection；
Chip wafer connected ball is by connecting redistribution layer, chip wafer on the wafer plastic-sealed body on chip wafer plastic-sealed body
Wafer plastic-sealed body packed column and chip wafer pad connection redistribution layer in plastic-sealed body are electrically connected with chip wafer.
The PCB substrate is equipped with upper layer signal connecting line, and the upper layer signal connecting line passes through the conducting in PCB substrate
Connecting pole is electrically connected with lower layer signal connecting line, and the second functional chip passes through the second functional chip lead and upper layer signal connecting line
Electrical connection,
Substrate connection ball is by connecting redistribution layer, the base in substrate plastic-sealed body on the substrate plastic-sealed body on substrate plastic-sealed body
Plate plastic-sealed body packed column, upper layer signal connecting line and conducting connecting pole are electrically connected with lower layer signal connecting line.
A kind of high preparation method for stacking wafer system-in-package structure, the preparation method include the following steps：
The first encapsulating structure that step 1, offer are obtained by cutting crystal wafer grade chip package, the first encapsulating structure packet
Include chip wafer and the first functional chip by chip wafer plastic-sealed body plastic packaging on the chip wafer, first work(
Energy chip is electrically connected with chip wafer matching, and the crystalline substance that chip wafer is drawn to connection is arranged on the chip wafer plastic-sealed body
Round core piece connected ball；
Step 2 provides at least one second encapsulating structure, and the second encapsulating structure includes PCB substrate and moulded by substrate
Body plastic packaging is sealed in positive second functional chip of the PCB substrate, second functional chip is electrically connected with PCB substrate matching,
The substrate connection ball being electrically connected with the second functional chip and PCB substrate is set on the substrate plastic-sealed body, in the PCB bases
The back side setting lower layer signal connecting line of plate and the lower layer signal connection opening that lower layer signal connecting line is exposed, under described
Layer signal connecting line is electrically connected with substrate connection ball；
Second encapsulating structure is connect by lower layer signal connection opening with the chip wafer of the first encapsulating structure by step 3
Ball is aligned, and by surface mount process the second encapsulating structure is stacked on the first encapsulating structure.
When being stacked with multiple second encapsulating structures on the first encapsulating structure, under the second encapsulating structure for being located above passes through
The substrate connection ball of layer signal connection opening second encapsulating structure adjacent with lower section is aligned, and is made by surface mount process
Two the second adjacent encapsulating structures stack integral.
In step 1, the process for obtaining the first encapsulating structure includes the following steps：
A, full wafer wafer is provided, there is the chip wafer of several required structures, each chip wafer on the full wafer wafer
On all have for inputting, exporting chip wafer connection pad；
B, chip wafer pad on the chip wafer is set connect redistribution layer, the chip wafer pad connection weight
Distribution layer connect pad electrical connection with chip wafer；
C, first passivation layer is set on above-mentioned chip wafer, first passivation layer is covered in the corresponding table of chip wafer
On face and partial chip wafer pad connection redistribution layer, to obtain so that chip wafer pad connection redistribution layer end
The first exposed passivation layer opening；
D, first functional chip is set above above-mentioned chip wafer, first functional chip is located at the first passivation layer and opens
Between mouthful；
E, the first above-mentioned functional chip is connected into weight by the first functional chip lead with corresponding chip wafer pad
Distribution layer is electrically connected；
F, plastic packaging is carried out to above-mentioned chip wafer, obtains wafer of the gland on the first functional chip and chip wafer
Chip plastic-sealed body；
G, it drills to above-mentioned chip wafer plastic-sealed body, to obtain perforation chip wafer plastic-sealed body and be passivated with first
The corresponding wafer plastic-sealed body through-hole of layer opening；
H, plating filling is carried out to above-mentioned wafer plastic-sealed body through-hole, the wafer to obtain filling up wafer plastic-sealed body through-hole is moulded
Body packed column is sealed, the wafer plastic-sealed body packed column connect redistribution layer electrical connection with chip wafer pad；
I, it is arranged on wafer plastic-sealed body on above-mentioned chip wafer plastic-sealed body and connects redistribution layer, on the wafer plastic-sealed body
Connection redistribution layer is electrically connected with wafer plastic-sealed body packed column；
J, second passivation layer is set on above-mentioned chip wafer plastic-sealed body, second passivation layer is covered in chip wafer modeling
It seals on body and partial wafer plastic-sealed body in connection redistribution layer, to obtain so that connecting redistribution layer end on wafer plastic-sealed body
The second passivation layer opening that portion exposes；
K, using above-mentioned second passivation layer opening, chip wafer connected ball is welded on wafer plastic-sealed body and connects redistribution
The end of layer；
L, cutting separation is carried out to above-mentioned full wafer wafer, to obtain the first required encapsulating structure.
In step 2, the preparation process of the second encapsulating structure includes the following steps：
Symmetrical upper layer signal connecting line is arranged in the front of the PCB substrate for PCB substrate needed for S1, offer,
At the back side of PCB substrate, with upper layer signal connecting line in the lower layer signal connecting line of corresponding distribution, the lower layer signal connects for setting
Wiring is electrically connected by the conducting connecting pole in PCB substrate with corresponding upper layer signal connecting line；
The front setting substrate upper layer passivation layer of PCB substrate, substrate underlying passivation layer, substrate is arranged in the back side of PCB substrate
The upper layer passivation layer corresponding front of covering PCB substrate and partial upper layer signal connecting line, to obtain so that upper layer signal connects
The upper layer signal connection opening that wiring desired zone exposes；Substrate underlying passivation layer covers the corresponding back side of PCB substrate and portion
The lower layer signal connecting line divided, to obtain so that the lower layer signal that lower layer signal connecting line desired zone exposes connects opening, institute
It is in correspond distribution to state lower layer signal connection opening and connect opening with upper layer signal；
S2, the second functional chip of front setting in above-mentioned PCB substrate, second functional chip pass through the second function core
Piece lead and upper layer signal connection opening are electrically connected with upper layer signal connecting line；
S3, plastic packaging is carried out to above-mentioned PCB substrate, obtains substrate of the gland on the second functional chip and PCB substrate
Plastic-sealed body；
S4, it drills to above-mentioned substrate plastic-sealed body, to obtain through substrate plastic-sealed body and be connect out with upper layer signal
The corresponding substrate plastic-sealed body through-hole of mouth；
S5, plating filling is carried out to above-mentioned substrate plastic-sealed body through-hole, to obtain filling up the substrate of substrate plastic-sealed body through-hole
Plastic-sealed body packed column, the substrate plastic-sealed body packed column are electrically connected with upper layer signal connecting line；
S6, redistribution layer is connected on setting substrate plastic-sealed body on aforesaid substrate plastic-sealed body, connected on the substrate plastic-sealed body
The center gland of redistribution layer is connect on substrate plastic-sealed body packed column, redistribution layer and substrate plastic packaging are connected on substrate plastic-sealed body
Body packed column is electrically connected；
S7, on aforesaid substrate plastic-sealed body be arranged third passivation layer, the third passivation layer be covered in substrate plastic-sealed body with
And connected in redistribution layer on partial substrate plastic-sealed body, so that connect that redistribution layer end exposes on substrate plastic-sealed body the
Three passivation layer openings；
S8, using above-mentioned third passivation layer opening, welding substrate in redistribution layer is connected on aforesaid substrate plastic-sealed body and is connected
It receives.
The substrate connection ball is tin ball.
Advantages of the present invention：First encapsulating structure realizes the encapsulating structure of multi-chip, the second envelope using WLCSP packaged types
Assembling structure is stacked on the first encapsulating structure so that obtained encapsulating structure size is small, identical as the size of chip wafer, improves
The capacity and production efficiency of encapsulating structure, reduction packaging cost, wide adaptation range, securely and reliably.
Description of the drawings
Fig. 1 is the structural diagram of the present invention.
Fig. 2 ~ Figure 14 is the specific implementation process block diagram of the first encapsulating structure of the invention, wherein
Fig. 2 provides the sectional view of full wafer wafer for the present invention.
Fig. 3 is that the present invention obtains the sectional view that chip wafer pad connects redistribution layer.
Fig. 4 is that the present invention obtains the sectional view after the first passivation layer and the first passivation layer opening.
Fig. 5 is the sectional view after the present invention the first functional chip of installation.
Fig. 6 is that the first functional chip of the invention connect redistribution layer by the first functional chip lead with chip wafer pad
Sectional view after connection.
Fig. 7 is that the present invention obtains the sectional view after chip wafer plastic-sealed body.
Fig. 8 is that the present invention obtains the sectional view after wafer plastic-sealed body through-hole.
Fig. 9 is that the present invention obtains the sectional view after wafer plastic-sealed body packed column.
Figure 10 is that the present invention obtains connecting the sectional view after redistribution layer on wafer plastic-sealed body.
Figure 11 is that the present invention obtains the sectional view after the second passivation layer and the second passivation layer opening.
Figure 12 is the sectional view after present invention welding chip wafer connected ball.
Figure 13 is the schematic diagram that the present invention cuts full wafer wafer.
Figure 14 is that the present invention cuts the sectional view after isolated first encapsulating structure.
Figure 15 ~ Figure 22 obtains the specific implementation process block diagram of the second encapsulating structure for the present invention, wherein
Figure 15 provides the sectional view of PCB substrate for the present invention.
Figure 16 is that the present invention installs the sectional view after the second functional chip in PCB substrate.
Figure 17 is that the present invention obtains the sectional view after substrate plastic-sealed body.
Figure 18 is that the present invention obtains the sectional view after substrate plastic-sealed body through-hole.
Figure 19 is that the present invention obtains the sectional view after substrate plastic-sealed body packed column.
Figure 20 is that the present invention obtains connecting the sectional view after redistribution layer on substrate plastic-sealed body.
Figure 21 is that the present invention obtains the sectional view after the 4th passivation layer and the 4th passivation layer opening.
Figure 22 is that the present invention obtains the sectional view after the second encapsulating structure.
Figure 23 is that multiple second encapsulating structures of the present invention are stacked on the sectional view on the first encapsulating structure.
Figure 24 is that the present invention obtains the sectional view after encapsulating structure connected ball.
Reference sign：1- full wafers wafer, 2- chip wafers, 3- chip wafers connection pad, 4- chip wafer pads
Connect redistribution layer, the first passivation layers of 5-, the first passivation layer openings of 6-, the first functional chips of 7-, the welding of the first functional chips of 8-
Layer, the filling of the first functional chips of 9- lead, 10- chip wafers plastic-sealed body, 11- wafer plastic-sealed bodies through-hole, 12- wafer plastic-sealed bodies
Redistribution layer, the second passivation layers of 14-, the second passivation layer openings of 15-, 16- chip wafers is connected on column, 13- wafer plastic-sealed bodies to connect
It receives, 17-PCB substrates, 18- conducting connecting pole, 19- upper layer signals connecting line, 20- substrates upper layer passivation layer, 21- upper layer signals
Connect opening, 22- lower layer signals connecting line, 23- substrates underlying passivation layer, 24- lower layer signals connection opening, the second functions of 25-
Chip, the second functional chips of 26- welding layer, the second functional chips of 27- lead, 28- substrates plastic-sealed body, 29- substrate plastic-sealed bodies are logical
Hole, 30- substrate plastic-sealed bodies packed column, connection redistribution layer, the 4th passivation layers of 32-, 33- the 4th are passivated on 31- substrate plastic-sealed bodies
Layer opening, 34- substrate connections ball, the second encapsulating structure of 35- encapsulating structures connected ball, the first encapsulating structures of 100- and 200-.
Specific implementation mode
With reference to specific drawings and examples, the invention will be further described.
As shown in Fig. 2 and Figure 24：In order to realize the encapsulating structure of multi-chip, power system capacity and encapsulation production effect are improved
Rate, the present invention include the first encapsulating structure 100 obtained by cutting crystal wafer grade chip package, first encapsulating structure 100
On be stacked at least one second encapsulating structure 200；
First encapsulating structure 100 is including chip wafer 2 and by 10 plastic packaging of chip wafer plastic-sealed body in the crystalline substance
The first functional chip 7 on round core piece 2, first functional chip 7 is electrically connected with the matching of chip wafer 2, in the wafer core
Chip wafer 2 is drawn the chip wafer connected ball 16 of connection by setting on piece plastic-sealed body 10；
Second encapsulating structure 200 include PCB substrate 17 and by 28 plastic packaging of substrate plastic-sealed body the PCB substrate 17 just
Second functional chip 25 in face, second functional chip 25 is electrically connected with the matching of PCB substrate 17, in the substrate plastic-sealed body 28
It is upper that the substrate connection ball 34 being electrically connected with the second functional chip 25 and PCB substrate 17 is set, at the back side of the PCB substrate 17
The lower layer signal connection opening 24 that lower layer signal connecting line 22 is set and lower layer signal connecting line 22 is exposed, the lower layer
Signal connecting line 22 is electrically connected with substrate connection ball 34；
Second encapsulating structure 200 is connect by lower layer signal connection opening 24 with the chip wafer of the first encapsulating structure 100
Ball 16 is aligned, and by surface mount process the second encapsulating structure 200 is stacked on the first encapsulating structure 100.
Specifically, the first encapsulating structure 100 is obtained by cutting crystal wafer grade chip package, and the first functional chip 7 is passed through
10 plastic packaging of chip wafer plastic-sealed body realizes that the matching between the first functional chip 7 and chip wafer 2 connects on chip wafer 2,
Finally, first functional chip 7 and chip wafer 2 can be drawn, is convenient for and second by chip wafer connected ball 16
The connection of encapsulating structure 200 coordinates.Since the first encapsulating structure 100 is obtained by cutting crystal wafer grade chip package, passing through crystalline substance
10 plastic packaging of round core piece plastic-sealed body realizes the encapsulating structure of multi-chip that is, on the basis of WL-CSP.Chip wafer 2, the first work(
The concrete type and function type of energy chip 7 can carry out selection determination, specially those skilled in the art as needed
Known, details are not described herein again.
Type of the concrete form of PCB substrate 17, the second functional chip 25 etc. can carry out selection determination as needed,
Second functional chip 25 by 28 plastic packaging of substrate plastic-sealed body in PCB substrate 17, can be by the second function by substrate connection ball 34
The input and output of chip 25 are drawn, and opening is connected by the lower layer signal connecting line 22 and lower layer signal at 17 back side of PCB substrate
24 for the cooperation with the first encapsulating structure 100.The lower layer signal connection opening 24 of second encapsulating structure 200 and the first encapsulation are tied
The chip wafer connected ball 16 of structure 100 is aligned, and passes through surface mount process（SMT）So that the second encapsulating structure 200 is stacked on
It after on first encapsulating structure 100, is electrically connected between lower layer signal connecting line 22 and chip wafer connected ball 16, so as to realize wafer
Connection is matched between chip 2, the first functional chip 7 and the second functional chip 25, realizes required data processing etc.
Ability, entire stack package structure can be realized and external circuit by the connection of substrate connection ball 34 and external circuit
Input, output.After second encapsulating structure 200 is stacked on by surface mount process on the first encapsulating structure 100, obtained stacking
Encapsulating structure size is small, identical as the size of chip wafer 2, and production efficiency is high, wide adaptation range.
Further, when being stacked with multiple second encapsulating structures 200 on the first encapsulating structure 100, be located above
Two encapsulating structures 200 connect the substrate connection ball 34 of 24 second encapsulating structures 200 adjacent with lower section of opening by lower layer signal
Alignment, and by surface mount process two the second adjacent encapsulating structures 200 are stacked integrally.
In the embodiment of the present invention, multiple second encapsulating structures 200 can be stacked on the first encapsulating structure 100, it is more when stacking
When a second encapsulating structure 200, the second encapsulating structure 200 for being below neighbouring first encapsulating structure 100 passes through surface mount
Technique is directly stacked upon on the first encapsulating structure 100, is stacked between remaining second encapsulating structure 200, i.e., adjacent two
It is stacked between second encapsulating structure 200.When the second encapsulating structure 200 is stacked with, the second encapsulating structure of lower section 200 is utilized
The lower layer signal connection opening 24 of substrate connection ball 34 and the second encapsulating structure of top 200 be directed at, utilize surface mount again
Technique makes two the second adjacent encapsulating structures 200 be stacked with.200 heap poststack of multiple second encapsulating structures, utilizes the top
The substrate connection ball 34 of second encapsulating structure 200 is connect with external circuit, i.e., realized between external circuit required input with it is defeated
Output capacity.
Further, chip wafer of the setting for redistributing chip wafer connection pad 3 on the chip wafer 2
Pad connects redistribution layer 4, and the first functional chip 7 is divided again by the first functional chip lead 9 and the connection of chip wafer pad
Layer of cloth 4 is electrically connected with chip wafer 2；
Chip wafer connected ball 16 is by connecting redistribution layer 13, crystalline substance on the wafer plastic-sealed body on chip wafer plastic-sealed body 10
Wafer plastic-sealed body packed column 12 and chip wafer pad connection redistribution layer 4 in round core piece plastic-sealed body 10 and chip wafer 2
Electrical connection.
In the embodiment of the present invention, chip wafer connects pad 3 for realizing the input between chip wafer 2 and external circuit
And output, the input of chip wafer 2, output link position can be changed by connecting redistribution layer 4 by chip wafer pad, i.e., logical
It is to change the position of chip wafer connection pad 3 to cross chip wafer pad connection redistribution layer 4, to the function of chip wafer 2
Etc. unaffected, redistribution layer 4 is connected by chip wafer pad and chip wafer connects being electrically connected between pad 3, convenient for crystalline substance
The connection of round core piece 2 and the first functional chip 7 etc. coordinates, and specially known to those skilled in the art, details are not described herein again.
First functional chip 7 is located at the top of chip wafer 2, is welded using the first functional chip lead 9 and chip wafer
Disk connection redistribution layer 4 is electrically connected with chip wafer 2.Chip wafer connected ball 16 is located on chip wafer plastic-sealed body 10, in order to
Realization chip wafer connected ball 16 is electrically connected with chip wafer 2, needs that wafer plastic packaging is arranged on chip wafer plastic-sealed body 10
Redistribution layer 13, and the setting wafer plastic-sealed body packed column 12 in chip wafer plastic-sealed body 10, chip wafer connection are connected on body
Ball 16 is electrically connected with chip wafer 2, can the signal of chip wafer 2 and the first functional chip 7 be inputted or be exported.
Further, the PCB substrate 17 is equipped with upper layer signal connecting line 19, and the upper layer signal connecting line 19 passes through
Conducting connecting pole 18 in PCB substrate 17 is electrically connected with lower layer signal connecting line 22, and the second functional chip 25 passes through the second function
Chip lead 27 is electrically connected with upper layer signal connecting line 19,
Substrate connection ball 34 is by connecting redistribution layer 31, substrate plastic-sealed body on the substrate plastic-sealed body on substrate plastic-sealed body 28
Substrate plastic-sealed body packed column 30, upper layer signal connecting line 19 and conducting connecting pole 18 in 28 and 22 electricity of lower layer signal connecting line
Connection.
In the embodiment of the present invention, cooperation, lower layer's letter are connect with the second functional chip 25 by the PCB substrate 17 of multilayered structure
Number connecting line 22 is by being connected being electrically connected for connecting pole 18 and upper layer signal connecting line 19, so as to by the second functional chip 25
Signal is drawn out to lower layer signal connecting line 22 by upper layer signal connecting line 19, conducting connecting pole 18, connects convenient for subsequent encapsulation
Connect cooperation.
As shown in Figure 14, Figure 22, Figure 23 and Figure 24, above-mentioned high stacking wafer system-in-package structure can be by following
Technology arrangement realize, specifically, the preparation method includes the following steps：
The first encapsulating structure 100 that step 1, offer are obtained by cutting crystal wafer grade chip package, the first encapsulation knot
Structure 100 includes chip wafer 2 and the first functional chip by 10 plastic packaging of chip wafer plastic-sealed body on the chip wafer 2
7, first functional chip 7 is electrically connected with the matching of chip wafer 2, is arranged wafer core on the chip wafer plastic-sealed body 10
Piece 2 draws the chip wafer connected ball 16 of connection；
As shown in Fig. 2 ~ Figure 14, the process for obtaining the first encapsulating structure 100 includes the following steps：
A, full wafer wafer 1 is provided, there is the chip wafer 2 of several required structures, each wafer core on the full wafer wafer 1
The chip wafer connection pad 3 for inputting, exporting is all had on piece 2；
As shown in Fig. 2, required chip wafer 2 has been prepared on the full wafer wafer 1 provided, crystalline substance is specifically prepared
The process of round core piece 2 is known to those skilled in the art, and details are not described herein again.Similarly, concrete structure of chip wafer 2 etc. is equal
It can be selected as needed.The chip wafer connection for inputting, exporting is all had on the chip wafer 2 being prepared
Pad 3, connecting pad 3 by chip wafer can connect with external circuit, can realize the input and output between external circuit,
Usually, chip wafer connection pad 3 is located at the position of 2 center of chip wafer；With a crystalline substance in full wafer wafer 1 in Fig. 2
2 situation of round core piece is isolated by chip boundary between adjacent chip wafer 2.
B, chip wafer pad on the chip wafer 2 is set connect redistribution layer 4, the chip wafer pad connection
Redistribution layer 4 connect the electrical connection of pad 3 with chip wafer；
As shown in figure 3, since chip wafer connects the distributing position of pad 3, needed for the ease of subsequent connection, in crystalline substance
Chip wafer pad is set on round core piece 2 and connects redistribution layer 4, chip wafer pad connection redistribution layer 4 is covered in wafer core
Piece connects on pad 3, and extends outwardly, to improve the join domain that chip wafer connects pad 3.In order to adapt to input and output
It needs, two chip wafer pads is set and connect the connection cooperation that redistribution layer 4 connect pad 3 with chip wafer respectively, specifically
The process that chip wafer pad connection redistribution layer 4 is arranged is known to those skilled in the art, and details are not described herein again.
C, first passivation layer 5 is set on above-mentioned chip wafer 2, it is corresponding that first passivation layer 5 is covered in chip wafer 2
Surface and partial chip wafer pad connection redistribution layer 4 on, to obtain so that chip wafer pad connection redistribution
The first exposed passivation layer opening 6 of 4 end of layer；
As shown in figure 4, covering chip wafer 2 by the first passivation layer 5, the area that chip bonding pad connects redistribution layer 4 is not arranged
The chip wafer pad in domain, 5 covering part of the first passivation layer connects redistribution layer 4, can obtain the first passivation layer opening 6, generally
Ground, the first passivation layer opening 6 are located at the end of chip wafer pad connection redistribution layer 4；It is specific prepare the first passivation layer 5 and
The process for obtaining the first passivation layer opening 6 is known to those skilled in the art, and details are not described herein again.
D, first functional chip 7 is set above above-mentioned chip wafer 2, first functional chip 7 is located at the first passivation
Between layer opening 6；
As shown in figure 5, the first functional chip 7 is welded on the mesh of 2 top of chip wafer by the first functional chip welding layer 8
, realize the fixation and heat dissipation to the first functional chip 7 using the first functional chip welding layer 8；First functional chip 7 it is specific
Structure type can be selected as needed, and details are not described herein again.
E, the first above-mentioned functional chip 7 is connected by the first functional chip lead 9 with corresponding chip wafer pad
Redistribution layer 4 is electrically connected；
As shown in fig. 6, the first functional chip 7 by two first functional chip leads 9 respectively with corresponding chip wafer
Pad connects redistribution layer 4 and is electrically connected, to realize the signal interconnection between the first functional chip 7 and chip wafer 2.
F, plastic packaging is carried out to above-mentioned chip wafer 2, obtains gland on the first functional chip 7 and chip wafer 2
Chip wafer plastic-sealed body 10；
As shown in fig. 7, by disposable plastic packaging, chip wafer plastic-sealed body 10,10 gland of chip wafer plastic-sealed body can be obtained
On chip wafer 2, thus by plastic packagings such as the first functional chips 7 in chip wafer plastic-sealed body 10；Specific plastic packaging obtains wafer
The process of chip plastic-sealed body 10 is known to those skilled in the art, and details are not described herein again.
G, it drills to above-mentioned chip wafer plastic-sealed body 10, to obtain perforation chip wafer plastic-sealed body 10 and with first
6 corresponding wafer plastic-sealed body through-hole 11 of passivation layer opening；
As shown in figure 8, laser drilling process can be used to drill in chip wafer plastic-sealed body 10, wafer plastic packaging is obtained
Body through-hole 11, can be so that the first passivation layer opening 6 exposes by wafer plastic-sealed body through-hole 11, but wafer plastic-sealed body through-hole 11 will not
So that the first functional chip lead 9 connect the engaging portion of redistribution layer 4 with chip wafer pad.
H, plating filling is carried out to above-mentioned wafer plastic-sealed body through-hole 11, to obtain filling up the crystalline substance of wafer plastic-sealed body through-hole 11
Circle plastic-sealed body packed column 12, the wafer plastic-sealed body packed column 12 connect the electrical connection of redistribution layer 4 with chip wafer pad；
As shown in figure 9, wafer plastic-sealed body packed column 12 can be copper post, filling obtains the tool of wafer plastic-sealed body packed column 12
Body process is known to those skilled in the art, and details are not described herein again.
I, it is arranged on wafer plastic-sealed body on above-mentioned chip wafer plastic-sealed body 10 and connects redistribution layer 13, the wafer plastic packaging
Redistribution layer 13 is connected on body to be electrically connected with wafer plastic-sealed body packed column 12；
As shown in Figure 10, the process of connection redistribution layer 13 is on setting wafer plastic-sealed body on chip wafer plastic-sealed body 10
13 gland of redistribution layer is connected known to those skilled in the art, on wafer plastic-sealed body on wafer plastic-sealed body packed column 12, and
It is symmetrically extended outward.
J, second passivation layer 14 is set on above-mentioned chip wafer plastic-sealed body 10, second passivation layer 14 is covered in wafer
It is connected in redistribution layer 13 on chip plastic-sealed body 10 and partial wafer plastic-sealed body, to obtain so that being connected on wafer plastic-sealed body
The second passivation layer opening 15 that 13 end of redistribution layer is exposed；
As shown in figure 11, the second passivation layer 14 be covered in chip wafer plastic-sealed body 10 be not arranged on wafer plastic-sealed body connect weight
The region surface of distribution layer 13, connection redistribution layer 13 forms the second passivation layer opening 15 on unlapped wafer plastic-sealed body；
K, using above-mentioned second passivation layer opening 15, chip wafer connected ball 16 is welded on wafer plastic-sealed body and connects weight
The end of distribution layer 13；
As shown in figure 12, chip wafer connected ball 16 is tin ball, passes through conventional welding procedure so that chip wafer connects
Ball 16 with connect redistribution layer 13 on wafer plastic-sealed body and be welded and fixed.
L, cutting separation is carried out to above-mentioned full wafer wafer 1, to obtain the first required encapsulating structure 100.
As shown in Figure 13 and Figure 14, after the completion of above-mentioned technique, full wafer wafer 1 is cut by conventional cutting technique
It cuts, to obtain the first encapsulating structure 100, on the basis of WL-CSP, realize the encapsulating structure of multi-chip, improves life
Produce efficiency.
Step 2 provides at least one second encapsulating structure 200, and the second encapsulating structure 200 includes PCB substrate 17 and leads to
28 plastic packaging of substrate plastic-sealed body is crossed in 17 positive second functional chip 25 of the PCB substrate, second functional chip 25 and PCB
The matching electrical connection of substrate 17, is arranged on the substrate plastic-sealed body 28 and is electrically connected with the second functional chip 25 and PCB substrate 17
Substrate connection ball 34, in the back side of the PCB substrate 17 setting lower layer signal connecting line 22 and make lower layer signal connection
The lower layer signal connection opening 24 that line 22 exposes, the lower layer signal connecting line 22 is electrically connected with substrate connection ball 34；
As shown in Figure 15 ~ Figure 22, the preparation process of the second encapsulating structure 100 includes the following steps：
PCB substrate 17 needed for S1, offer is arranged symmetrical upper layer signal in the front of the PCB substrate 17 and connects
The lower layer signal connecting line 22 with upper layer signal connecting line 19 in corresponding distribution, institute is arranged at the back side of PCB substrate 17 in wiring 19
Lower layer signal connecting line 22 is stated to be electrically connected with corresponding upper layer signal connecting line 19 by the conducting connecting pole 18 in PCB substrate 17
It connects；
The front setting substrate upper layer passivation layer 20 of PCB substrate 17, substrate underlying passivation layer is arranged in the back side of PCB substrate 17
23, substrate upper layer passivation layer 20 covers the corresponding front of PCB substrate 17 and partial upper layer signal connecting line 19, to be made
Obtain the upper layer signal connection opening 21 that 19 desired zone of upper layer signal connecting line exposes；Substrate underlying passivation layer 23 covers PCB bases
The 17 corresponding back side of plate and partial lower layer signal connecting line 22, to obtain so that 19 desired zone of lower layer signal connecting line reveals
The lower layer signal connection opening 24 gone out, it 21 is in correspond point that lower layer signal connection opening 24, which connect with upper layer signal and is open,
Cloth；
As shown in figure 15, by the common technological means of the art, upper layer signal connecting line 19, base can be prepared
Plate upper layer passivation layer 20, upper layer signal connection opening 21, lower layer signal connecting line 22, substrate underlying passivation layer 23 and lower layer's letter
Number connection opening 24 with conducting connecting pole 18.
S2, the second functional chip 25 of front setting in above-mentioned PCB substrate 17, second functional chip 25 pass through second
Functional chip lead 27 and upper layer signal connection opening 21 are electrically connected with upper layer signal connecting line 19；
As shown in figure 16, the second functional chip 25 is welded on PCB substrate 17 by the second functional chip welding layer 26
Top can realize that fixed and heat dissipation effect, the second functional chip 25 are located at upper layer by the second functional chip welding layer 26
Between signal connection opening 21, electrical connection corresponding with upper layer signal connecting line 19 can be realized by the second functional chip lead 27.
S3, plastic packaging is carried out to above-mentioned PCB substrate 17, obtains gland on the second functional chip 25 and PCB substrate 17
Substrate plastic-sealed body 28；
As shown in figure 17,28 gland of substrate plastic-sealed body is in PCB substrate 17, by plastic packagings such as the second functional chips 25 in base
In plate plastic-sealed body 28.
S4, it drills to above-mentioned substrate plastic-sealed body 28, to obtain through substrate plastic-sealed body 28 and connect with upper layer signal
Connect 21 corresponding substrate plastic-sealed body through-holes 29 of opening；
As shown in figure 18, using laser drilling process, substrate plastic-sealed body through-hole 29 is obtained, passes through substrate plastic-sealed body through-hole 29
It can be so that upper layer signal connection opening 21 be exposed.
S5, plating filling is carried out to above-mentioned substrate plastic-sealed body through-hole 29, to obtain filling up substrate plastic-sealed body through-hole 29
Substrate plastic-sealed body packed column 30, the substrate plastic-sealed body packed column 30 are electrically connected with upper layer signal connecting line 19；
As shown in figure 19, by electroplating technology, substrate plastic-sealed body packed column 30 can be obtained.
S6, connection redistribution layer 31, the substrate plastic-sealed body on substrate plastic-sealed body are set on aforesaid substrate plastic-sealed body 28
The center gland of upper connection redistribution layer 31 connects redistribution layer 31 on substrate plastic-sealed body packed column 30 on substrate plastic-sealed body
It is electrically connected with substrate plastic-sealed body packed column 30；
As shown in figure 20, using the common technological means of the art, it can be prepared on substrate plastic-sealed body and connect weight
Distribution layer 31, connection redistribution layer 31 is covered on substrate plastic-sealed body packed column 30 on substrate plastic-sealed body, and in substrate plastic-sealed body
The both sides of packed column 30 extend outwardly, and following lower layer signal connection opening 24 corresponds to.
S7, third passivation layer 32 is set on aforesaid substrate plastic-sealed body 28, the third passivation layer 32 is covered in substrate modeling
It seals on body 28 and partial substrate plastic-sealed body in connection redistribution layer 31, so that connecting redistribution layer 31 on substrate plastic-sealed body
The third passivation layer opening 32 that end is exposed；
As shown in figure 21, the position that the position of the third passivation layer opening 32 connect opening 24 with lower layer signal is in face
It answers, i.e., third passivation layer opening 32 is located at the washed surface for connecting opening 24 of lower layer, in order to follow-up two adjacent second encapsulation
Connection cooperation between structure 200.
S8, using above-mentioned third passivation layer opening 32, connected on aforesaid substrate plastic-sealed body in redistribution layer 31 and weld base
Plate connected ball 34.
As shown in figure 22, the substrate connection ball 34 is tin ball；After welding substrate connected ball 34, the second encapsulating structure is obtained
200。
Second encapsulating structure 200 is passed through the wafer of lower layer signal connection opening 24 and the first encapsulating structure 100 by step 3
Chip connected ball 16 is aligned, and makes the second encapsulating structure 200 be stacked on the first encapsulating structure 100 by surface mount process
On.
As shown in Figure 23 and Figure 24, the second encapsulating structure 200 can be made to be stacked on the first envelope by surface mount process
On assembling structure 100.When being stacked with multiple second encapsulating structures 200 on the first encapsulating structure 100, the second envelope for being located above
The substrate connection ball 34 that assembling structure 200 connects 24 second encapsulating structures 200 adjacent with lower section of opening by lower layer signal is aligned,
And by surface mount process two the second adjacent encapsulating structures 200 are stacked integrally.
First encapsulating structure 100 of the invention realizes the encapsulating structure of multi-chip, the second encapsulation knot using WLCSP packaged types
Structure 200 is stacked on the first encapsulating structure 100 so that and obtained encapsulating structure size is small, identical as the size of chip wafer 2,
The capacity and production efficiency of raising encapsulating structure, reduction packaging cost, wide adaptation range, securely and reliably.
Claims (4)
1. a kind of high preparation method for stacking wafer system-in-package structure, characterized in that the preparation method includes following step
Suddenly：
The first encapsulating structure that step 1, offer are obtained by cutting crystal wafer grade chip package（100）, first encapsulating structure
（100）Including chip wafer（2）And pass through chip wafer plastic-sealed body（10）Plastic packaging is in the chip wafer（2）On the first work(
It can chip（7）, first functional chip（7）With chip wafer（2）Matching electrical connection, in the chip wafer plastic-sealed body（10）
It is upper to be arranged chip wafer（2）Draw the chip wafer connected ball of connection（16）；
Step 2 provides at least one second encapsulating structure（200）, the second encapsulating structure（200）Including PCB substrate（17）And
Pass through substrate plastic-sealed body（28）Plastic packaging is in the PCB substrate（17）Positive second functional chip（25）, the second function core
Piece（25）With PCB substrate（17）Matching electrical connection, in the substrate plastic-sealed body（28）Upper setting and the second functional chip（25）With
And PCB substrate（17）The substrate connection ball of electrical connection（34）, in the PCB substrate（17）The back side be arranged lower layer signal connecting line
（22）And make lower layer signal connecting line（22）The lower layer signal connection opening of exposing（24）, the lower layer signal connecting line
（22）With substrate connection ball（34）Electrical connection；
In step 2, the second encapsulating structure（100）Preparation process include the following steps：
（S1）, provide needed for PCB substrate（17）, in the PCB substrate（17）Front symmetrical upper layer signal is set
Connecting line（19）, in PCB substrate（17）The back side setting with upper layer signal connecting line（19）Lower layer signal in corresponding distribution connects
Wiring（22）, the lower layer signal connecting line（22）Pass through PCB substrate（17）Interior conducting connecting pole（18）With corresponding upper layer
Signal connecting line（19）Electrical connection；
PCB substrate（17）Front setting substrate upper layer passivation layer（20）, PCB substrate（17）The passivation of back side setting substrate lower layer
Layer（23）, substrate upper layer passivation layer（20）Cover PCB substrate（17）Corresponding front and partial upper layer signal connecting line
（19）, to obtain so that upper layer signal connecting line（19）The upper layer signal connection opening that desired zone exposes（21）；Substrate lower layer
Passivation layer（23）Cover PCB substrate（17）The corresponding back side and partial lower layer signal connecting line（22）, under being made
Layer signal connecting line（19）The lower layer signal connection opening that desired zone exposes（24）, the lower layer signal connection opening（24）With
Upper layer signal connection opening（21）It is distributed in corresponding；
（S2）, in above-mentioned PCB substrate（17）Front setting the second functional chip（25）, second functional chip（25）Pass through
Second functional chip lead（27）And upper layer signal connection opening（21）With upper layer signal connecting line（19）Electrical connection；
（S3）, to above-mentioned PCB substrate（17）Plastic packaging is carried out, obtains gland in the second functional chip（25）And PCB substrate
（17）On substrate plastic-sealed body（28）；
（S4）, to above-mentioned substrate plastic-sealed body（28）It drills, to obtain through substrate plastic-sealed body（28）And and upper layer signal
Connection opening（21）Corresponding substrate plastic-sealed body through-hole（29）；
（S5）, to above-mentioned substrate plastic-sealed body through-hole（29）Plating filling is carried out, to obtain filling up substrate plastic-sealed body through-hole（29）
Substrate plastic-sealed body packed column（30）, the substrate plastic-sealed body packed column（30）With upper layer signal connecting line（19）Electrical connection；
（S6）, in aforesaid substrate plastic-sealed body（28）Redistribution layer is connected on upper setting substrate plastic-sealed body（31）, the substrate plastic packaging
Redistribution layer is connected on body（31）Center gland in substrate plastic-sealed body packed column（30）On, it connects on substrate plastic-sealed body and divides again
Layer of cloth（31）With substrate plastic-sealed body packed column（30）Electrical connection；
（S7）, in aforesaid substrate plastic-sealed body（28）Upper setting third passivation layer（32）, the third passivation layer（32）It is covered in base
Plate plastic-sealed body（28）And connect redistribution layer on partial substrate plastic-sealed body（31）On, so that connecting weight on substrate plastic-sealed body
Distribution layer（31）The third passivation layer opening that end is exposed（32）；
（S8）, utilize above-mentioned third passivation layer opening（32）, redistribution layer is connected on aforesaid substrate plastic-sealed body（31）Upper welding
Substrate connection ball（34）；
Step 3, by the second encapsulating structure（200）It is connected and is open by lower layer signal（24）With the first encapsulating structure（100）Crystalline substance
Round core piece connected ball（16）Alignment, and the second encapsulating structure is made by surface mount process（200）It is stacked on the first encapsulation knot
Structure（100）On.
2. the high preparation method for stacking wafer system-in-package structure according to claim 1, characterized in that in the first encapsulation
Structure（100）On be stacked with multiple second encapsulating structures（200）When, the second encapsulating structure for being located above（200）Pass through lower layer
Signal connection opening（24）Second encapsulating structure adjacent with lower section（200）Substrate connection ball（34）Alignment, and pass through surface
Attachment process makes two the second adjacent encapsulating structures（200）It stacks integral.
3. the high preparation method for stacking wafer system-in-package structure according to claim 1, characterized in that in step 1, obtain
To the first encapsulating structure（100）Process include the following steps：
（a）, provide full wafer wafer（1）, the full wafer wafer（1）The upper chip wafer with several required structures（2）, Mei Gejing
Round core piece（2）On all have for inputting, exporting chip wafer connection pad（3）；
（b）, in the chip wafer（2）Upper setting chip wafer pad connects redistribution layer（4）, the chip wafer pad company
Connect redistribution layer（4）It connect pad with chip wafer（3）Electrical connection；
（c）, in above-mentioned chip wafer（2）The first passivation layer of upper setting（5）, first passivation layer（5）It is covered in chip wafer
（2）Corresponding surface and partial chip wafer pad connect redistribution layer（4）On, to obtain so that chip wafer pad connects
Connect redistribution layer（4）The first exposed passivation layer opening of end（6）；
（d）, in above-mentioned chip wafer（2）The first functional chip is arranged in top（7）, first functional chip（7）Positioned at first
Passivation layer opening（6）Between；
（e）, by the first above-mentioned functional chip（7）Pass through the first functional chip lead（9）Connect with corresponding chip wafer pad
Connect redistribution layer（4）Electrical connection；
（f）, to above-mentioned chip wafer（2）Plastic packaging is carried out, obtains gland in the first functional chip（7）And chip wafer（2）
On chip wafer plastic-sealed body（10）；
（g）, to above-mentioned chip wafer plastic-sealed body（10）It drills, to obtain perforation chip wafer plastic-sealed body（10）And with
One passivation layer opening（6）Corresponding wafer plastic-sealed body through-hole（11）；
（h）, to above-mentioned wafer plastic-sealed body through-hole（11）Plating filling is carried out, to obtain filling up wafer plastic-sealed body through-hole（11）'s
Wafer plastic-sealed body packed column（12）, the wafer plastic-sealed body packed column（12）It connect redistribution layer with chip wafer pad（4）Electricity
Connection；
（i）, in above-mentioned chip wafer plastic-sealed body（10）Redistribution layer is connected on upper setting wafer plastic-sealed body（13）, the wafer modeling
Redistribution layer is connected on envelope body（13）With wafer plastic-sealed body packed column（12）Electrical connection；
（j）, in above-mentioned chip wafer plastic-sealed body（10）The second passivation layer of upper setting（14）, second passivation layer（14）It is covered in
Chip wafer plastic-sealed body（10）And connect redistribution layer on partial wafer plastic-sealed body（13）On, to obtain so that wafer plastic packaging
Redistribution layer is connected on body（13）The second passivation layer opening that end is exposed（15）；
（k）, utilize above-mentioned second passivation layer opening（15）, by chip wafer connected ball（16）It is welded on wafer plastic-sealed body and connects
Redistribution layer（13）End；
（l）, to above-mentioned full wafer wafer（1）Cutting separation is carried out, to obtain the first required encapsulating structure（100）.
4. the high preparation method for stacking wafer system-in-package structure according to claim 1, characterized in that the substrate connects
It receives（34）For tin ball.
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| CN110060993B (en) * | 2019-04-26 | 2020-12-11 | 胡志刚 | Multi-layer chip architecture and connection method |
| CN111128979B (en) * | 2019-11-22 | 2022-08-16 | 中国电子科技集团公司第十三研究所 | Wafer-level 3D chip preparation method |
| CN117312066A (en) * | 2023-12-01 | 2023-12-29 | 成都电科星拓科技有限公司 | Method for realizing chip eutectic wafer, wafer and chip |
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| CN102646668A (en) * | 2011-02-17 | 2012-08-22 | 三星电子株式会社 | Semiconductor package having tsv interposer and method of manufacturing same |
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| CN102646668A (en) * | 2011-02-17 | 2012-08-22 | 三星电子株式会社 | Semiconductor package having tsv interposer and method of manufacturing same |
| CN103311192A (en) * | 2013-06-25 | 2013-09-18 | 华进半导体封装先导技术研发中心有限公司 | Thin-gap POP (Package on Package) type packaging structure and packaging method |
| CN104733403A (en) * | 2015-03-23 | 2015-06-24 | 华进半导体封装先导技术研发中心有限公司 | Wafer-level packaging structure and manufacturing method |
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