CN107464790A - Chip package array and chip package - Google Patents

Chip package array and chip package Download PDF

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Publication number
CN107464790A
CN107464790A CN201710655920.0A CN201710655920A CN107464790A CN 107464790 A CN107464790 A CN 107464790A CN 201710655920 A CN201710655920 A CN 201710655920A CN 107464790 A CN107464790 A CN 107464790A
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CN
China
Prior art keywords
chip
sealing
wafer
supporting construction
encapsulation body
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710655920.0A
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Chinese (zh)
Inventor
张文远
陈伟政
吕学忠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Zhaoxin Semiconductor Co Ltd
Original Assignee
VIA Alliance Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from TW106115539A external-priority patent/TWI674647B/en
Application filed by VIA Alliance Semiconductor Co Ltd filed Critical VIA Alliance Semiconductor Co Ltd
Publication of CN107464790A publication Critical patent/CN107464790A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Dicing (AREA)

Abstract

A chip package array and a chip package are provided, the chip package array includes a plurality of chip packages. The chip packages are adapted to be arranged in an array to form the array of chip packages. Each chip package includes a redistribution circuit structure, a support structure, a chip and a molding compound. The supporting structure is configured on the redistribution circuit structure and has an opening. The chip is disposed on the redistribution circuit structure and in the opening. The sealant is located between the opening and the chip, wherein the sealant is filled between the opening and the chip. The wafer and the supporting structure are respectively connected with the redistribution circuit structure. The invention can improve the structural strength and reduce the production cost of the manufacturing process.

Description

Wafer package array and wafer encapsulation body
Technical field
The invention relates to a kind of chip package structure, and in particular to a kind of wafer package array and chip Packaging body.
Background technology
In semiconductor industry, the production of integrated circuit (Integrated Circuits, IC), three are can be divided mainly into Stage：IC design (IC design), the making (IC process) of integrated circuit and the encapsulation (IC of integrated circuit Package) etc..Therefore, bare crystalline piece (die) is brilliant via wafer (wafer) making, circuit design, light shield manufacture and cutting The steps such as circle and complete, and bare crystalline piece then engages (wire bonding) or chip bonding (flip chip via routing The mode such as bonding), is electrically connected to carrier, such as lead frame or dielectric layer etc. so that the engagement of bare crystalline piece by bare crystalline piece Pad by can reroute road to chip periphery or chip active surface lower section.Then, then with packing colloid (molding Compound bare crystalline piece) is coated, to protect bare crystalline piece.
The content of the invention
The present invention provides a kind of wafer package array, lift structure intensity and can reduce the production cost of its processing procedure.
The present invention provides a kind of wafer encapsulation body, lift structure intensity and can reduce the production cost of its processing procedure.
The present invention separately proposes a kind of wafer package array, including multiple wafer encapsulation bodies.Wafer encapsulation body is arranged suitable for array Arrange to form the wafer package array.Each wafer encapsulation body includes rerouting line structure, supporting construction, chip and sealing.Branch Support structure is configured at rewiring line structure and has opening.Wafer configuration is in rewiring line structure and in opening.Sealing position Between opening and chip, wherein sealing is filled between opening and chip, and chip is with supporting construction respectively with rerouting road knot Structure connects.
The present invention reintroduces a kind of wafer encapsulation body, including reroutes line structure, supporting construction, chip and sealing.Branch Support structure is configured at rewiring line structure and has opening.Wafer configuration is in rewiring line structure and in opening.Sealing position Between opening and chip, wherein sealing is filled between opening and chip, and chip is with supporting construction respectively with rerouting road knot Structure connects.
Based on above-mentioned, in the wafer encapsulation procedure of the present invention, due to wafer package array each wafer encapsulation body it is outer Enclose region and be configured with supporting construction, accordingly, it is capable to improve the warpage occurred in encapsulation process, and wafer package array can be lifted Structural strength and the production cost for reducing its processing procedure, and then increase the yield of wafer encapsulation body.In addition, supporting construction is matched somebody with somebody The overall construction intensity of each wafer encapsulation body can also be improved by putting.
For features described above of the invention and advantage can be become apparent, special embodiment below, and coordinate institute's accompanying drawings It is described in detail below.
Brief description of the drawings
Figure 1A to Fig. 1 F is sequentially the schematic top plan view of the wafer encapsulation procedure of one embodiment of the invention.
Fig. 2A to Fig. 2 F is line A-A ' of Figure 1A to Fig. 1 F structure along Figure 1A diagrammatic cross-section respectively.
Fig. 3 A are schematic perspective view of Figure 1A and Fig. 2A structure under good working condition.
Fig. 3 B are schematic perspective view of Figure 1B and Fig. 2 B structure under good working condition.
Fig. 3 C are schematic perspective view of Fig. 1 E and Fig. 2 the E structure under good working condition.
Fig. 4 A are the schematic top plan view of the wafer encapsulation body of another embodiment of the present invention.
Fig. 4 B are the diagrammatic cross-section of the wafer encapsulation body of another embodiment of the present invention.
Fig. 5 is the diagrammatic cross-section of the wafer encapsulation body of another embodiment of the present invention.
Fig. 6 is the diagrammatic cross-section of the wafer encapsulation body of one more embodiment of the present invention.
Wherein, symbol is simply described as follows in accompanying drawing：
50：Wafer package array；100、100A、100B、100C：Wafer encapsulation body；102：Side；110：Loading plate； 120：Supporting construction；122：Opening；124：Top surface；126、126C：Inner face；128：Groove；130：Chip；130a：Connection pad；132： First face；140：Passive element；150、150A：Sealing；160：Reroute line structure；170：Soldered ball；P1：First reference planes； P2：Second reference planes；L：Line of cut.
Embodiment
The good working condition that refer to Figure 1A, Fig. 2A and Fig. 3 A, wherein Figure 1A and Fig. 2A structure as shown in Figure 3A, implies that figure The part of 3A structure is presented in Figure 1A and Fig. 2A.In the crystal package processing procedure of the present embodiment, there is provided supporting construction 120 and hold Support plate 110.Supporting construction 120 is configured on loading plate 110.Supporting construction 120 has multiple openings 122.Specifically, at this In embodiment, supporting construction 120 is a network structure, e.g. a netted reinforcement supporting member.Consequently, it is possible to pass through tool The supporting construction and loading plate for having multiple openings can improve the warpage occurred in encapsulation process, especially for larger-size fan Go out type wafer-level packaging (Fan-out wafer level package, FOWLP) or fan-out-type face Board level packaging (Fan-out Panel level package, FOPLP), its effect is more obvious.In addition, pass through the supporting construction with multiple openings 122 120 and loading plate 110 can lift the structural strength of wafer package array 50 (seeing Fig. 3 C) and reduce the production cost of its processing procedure, And then increase the yield of wafer encapsulation body 100 (seeing Fig. 1 F and Fig. 2 F).
Figure 1B, Fig. 2 B and Fig. 3 B are refer to, the wherein good working condition of Figure 1B and Fig. 2 B structure as shown in Figure 3 B, implies that figure The part of 3B structure is presented in Figure 1B and Fig. 2 B.After the above step, multiple chips 130 are configured on loading plate 110, its In these chips 130 respectively positioned at supporting construction 120 multiple openings 122 in.In the present embodiment, configured in an opening 122 One chip 130, the present invention is not limited.In other embodiments, multiple chips can be configured in an opening, it is to utilize heap Folded mode, it is configured in corresponding be open.In the present embodiment, step of the chip 130 on loading plate 110 is configured also to wrap Include, configure multiple passive elements 140 on loading plate 110, and between chip 130 and supporting construction 120.For example, One or more passive elements 140 can be configured in each opening 122, to meet electrical requirements.
Fig. 1 C and Fig. 2 C are refer to, after the above step, sealing 150 is formed and covers supporting construction 120 and chip 130, Between sealing 150 and loading plate 110, sealing 150 is filled in opening 122 and chip 130 for supporting construction 120 and chip 130 Between.In other words, in this step, sealing 150 is filled in supporting construction 120 and intactly covers supporting construction 120 and chip 130, to cause each opening 122 in supporting construction 120 to be all full of sealing 150 and then fixed support structure 120 and chip 130.In addition, sealing 150 also intactly covers passive element 140.
Fig. 1 D and Fig. 2 D are refer to, after the above step, remove loading plate 110.Because sealing 150 is filled in each Opening 122, therefore supporting construction 120 is fixedly secured to one another without separating with chip 130 by sealing 150.Now, support knot Structure 120, chip 130, passive element 140 and sealing 150 form one first reference planes P1, i.e., supporting construction 120, chip 130, Passive element 140 and the copline of sealing 150.
Fig. 1 E, Fig. 2 E and Fig. 3 C are refer to, the wherein good working condition of Fig. 1 E and Fig. 2 E structure as shown in Figure 3 C, implies that figure The part of 3C structure is presented in Fig. 1 E and Fig. 2 E.After the above step, configuration reroutes line structure 160 in supporting construction On 120 and chip 130 is directly connected, can be by script configuration on chip 130 by rerouting the configuration of line structure 160 Signal be fanned out to (fan-out) to reroute line structure 160 the projected area of chip 130 outside, and then increase chip 130 signal match somebody with somebody The elasticity put.In addition, reroute the Conductive layer portions of line structure 160 directly can be electrically connected with the connection pad 130a on chip 130, Without being additionally reconfigured at projection (bump).In other words, the configuration of line structure 160 is rerouted on the first reference planes P1 And it is directly connected chip 130.Further, it is also possible to configure multiple soldered balls 170 on line structure 160 is rerouted, and reroute Line structure 160 is located between chip 130 and these soldered balls 170.So far, a wafer package array 50 is completed, as shown in Figure 3 C, its Include multiple still uncut wafer encapsulation bodies 100.
Fig. 1 F and Fig. 2 F are refer to, after the above step, multiple line of cut L along between multiple openings 122 Cut crystal array of packages 50, to form single individual wafer encapsulation body 100, as depicted in Fig. 1 F and Fig. 2 F.In other words, each A part with supporting construction 120 in the wafer encapsulation body 100 formed along line of cut L cuttings supporting construction 120, and this Supporting construction 120 is the reinforcement supporting member of a ring-type for single individual wafer encapsulation body 100, and it can lift chip envelope Fill the overall construction intensity of body 100.For further, cut because the reinforcement supporting member of ring-type is aligned in line of cut L And formed, therefore reinforcement supporting member can be exposed to the side 102 of single individual wafer encapsulation body 100, therefore for wafer encapsulation body 100 For outer peripheral areas, there is provided stronger protection, similarly, sealing 150 and rewiring line structure 160 are also aligned in line of cut L is cut and causes a part for sealing 150 and a part for rewiring line structure 160 to be exposed to single individual wafer encapsulation body 100 side 102.
Fig. 1 E, Fig. 2 E and Fig. 3 C are refer again to, specifically, in the present embodiment, wafer package array 50 includes multiple Wafer encapsulation body 100, and wafer encapsulation body 100 is suitable to array and arranged to form wafer package array 50, as Fig. 3 C are presented.Respectively Wafer encapsulation body 100 includes rerouting line structure 160, supporting construction 120, chip 130 and sealing 150.Supporting construction 120 is matched somebody with somebody It is placed in rewiring line structure 160 and there is opening 122.Chip 130, which is configured at, reroutes line structure 160 and in opening 122. Sealing 150 is between opening 122 and chip 130, and wherein sealing 150 is filled between opening 122 and chip 130, chip 130 It is directly connected respectively with rerouting line structure 160 with supporting construction 120.In other words, wafer encapsulation body 100 is sealed by chip The dress cutting of array 50 forms, therefore reroutes line structure 160, supporting construction 120 and sealing 150 and be also cut and be formed at each In wafer encapsulation body 100.Because the outer peripheral areas of each wafer encapsulation body 100 of wafer package array 50 is configured with supporting construction 120, accordingly, it is capable to improve the warpage occurred in the encapsulation process of wafer package array 50, and wafer package array 50 can be lifted Structural strength and the production cost for reducing its processing procedure, and then increase the yield of wafer encapsulation body 100.In addition, supporting construction 120 configuration can also improve the overall construction intensity of each wafer encapsulation body 100.
Fig. 1 F and Fig. 2 F are refer again to, specifically, in the present embodiment, wafer encapsulation body 100 includes rerouting road knot Structure 160, supporting construction 120, chip 130 and sealing 150.Supporting construction 120 is configured to reroute line structure 160 and have and opened Mouth 122.Chip 130, which is configured at, reroutes line structure 160 and in opening 122.Sealing 150 is located at opening 122 and chip 130 Between, wherein sealing 150 is filled between opening 122 and chip 130, and chip 130 is with supporting construction 120 respectively with rerouting road Structure 160 is directly connected.Wherein wafer encapsulation body 100 is formed as wafer package array 50 (as depicted in Fig. 3 C) cutting, Therefore line structure 160, supporting construction 120 and sealing 150 is rerouted also to be cut and be formed in each wafer encapsulation body 100. Because the outer peripheral areas of wafer encapsulation body 100 is configured with supporting construction 120, accordingly, it is capable to improve the overall knot of wafer encapsulation body 100 Structure intensity.
Fig. 4 A and Fig. 4 B are refer to, the wafer encapsulation body 100A of the present embodiment is similar to Fig. 1 F and Fig. 2 F wafer encapsulation body 100, between the two Main Differences be sealing 150A configuration.Before the step of cut crystal array of packages 50, envelope is removed A part for glue 150 is to form sealing 150A and then make chip 130 exposed.Specifically, before the step of Fig. 2 F, removal portion Divide positioned at supporting construction 120 and the sealing 150 on chip 130, and retain the envelope between supporting construction 120 and chip 130 Glue 150A.Away from the top surface 124 and the remote weight cloth of chip 130 for rerouting line structure 160 in the supporting construction 120 of the present embodiment One first face 132 of line construction 160 is coplanar, i.e., on same second reference planes P2.Consequently, it is possible to chip 130 can be sudden and violent It is outer to contact heat dissipation conductor to be exposed to wafer encapsulation body 100A, and then wafer encapsulation body 100A is had more preferable thermal diffusivity.
Fig. 5 is refer to, the wafer encapsulation body 100B of the present embodiment is similar to Fig. 2 F wafer encapsulation body 100, between the two Main Differences are for example that the opening 122 of the present embodiment has an inner face 126, and inner face 126 has an at least groove 128, and seals Glue 150 is full of groove 128.Consequently, it is possible to it can be filled in by sealing 150 in groove 128 to ensure wafer encapsulation body 100B Overall construction intensity.In addition, in another embodiment, part sealing 150 can be further removed, and makes chip 130 naked Dew, similar to depicted in Fig. 4 A and Fig. 4 B.
Fig. 6 is refer to, the wafer encapsulation body 100C of the present embodiment is similar to Fig. 2 F wafer encapsulation body 100, between the two Main Differences are for example that the opening 122 of the present embodiment has an inner face 126C, and inner face 126C is directed away from the side of chip 130 To inclination so that sealing 150 extends to inner face 126C top.Stated differently, since inner face 126C inclined design, may be such that Supporting construction 120 is covered by the extension of sealing 150, and then supporting construction 120 is more closely connected with rerouting line structure 160 Connect and difficult for drop-off.Consequently, it is possible to inner face 126C can be covered by sealing 150 to ensure wafer encapsulation body 100C overall knot Structure intensity.In addition, in another embodiment, part sealing 150 can be further removed, and makes chip 130 exposed, is similar to Depicted in Fig. 4 A and Fig. 4 B.
In summary, in the wafer encapsulation procedure of the present invention, due to wafer package array each wafer encapsulation body it is outer Enclose region and be configured with supporting construction (now reinforcement supporting member can be exposed on the side of single individual wafer encapsulation body), because This, can improve the warpage occurred in encapsulation process, and can lift the structural strength of wafer package array and reduce its processing procedure Production cost, and then increase the yield of wafer encapsulation body.In addition, the configuration of supporting construction can also improve each wafer package The overall construction intensity of body.
Present pre-ferred embodiments are the foregoing is only, so it is not limited to the scope of the present invention, any to be familiar with sheet The personnel of item technology, without departing from the spirit and scope of the present invention, further can be improved and be changed on this basis, because This protection scope of the present invention is defined when the scope defined by following claims.

Claims (20)

  1. A kind of 1. wafer package array, it is characterised in that including：
    Multiple wafer encapsulation bodies, arranged suitable for array to form the wafer package array, respectively the wafer encapsulation body includes：
    Reroute line structure；
    Supporting construction, it is configured at the rewiring line structure and there is opening；
    Chip, it is configured at the rewiring line structure and in the opening；And
    Sealing, between the opening and the chip, the wherein sealing is filled between the opening and the chip, the chip and branch Support structure is connected with the rewiring line structure respectively.
  2. 2. wafer package array according to claim 1, it is characterised in that the supporting construction, the chip and the sealing Form copline.
  3. 3. wafer package array according to claim 1, it is characterised in that the chip includes an at least connection pad, the heavy cloth Line construction is directly connected an at least connection pad.
  4. 4. wafer package array according to claim 1, it is characterised in that tied in the supporting construction away from the rewiring road The top surface of structure and first face of the chip away from the rewiring line structure are coplanar.
  5. 5. wafer package array according to claim 1, it is characterised in that the sealing intactly cover the supporting construction with The chip.
  6. 6. wafer package array according to claim 1, it is characterised in that in the chip and the supporting construction at least its One of be exposed to the sealing.
  7. 7. wafer package array according to claim 1, it is characterised in that the opening has inner face, and the inner face has recessed Groove, and the sealing is full of the groove.
  8. 8. wafer package array according to claim 1, it is characterised in that the opening has an inner face, and this it is interior facing to Direction away from the chip tilts so that the sealing extends to the top of the inner face.
  9. 9. wafer package array according to claim 1, it is characterised in that respectively the wafer encapsulation body also includes：
    An at least passive element, the rewiring line structure is configured at, the wherein sealing intactly covers an at least passive element.
  10. 10. wafer package array according to claim 1, it is characterised in that the supporting construction is network structure.
  11. A kind of 11. wafer encapsulation body, it is characterised in that including：
    Reroute line structure；
    Supporting construction, it is configured at the rewiring line structure and there is opening；
    Chip, it is configured at the rewiring line structure and in the opening；And
    Sealing, between the opening and the chip, the wherein sealing is filled between the opening and the chip, the chip and branch Support structure is connected with the rewiring line structure respectively.
  12. 12. wafer encapsulation body according to claim 11, it is characterised in that the supporting construction, the chip and the sealing Form copline.
  13. 13. wafer encapsulation body according to claim 11, it is characterised in that the chip includes an at least connection pad, the heavy cloth Line construction is directly connected an at least connection pad.
  14. 14. wafer encapsulation body according to claim 11, it is characterised in that tied in the supporting construction away from the rewiring road The top surface of structure and first face of the chip away from the rewiring line structure are coplanar.
  15. 15. wafer encapsulation body according to claim 11, it is characterised in that the sealing intactly cover the supporting construction with The chip.
  16. 16. wafer encapsulation body according to claim 11, it is characterised in that in the chip and the supporting construction at least its One of be exposed to the sealing.
  17. 17. wafer encapsulation body according to claim 11, it is characterised in that the opening has inner face, and the inner face has recessed Groove, and the sealing is full of the groove.
  18. 18. wafer encapsulation body according to claim 11, it is characterised in that the opening has an inner face, and this it is interior facing to Direction away from the chip tilts so that the sealing extends to the top of the inner face.
  19. 19. wafer encapsulation body according to claim 11, it is characterised in that also include：
    An at least passive element, the rewiring line structure is configured at, the wherein sealing intactly covers an at least passive element.
  20. 20. wafer encapsulation body according to claim 11, it is characterised in that the supporting construction is exposed to the wafer encapsulation body Side.
CN201710655920.0A 2016-08-29 2017-08-03 Chip package array and chip package Pending CN107464790A (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201662380960P 2016-08-29 2016-08-29
US62/380,960 2016-08-29
TW106115539A TWI674647B (en) 2016-08-29 2017-05-11 Chip package array and chip package
TW106115539 2017-05-11

Publications (1)

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CN107464790A true CN107464790A (en) 2017-12-12

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160005628A1 (en) * 2014-07-01 2016-01-07 Freescal Semiconductor, Inc. Wafer level packaging method and integrated electronic package
CN205177808U (en) * 2015-11-18 2016-04-20 上海兆芯集成电路有限公司 Chip packaging structure
US20160111364A1 (en) * 2013-12-16 2016-04-21 Chipmos Technologies Inc. Chip package structure

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160111364A1 (en) * 2013-12-16 2016-04-21 Chipmos Technologies Inc. Chip package structure
US20160005628A1 (en) * 2014-07-01 2016-01-07 Freescal Semiconductor, Inc. Wafer level packaging method and integrated electronic package
CN205177808U (en) * 2015-11-18 2016-04-20 上海兆芯集成电路有限公司 Chip packaging structure

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