TWI674647B - Chip package array and chip package - Google Patents

Abstract

A chip package array includes a plurality of chip packages. The chip package is suitable for array arrangement to form the chip package array. Each chip package includes a redistribution circuit structure, a support structure, a chip, and a sealant. The supporting structure is disposed in the redistribution circuit structure and has an opening. The chip is disposed in the redistribution circuit structure and is located in the opening. The sealant is located between the opening and the wafer, and the sealant is filled between the opening and the wafer. The wafer and the support structure are respectively connected to the redistribution circuit structure. A chip package is also provided here.

Description

Chip package array and chip package

The present invention relates to a chip package structure, and more particularly, to a chip package array and a chip package.

In the semiconductor industry, the production of integrated circuits (ICs) can be divided into three stages: integrated circuit design (IC design), integrated circuit manufacturing (IC process), and integrated circuit packaging ( IC package) and so on. Therefore, the die is completed through wafer fabrication, circuit design, photomask fabrication, and wafer dicing, and the bare wafer is processed through wire bonding or flip chip bonding. ) And other methods to electrically connect the bare chip to a carrier, such as a lead frame or a dielectric layer, so that the bonding pads of the bare chip can be rerouted to the periphery of the chip or below the active surface of the chip. Then, the bare wafer is covered with a molding compound to protect the bare wafer.

The invention provides a chip package array, which can improve the structural strength and reduce the production cost of its manufacturing process.

The invention provides a chip package, which can improve the structural strength and reduce the production cost of its manufacturing process.

The present invention further provides a chip package array including a plurality of chip packages. The chip package is suitable for array arrangement to form the chip package array. Each chip package includes a redistribution circuit structure, a support structure, a chip, and a sealant. The supporting structure is disposed in the redistribution circuit structure and has an opening. The chip is disposed in the redistribution circuit structure and is located in the opening. The sealant is located between the opening and the wafer, wherein the sealant is filled between the opening and the wafer, and the wafer and the support structure are respectively connected to the redistribution circuit structure.

The present invention further provides a chip package, which includes a redistribution circuit structure, a support structure, a chip, and a sealant. The supporting structure is disposed in the redistribution circuit structure and has an opening. The chip is disposed in the redistribution circuit structure and is located in the opening. The sealant is located between the opening and the wafer, wherein the sealant is filled between the opening and the wafer, and the wafer and the support structure are respectively connected to the redistribution circuit structure.

Based on the above, in the chip packaging process of the present invention, since a support structure is arranged in the peripheral region of each chip package body of the chip package array, warpage occurring during the packaging process can be improved, and the structure of the chip package array can be improved. The strength and the production cost of the manufacturing process are reduced, thereby increasing the output of the chip package. In addition, the configuration of the support structure can also improve the overall structural strength of each chip package.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

Please refer to FIG. 1A, FIG. 2A, and FIG. 3A. The complete state of the structure of FIG. 1A and FIG. 2A is shown in FIG. 3A, which means that a part of the structure of FIG. In the crystal packaging process of this embodiment, a support structure 120 and a carrier plate 110 are provided. The support structure 120 is disposed on the carrier plate 110. The support structure 120 has a plurality of openings 122. In detail, in this embodiment, the supporting structure 120 is a mesh structure, such as a mesh-shaped reinforcing support. In this way, the support structure and the carrier plate with multiple openings can improve the warping that occurs during the packaging process, especially for larger fan-out wafer level packages (FOWLP) Or Fan-out panel level package (FOPLP), the effect is more obvious. In addition, the support structure 120 and the carrier plate 110 having multiple openings 122 can improve the structural strength of the chip package array 50 (see FIG. 3C) and reduce the production cost of the process, thereby increasing the chip package 100 (see FIG. 1F and Figure 2F).

Please refer to FIG. 1B, FIG. 2B, and FIG. 3B. The complete state of the structure of FIG. 1B and FIG. 2B is shown in FIG. 3B, which means that a part of the structure of FIG. 3B is shown in FIG. 1B and FIG. 2B. After the above steps, a plurality of wafers 130 are disposed on the carrier plate 110, wherein the wafers 130 are respectively located in the plurality of openings 122 of the support structure 120. In this embodiment, a wafer 130 is disposed in an opening 122, but the present invention is not limited thereto. In other embodiments, a plurality of wafers can be arranged in an opening, which are arranged in a corresponding opening in a stacking manner. In this embodiment, the step of disposing the wafer 130 on the carrier plate 110 further includes disposing a plurality of passive elements 140 on the carrier plate 110 and located between the wafer 130 and the support structure 120. For example, one or more passive components 140 may be configured in each opening 122 to meet electrical requirements.

Please refer to FIG. 1C and FIG. 2C. After the above steps, a sealant 150 is formed to cover the support structure 120 and the wafer 130. The support structure 120 and the wafer 130 are located between the sealant 150 and the carrier plate 110. The sealant 150 is filled in the opening 122 and Between the wafers 130. In other words, in this step, the sealant 150 is filled on the support structure 120 and completely covers the support structure 120 and the wafer 130 so that each opening 122 in the support structure 120 is filled with the sealant 150 to fix the support. Structure 120 and wafer 130. In addition, the sealant 150 also completely covers the passive element 140.

Please refer to FIG. 1D and FIG. 2D. After the above steps, the carrier plate 110 is removed. Since the sealant 150 fills each of the openings 122, the support structure 120 and the chip 130 are fixedly connected to each other by the sealant 150 without separation. At this time, the support structure 120, the chip 130, the passive component 140 and the sealant 150 constitute a first reference plane P1, that is, the support structure 120, the wafer 130, the passive component 140 and the sealant 150 are coplanar.

Please refer to FIG. 1E, FIG. 2E, and FIG. 3C. The complete state of the structure of FIG. 1E and FIG. 2E is shown in FIG. 3C, which means that a part of the structure of FIG. 3C is shown in FIG. 1E and FIG. 2E. After the above steps, the redistribution wiring structure 160 is arranged on the support structure 120 and directly connected to the chip 130. By the redistribution wiring structure 160 configuration, the signal originally arranged on the wafer 130 can be fan-out. To the outside of the projection area of the chip 130 of the redistribution circuit structure 160, the flexibility of the signal configuration of the chip 130 is increased. In addition, the conductive layer portion of the redistribution circuit structure 160 can be electrically connected directly to the pads 130 a on the chip 130 without the need for additional bumps. In other words, the redistribution wiring structure 160 is disposed on the first reference plane P1 and is directly connected to the chip 130. In addition, a plurality of solder balls 170 may be disposed on the redistribution circuit structure 160, and the redistribution circuit structure 160 is located between the wafer 130 and the solder balls 170. So far, a chip package array 50 is completed, as shown in FIG. 3C, which includes a plurality of chip packages 100 that have not been cut.

Please refer to FIG. 1F and FIG. 2F. After the above steps, the chip package array 50 is cut along a plurality of cutting lines L between the plurality of openings 122 to form a single chip package 100, as shown in FIGS. 1F and 2F. Draw. In other words, each chip package 100 formed by cutting the support structure 120 along the cutting line L has a part of the support structure 120, and the support structure 120 is a ring shape for a single chip package 100. The reinforcing support can improve the overall structural strength of the chip package 100. Furthermore, since the ring-shaped reinforcing support is formed by being aligned with the cutting line L for cutting, the reinforcing support is exposed to the side 102 of a single chip package 100. Therefore, for the peripheral area of the chip package 100, Provides strong protection. Similarly, the sealant 150 and the redistribution circuit structure 160 are also aligned with the cutting line L to be cut so that part of the sealant 150 and the redistribution circuit structure 160 are exposed to a single chip package 100.的 侧 102。 The side 102.

Please refer to FIG. 1E, FIG. 2E and FIG. 3C again. Specifically, in this embodiment, the chip package array 50 includes a plurality of chip packages 100, and the chip packages 100 are suitable for array arrangement to form the chip package array 50 As shown in Figure 3C. Each chip package 100 includes a redistribution circuit structure 160, a support structure 120, a chip 130, and an encapsulant 150. The supporting structure 120 is disposed on the redistribution circuit structure 160 and has an opening 122. The chip 130 is disposed in the redistribution circuit structure 160 and is located in the opening 122. The sealant 150 is located between the opening 122 and the wafer 130, wherein the sealant 150 is filled between the opening 122 and the wafer 130, and the wafer 130 and the support structure 120 are directly connected to the redistribution circuit structure 160, respectively. In other words, the chip package 100 is cut from the chip package array 50, so the redistribution circuit structure 160, the support structure 120, and the sealant 150 are also cut to form each chip package 100. Since the support structure 120 is disposed in the peripheral area of each of the chip package arrays 100 of the chip package array 50, the warpage occurring during the package process of the chip package array 50 can be improved, and the structural strength of the chip package array 50 can be improved and its The production cost of the process further increases the output of the chip package 100. In addition, the configuration of the support structure 120 can also improve the overall structural strength of the respective chip packages 100.

Please refer to FIG. 1F and FIG. 2F again. Specifically, in this embodiment, the chip package 100 includes a redistribution circuit structure 160, a support structure 120, a chip 130, and an encapsulant 150. The supporting structure 120 is disposed on the redistribution circuit structure 160 and has an opening 122. The chip 130 is disposed in the redistribution circuit structure 160 and is located in the opening 122. The sealant 150 is located between the opening 122 and the wafer 130, wherein the sealant 150 is filled between the opening 122 and the wafer 130, and the wafer 130 and the support structure 120 are directly connected to the redistribution circuit structure 160, respectively. The chip package 100 is cut from the chip package array 50 (shown in FIG. 3C). Therefore, the redistribution circuit structure 160, the support structure 120 and the sealant 150 are also cut to form the chip packages 100. Since the support structure 120 is disposed in the peripheral region of the chip package 100, the overall structural strength of the chip package 100 can be improved.

Please refer to FIGS. 4A and 4B. The chip package 100A of this embodiment is similar to the chip package 100 of FIGS. 1F and 2F, but the main difference between the two is the configuration of the sealant 150A. Prior to the step of dicing the chip package array 50, a part of the sealant 150 is removed to form a sealant 150A to expose the wafer 130. In detail, before the step of FIG. 2F, a part of the sealant 150 located on the support structure 120 and the wafer 130 is removed, and the sealant 150A located between the support structure 120 and the wafer 130 is retained. A top surface 124 of the support structure 120 far from the redistribution circuit structure 160 in this embodiment and a first surface 132 of the wafer 130 far from the redistribution circuit structure 160 are coplanar, that is, located on the same second reference plane P2. In this way, the chip 130 can be exposed to the outside of the chip package 100A to contact the heat dissipation conductor, so that the chip package 100A has better heat dissipation.

Please refer to FIG. 5. The chip package 100B of this embodiment is similar to the chip package 100 of FIG. 2F, but the main difference between the two is, for example, that the opening 122 of this embodiment has an inner surface 126, and the inner surface 126 has at least one The groove 128 is filled with the sealant 150. In this way, the overall structural strength of the chip package 100B can be ensured by filling the groove 128 with the sealant 150. In addition, in another embodiment, a part of the sealant 150 may be further removed, so that the chip 130 is exposed, similar to that shown in FIGS. 4A and 4B.

Please refer to FIG. 6. The chip package 100C of this embodiment is similar to the chip package 100 of FIG. 2F, but the main difference between the two is that the opening 122 of this embodiment has an inner surface 126C, and the inner surface 126C faces away from The direction of the wafer 130 is inclined, so that the sealant 150 extends above the inner surface 126C. In other words, due to the inclined design of the inner surface 126C, the support structure 120 can be covered by the extension of the sealant 150, so that the support structure 120 and the redistribution circuit structure 160 are more closely connected and are not easy to fall off. In this way, the overall structural strength of the chip package 100C can be ensured by covering the inner surface 126C with the sealant 150. In addition, in another embodiment, a part of the sealant 150 may be further removed, so that the chip 130 is exposed, similar to that shown in FIGS. 4A and 4B.

In summary, in the wafer packaging process of the present invention, since the peripheral regions of the respective chip packages of the chip package array are configured with supporting structures (at this time, the reinforcing support members will be exposed on the sides of a single chip package) Therefore, the warpage occurring during the packaging process can be improved, and the structural strength of the chip packaging array can be improved, and the production cost of its manufacturing process can be reduced, thereby increasing the yield of the chip package. In addition, the configuration of the support structure can also improve the overall structural strength of each chip package.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

50‧‧‧ Wafer Package Array

100, 100A, 100B, 100C‧‧‧ Chip Packages

102‧‧‧ side

110‧‧‧carrying plate

120‧‧‧ support structure

122‧‧‧ opening

124‧‧‧Top

126, 126C‧‧‧ inside

128‧‧‧ groove

130‧‧‧Chip

130a‧‧‧ pad

132‧‧‧ the first side

140‧‧‧Passive components

150, 150A‧‧‧ Sealant

160‧‧‧ Redistribution line structure

170‧‧‧Solder Ball

P1‧‧‧first reference plane

P2‧‧‧Second reference plane

L‧‧‧ cutting line

1A to FIG. 1F are schematic top views of a chip packaging process according to an embodiment of the present invention in sequence. 2A to 2F are schematic cross-sectional views of the structure of FIGS. 1A to 1F along the line A-A 'of FIG. 1A, respectively. 3A is a schematic perspective view of the structure of FIGS. 1A and 2A in a complete state. 3B is a schematic perspective view of the structure of FIGS. 1B and 2B in a complete state. 3C is a schematic perspective view of the structure of FIG. 1E and FIG. 2E in a complete state. 4A is a schematic top view of a chip package according to another embodiment of the present invention. 4B is a schematic cross-sectional view of a chip package according to another embodiment of the present invention. FIG. 5 is a schematic cross-sectional view of a chip package according to another embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of a chip package according to another embodiment of the present invention.

Claims (16)

A chip package array includes: a plurality of chip packages suitable for array arrangement to form the chip package array, each of the chip packages includes: a redistribution circuit structure; a support structure disposed on the redistribution circuit structure and having An opening; a wafer disposed in the redistribution circuit structure and located in the opening; and an adhesive between the opening and the wafer, wherein the sealant is filled between the opening and the wafer, the wafer and the support The structure is respectively connected to the redistribution circuit structure, the sealant completely covers the support structure and the wafer, and the support structure, the wafer and the sealant constitute a coplanar plane. The chip package array according to item 1 of the patent application scope, wherein the chip includes at least one pad, and the redistribution circuit structure directly connects the pads. The chip package array according to item 1 of the scope of the patent application, wherein a top surface of the support structure far from the redistribution circuit structure and a first surface of the chip far from the redistribution circuit structure are coplanar. The chip package array according to item 1 of the patent application scope, wherein the opening has an inner surface, the inner mask has a groove, and the sealant fills the groove. The chip package array according to item 1 of the scope of patent application, wherein the opening has an inner surface, and the inner surface is inclined away from the wafer, so that the sealant extends above the inner surface. The chip package array according to item 1 of the scope of the patent application, wherein each of the chip package bodies further comprises: at least one passive component disposed in the redistribution circuit structure, wherein the sealant completely covers the at least one passive component. The chip package array according to item 1 of the patent application scope, wherein the support structure is a mesh structure. A chip package includes: a redistribution circuit structure; a support structure disposed in the redistribution circuit structure and having an opening; a wafer disposed in the redistribution circuit structure and located in the opening; and a glue at Between the opening and the wafer, wherein the sealant is filled between the opening and the wafer, the wafer and the support structure are respectively connected to the redistribution wiring structure, and the sealant completely covers the support structure and the wafer, and The support structure, the wafer and the sealant form a coplanar plane. The chip package according to item 8 of the patent application scope, wherein the chip includes at least one pad, and the redistribution circuit structure directly connects the pads. According to the chip package of claim 8, a top surface of the support structure far from the redistribution circuit structure and a first surface of the chip far from the redistribution circuit structure are coplanar. The chip package according to item 8 of the patent application scope, wherein the opening has an inner surface, the inner mask has a groove, and the sealant fills the groove. According to the chip package of claim 8, the opening has an inner surface, and the inner surface is inclined away from the wafer, so that the sealant extends above the inner surface. The chip package according to item 8 of the scope of patent application, further comprising: at least one passive component disposed in the redistribution circuit structure, wherein the sealant completely covers the at least one passive component. The chip package according to item 8 of the patent application scope, wherein the support structure is exposed on a side of the chip package. A chip package array includes: a plurality of chip packages suitable for array arrangement to form the chip package array, each of the chip packages includes: a redistribution circuit structure; a support structure disposed on the redistribution circuit structure and having a An opening; a wafer disposed in the redistribution circuit structure and located in the opening; and an adhesive between the opening and the wafer, wherein the sealant is filled between the opening and the wafer, the wafer and the support The structure is respectively connected to the redistribution circuit structure, and at least one of the chip and the supporting structure is exposed to the sealant. A chip package includes: a redistribution circuit structure; a support structure disposed in the redistribution circuit structure and having an opening; a wafer disposed in the redistribution circuit structure and located in the opening; and a glue at Between the opening and the wafer, the sealant fills the opening Between the mouth and the wafer, the wafer and the supporting structure are respectively connected to the redistribution wiring structure, and at least one of the wafer and the supporting structure is exposed to the sealant.