TWI719205B - Chip package process - Google Patents

Abstract

A chip package process includes the following steps. A supporting structure and a carrier plate are provided. The supporting structure has a plurality of openings. The supporting structure is disposed on the carrier plate. A plurality of chips is disposed on the carrier plate. The chips are respectively located in the openings of the supporting structure. A molding compound is formed to cover the supporting structure and the chips. The supporting structure and the chips are located between the molding compound and the carrier plate. The molding compound is filled between the openings and the chips. The carrier plate is removed. A redistribution structure is disposed on the supporting structure, wherein the redistribution structure is connected to the chips.

Description

Chip packaging process

The present invention relates to a chip package, and more particularly to a chip package process and a chip package array.

In the semiconductor industry, the production of integrated circuits (Integrated Circuits, IC) can be divided into three stages: IC design, IC process, and packaging of integrated circuits. IC package) and so on. Therefore, the bare chip is completed through the steps of wafer fabrication, circuit design, mask fabrication, and wafer dicing, while the bare chip is completed through wire bonding or flip chip bonding. ), etc., electrically connect the bare chip to a carrier, such as a lead frame or a dielectric layer, so that the bonding pads of the bare chip can be redistributed to the periphery of the chip or below the active surface of the chip. Then, the bare chip is covered with a molding compound to protect the bare chip.

The invention provides a chip packaging process, which can improve the structural strength and reduce the production cost of the process.

The present invention provides a chip packaging process, which includes the following steps. Provide supporting structure and load-bearing board. The support structure has a plurality of openings. The supporting structure is arranged on the bearing plate. Multiple wafers are arranged on the carrier board. A plurality of wafers are respectively located in a plurality of openings of the supporting structure. A sealant is formed to cover the supporting structure and a plurality of wafers. The supporting structure and a plurality of chips are located between the sealing compound and the carrier board. The sealing compound is filled between the plurality of openings and the plurality of chips. Remove the carrier plate. The redistributed circuit structure is arranged on the support structure, and the redistributed circuit structure is connected to a plurality of chips.

Based on the above, in the chip packaging process of the present invention, since the peripheral area of each chip package of the chip package array is provided with a support structure, the warpage that occurs during the packaging process can be improved, and the structure of the chip package array can be improved. Strength and reduce the production cost of the manufacturing process, thereby increasing the output of the chip package. In addition, the configuration of the support structure can also improve the overall structural strength of the individual chip packages.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

Please refer to FIG. 1A, FIG. 2A and FIG. 3A. The complete state of the structure of FIG. 1A and FIG. 2A is shown in FIG. 3A, which means that a part of the structure of FIG. 3A is shown in FIG. 1A and FIG. 2A. In the crystal packaging process of this embodiment, the supporting structure 120 and the carrying plate 110 are provided. The supporting structure 120 is configured on the supporting board 110. The supporting structure 120 has a plurality of openings 122. In detail, in this embodiment, the support structure 120 is a net-like structure, for example, a net-like reinforced support. In this way, the support structure and the carrier plate with multiple openings can improve the warpage that occurs during the packaging process, especially for the larger fan-out wafer level package (FOWLP). Or fan-out panel level package (FOPLP), the effect is more obvious. In addition, the support structure 120 and the carrier plate 110 having a plurality of openings 122 can increase the structural strength of the chip package array 50 (see FIG. 3C) and reduce the production cost of the manufacturing process, thereby increasing the chip package 100 (see FIG. 1F and Figure 2F) Yield.

Please refer to FIG. 1B, FIG. 2B, and FIG. 3B. The complete state of the structure of FIG. 1B and FIG. 2B is shown in FIG. 3B, which means that a part of the structure of FIG. 3B is shown in FIG. 1B and FIG. 2B. After the above steps, a plurality of wafers 130 are arranged on the carrier plate 110, wherein the wafers 130 are respectively located in the plurality of openings 122 of the supporting structure 120. In this embodiment, a chip 130 is disposed in an opening 122, and the invention is not limited to this. In other embodiments, multiple wafers can be arranged in one opening, which are arranged in the corresponding opening in a stacking manner. In this embodiment, the step of arranging the wafer 130 on the carrier board 110 further includes arranging a plurality of passive components 140 on the carrier board 110 and located between the wafer 130 and the supporting structure 120. For example, one or more passive components 140 may be disposed in each opening 122 to meet electrical requirements.

1C and 2C, after the above steps, a sealant 150 is formed to cover the support structure 120 and the chip 130. The support structure 120 and the chip 130 are located between the sealant 150 and the carrier plate 110. The sealant 150 is filled in the opening 122 and Between the wafers 130. In other words, in this step, the encapsulant 150 is filled on the supporting structure 120 and completely covers the supporting structure 120 and the chip 130, so that each opening 122 in the supporting structure 120 is filled with the encapsulant 150 to fix the support. Structure 120 and wafer 130. In addition, the sealant 150 also completely covers the passive component 140.

Please refer to FIG. 1D and FIG. 2D. After the above steps, the carrier plate 110 is removed. Since the encapsulant 150 fills each opening 122, the support structure 120 and the chip 130 are fixedly connected to each other by the encapsulant 150 without being separated. At this time, the support structure 120, the chip 130, the passive element 140 and the encapsulant 150 constitute a first reference plane P1, that is, the support structure 120, the chip 130, the passive element 140 and the encapsulant 150 are coplanar.

Please refer to FIG. 1E, FIG. 2E, and FIG. 3C. The complete state of the structure of FIG. 1E and FIG. 2E is shown in FIG. 3C, which means that a part of the structure of FIG. 3C is shown in FIG. 1E and FIG. 2E. After the above steps, the redistributed circuit structure 160 is arranged on the support structure 120 and directly connected to the chip 130. With the configuration of the redistributed circuit structure 160, the signal originally arranged on the chip 130 can be fan-out. The redistribution circuit structure 160 is outside the projection area of the chip 130, thereby increasing the flexibility of the signal configuration of the chip 130. In addition, the conductive layer portion of the redistributed circuit structure 160 can be directly electrically connected to the pad 130a on the chip 130 without additional bumps. In other words, the redistributed circuit structure 160 is located on the first reference plane P1 and directly connected to the chip 130. In addition, a plurality of solder balls 170 may be arranged on the redistributed circuit structure 160, and the redistributed circuit structure 160 is located between the chip 130 and the solder balls 170. So far, a chip package array 50 is completed, as shown in FIG. 3C, which includes a plurality of chip packages 100 that have not been diced.

1F and 2F, after the above steps, the chip package array 50 is cut along a plurality of cutting lines L between the openings 122 to form a single chip package 100, as shown in FIGS. 1F and 2F Illustrated. In other words, each chip package 100 formed by cutting the supporting structure 120 along the cutting line L has a part of the supporting structure 120, and the supporting structure 120 is a ring shape for a single chip package 100 The strengthening support can improve the overall structural strength of the chip package 100. Furthermore, since the ring-shaped reinforcing support is formed by aligning with the cutting line L for cutting, the reinforcing support will be exposed on the side surface 102 of a single chip package 100. Therefore, for the peripheral area of the chip package 100, Provides strong protection. Similarly, the encapsulant 150 and the redistributed circuit structure 160 are also aligned with the cutting line L and cut so that a part of the encapsulant 150 and a part of the redistributed circuit structure 160 are exposed to a single chip package 100的面102。 The side 102.

Please refer to FIG. 1E, FIG. 2E and FIG. 3C again. Specifically, in this embodiment, the chip package array 50 includes a plurality of chip packages 100, and the chip packages 100 are suitable for array arrangement to form the chip package array 50. As shown in Figure 3C. Each chip package 100 includes a redistributed circuit structure 160, a supporting structure 120, a chip 130 and a sealing compound 150. The supporting structure 120 is disposed on the redistributed circuit structure 160 and has an opening 122. The chip 130 is disposed in the redistributed circuit structure 160 and located in the opening 122. The encapsulant 150 is located between the opening 122 and the chip 130, and the encapsulant 150 is filled between the opening 122 and the chip 130, and the chip 130 and the supporting structure 120 are respectively directly connected to the redistributed circuit structure 160. In other words, the chip package 100 is formed by cutting the chip package array 50, so the redistributed circuit structure 160, the supporting structure 120, and the encapsulant 150 are also cut to be formed in each chip package 100. Since the peripheral area of the respective chip package body 100 of the chip package array 50 is provided with the support structure 120, the warpage that occurs during the packaging process of the chip package array 50 can be improved, and the structural strength of the chip package array 50 can be improved and reduced. The production cost of the manufacturing process further increases the output of the chip package 100. In addition, the configuration of the supporting structure 120 can also improve the overall structural strength of the individual chip packages 100.

Please refer to FIG. 1F and FIG. 2F again. Specifically, in this embodiment, the chip package 100 includes a redistributed circuit structure 160, a support structure 120, a chip 130, and an encapsulant 150. The supporting structure 120 is disposed on the redistributed circuit structure 160 and has an opening 122. The chip 130 is disposed in the redistributed circuit structure 160 and located in the opening 122. The encapsulant 150 is located between the opening 122 and the chip 130, and the encapsulant 150 is filled between the opening 122 and the chip 130, and the chip 130 and the supporting structure 120 are respectively directly connected to the redistributed circuit structure 160. The chip package 100 is formed by cutting the chip package array 50 (as shown in FIG. 3C). Therefore, the redistributed circuit structure 160, the supporting structure 120, and the encapsulant 150 are also cut to be formed in each chip package 100. Since the peripheral area of the chip package 100 is provided with the support structure 120, the overall structural strength of the chip package 100 can be improved.

Please refer to FIGS. 4A and 4B. The chip package 100A of this embodiment is similar to the chip package 100 of FIGS. 1F and 2F, but the main difference between the two lies in the configuration of the encapsulant 150A. Before the step of dicing the chip package array 50, a part of the encapsulant 150 is removed to form the encapsulant 150A so that the chip 130 is exposed. In detail, before the step of FIG. 2F, part of the encapsulant 150 on the support structure 120 and the wafer 130 is removed, and the encapsulant 150A between the support structure 120 and the wafer 130 is retained. In the present embodiment, a top surface 124 of the support structure 120 away from the redistributed circuit structure 160 is coplanar with a first surface 132 of the wafer 130 away from the redistributed circuit structure 160, that is, located on the same second reference plane P2. In this way, the chip 130 can be exposed to the outside of the chip package 100A to contact the heat dissipation conductors, so that the chip package 100A has better heat dissipation.

Please refer to FIG. 5, the chip package 100B of this embodiment is similar to the chip package 100 of FIG. 2F, but the main difference between the two is that the opening 122 of this embodiment has an inner surface 126, and the inner surface 126 has at least one The groove 128, and the sealing compound 150 fills the groove 128. In this way, the encapsulant 150 can be filled in the groove 128 to ensure the overall structural strength of the chip package 100B. In addition, in another embodiment, part of the encapsulant 150 may be further removed, leaving the chip 130 exposed, similar to those shown in FIGS. 4A and 4B.

Please refer to FIG. 6, the chip package 100C of this embodiment is similar to the chip package 100 of FIG. 2F, but the main difference between the two is that the opening 122 of this embodiment has an inner surface 126C, and the inner surface 126C faces away from The direction of the chip 130 is inclined so that the sealing compound 150 extends above the inner surface 126C. In other words, due to the inclined design of the inner surface 126C, the support structure 120 can be covered by the extension of the sealant 150, so that the support structure 120 and the redistributed circuit structure 160 are more closely connected and not easy to fall off. In this way, the inner surface 126C can be covered by the sealant 150 to ensure the overall structural strength of the chip package 100C. In addition, in another embodiment, part of the encapsulant 150 may be further removed, leaving the chip 130 exposed, similar to those shown in FIGS. 4A and 4B.

To sum up, in the chip packaging process of the present invention, because the peripheral area of each chip package of the chip package array is provided with a support structure (in this case, the reinforcing support will be exposed on the side of the single chip package) Therefore, the warpage occurring during the packaging process can be improved, the structural strength of the chip package array can be improved, and the production cost of the manufacturing process can be reduced, thereby increasing the output of the chip package. In addition, the configuration of the support structure can also improve the overall structural strength of the individual chip packages.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

50: chip package array

100, 100A, 100B, 100C: chip package

102: side

110: Carrier plate

120: Supporting structure

122: open

124: top surface

126, 126C: inside

128: Groove

130: chip

130a: pad

132: The first side

140: Passive components

150, 150A: sealant

160: heavy line structure

170: solder ball

P1: the first reference plane

P2: Second reference plane

L: Cutting line

1A to 1F are a schematic top view of a chip packaging process according to an embodiment of the present invention in sequence. 2A to 2F are cross-sectional schematic diagrams of the structure of FIGS. 1A to 1F along the line A-A' of FIG. 1A, respectively. FIG. 3A is a three-dimensional schematic diagram of the structure of FIG. 1A and FIG. 2A in a complete state. FIG. 3B is a three-dimensional schematic diagram of the structure of FIG. 1B and FIG. 2B in a complete state. FIG. 3C is a three-dimensional schematic diagram of the structure of FIG. 1E and FIG. 2E in a complete state. 4A is a schematic top view of a chip package according to another embodiment of the invention. 4B is a schematic cross-sectional view of a chip package according to another embodiment of the invention. 5 is a schematic cross-sectional view of a chip package according to another embodiment of the present invention. 6 is a schematic cross-sectional view of a chip package according to still another embodiment of the present invention.

50‧‧‧Chip Package Array

100‧‧‧Chip package

120‧‧‧Supporting structure

122‧‧‧Open

130‧‧‧chip

140‧‧‧Passive components

150‧‧‧Sealant

160‧‧‧Relay line structure

L‧‧‧Cutting line

Claims (10)

A chip packaging process includes: providing a supporting structure and a carrying plate, wherein the supporting structure has a plurality of openings, and the supporting structure is arranged on the carrying plate; and a plurality of chips are arranged on the carrying plate, wherein the chips are respectively Located in the openings of the supporting structure, each of the chips has an active surface, and the active surface is directly disposed on the carrier plate; a sealant is formed to cover the supporting structure and the chips, and the supporting structure and the chips are located Between the encapsulant and the carrier board, the encapsulant is filled between the openings and the chips; remove all the carrier board; and arrange a redistributed circuit structure on the support structure, wherein the redistributed circuit The structure is connected to the chips, and the support structure is electrically insulated from the redistributed circuit structure, wherein the support structure is not located between the chips and the redistributed circuit structure, and is located on the support structure on the redistributed circuit structure It is a mesh structure. According to the chip packaging process described in claim 1, wherein in the step of removing the carrier board, the supporting structure, the chips, and the encapsulant form a coplanar plane. According to the chip packaging process described in claim 1, wherein in the step of arranging a redistributed circuit structure on the supporting structure, each of the chips includes at least one pad, and the redistributed circuit structure directly connects the pads . The chip packaging process described in item 1 of the scope of patent application further includes: Remove a part of the encapsulant to expose the chips. As described in the first item of the patent application, the chip packaging process further includes: cutting the support structure and the redistributed circuit structure along a plurality of cutting lines between the openings to form a plurality of chip packages. According to the chip packaging process described in item 5 of the scope of patent application, a part of the supporting structure is exposed to a corresponding side surface of the chip package. According to the chip packaging process described in claim 1, wherein each of the openings has an inner surface, the inner surface has at least one groove, and the sealant fills at least the groove. In the chip packaging process described in claim 1, wherein each of the openings has an inner surface, and the inner surface is inclined in a direction away from the chip, so that the sealant extends above the inner surface. According to the chip packaging process described in claim 1, wherein the step of disposing a plurality of chips on the carrier board includes: disposing a plurality of passive components on the carrier board, wherein the sealing compound completely covers the passive components . According to the chip packaging process described in item 5 of the scope of patent application, the supporting structure is a ring-shaped reinforcing support member of each chip package.

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