CN113345847B - Chip packaging structure and manufacturing method thereof - Google Patents

Chip packaging structure and manufacturing method thereof Download PDF

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Publication number
CN113345847B
CN113345847B CN202010246021.7A CN202010246021A CN113345847B CN 113345847 B CN113345847 B CN 113345847B CN 202010246021 A CN202010246021 A CN 202010246021A CN 113345847 B CN113345847 B CN 113345847B
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China
Prior art keywords
wafer
chip
circuit layer
layer
reconfiguration circuit
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CN202010246021.7A
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Chinese (zh)
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CN113345847A (en
Inventor
曾子章
刘汉诚
柯正达
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Unimicron Technology Suzhou Corp
Unimicron Technology Corp
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Unimicron Technology Suzhou Corp
Unimicron Technology Corp
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Publication of CN113345847A publication Critical patent/CN113345847A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

Abstract

The invention provides a chip packaging structure and a manufacturing method thereof. At least one diced wafer is provided. A carrier plate having an adhesive layer disposed thereon is provided. The diced wafer is positioned on the carrier plate by the adhesive layer. A redistribution layer is formed on the diced wafer. The diced wafer is electrically connected with the reconfiguration circuit layer. And performing a singulation process on the diced wafer and the reconfiguration circuit layer to form a plurality of chip packaging structures. The manufacturing method of the chip packaging structure can have higher yield and can effectively reduce the production cost.

Description

Chip packaging structure and manufacturing method thereof
Technical Field
The present disclosure relates to packaging structures and methods for manufacturing the same, and particularly to a chip packaging structure and a method for manufacturing the same.
Background
With advances in electronics, semiconductor device dimensions have been scaled down while providing more powerful functions and including larger capacity integrated circuits. Wafer level chip scale packages (wafer level chip scale package, WLCSP) are widely used in manufacturing due to the miniaturization of semiconductor devices.
In the case of Wafer Level Chip Scale Package (WLCSP), a technique of packaging a single wafer by means of semiconductor devices and semiconductor processes and then cutting the wafer to obtain a chip package structure is known. However, since Wafer Level Chip Scale Packaging (WLCSP) uses semiconductor devices and semiconductor processes, manufacturing costs cannot be effectively reduced. In addition, in each process, only one wafer is manufactured, and thus the productivity cannot be effectively improved.
Disclosure of Invention
The invention is directed to a chip package structure and a method for manufacturing the same, which can have a higher yield (high throughput) and reduce the production cost.
According to an embodiment of the invention, a method for manufacturing a chip package structure includes the following steps. At least one diced wafer is provided. A carrier plate having an adhesive layer disposed thereon is provided. The diced wafer is positioned on the carrier plate by the adhesive layer. A redistribution layer is formed on the diced wafer. The diced wafer is electrically connected with the reconfiguration circuit layer. And performing a singulation process on the diced wafer and the reconfiguration circuit layer to form a plurality of chip packaging structures.
In the method for manufacturing a chip package structure according to an embodiment of the present invention, the method for manufacturing a chip package structure further includes: when the cut wafer is provided, at least one uncut wafer is provided at the same time. Before the cut wafer is positioned on the carrier plate through the adhesive layer, a plate with at least one first opening and at least one second opening is provided on the adhesive layer. The plate is positioned on the bearing plate through the adhesive layer. The uncut wafer and the cut wafer are respectively arranged in the first opening and the second opening and are positioned on the bearing plate through the adhesive layer.
In the method for manufacturing the chip package structure according to the embodiment of the invention, the outline of the first opening is equal to or greater than the outline of the uncut wafer. The outline of the second opening is equal to or larger than the outline of the cut wafer.
In the method for manufacturing the chip package structure according to the embodiment of the invention, the uncut wafer has a first active surface and a first back surface opposite to each other. The diced wafer has a second active surface and a second back surface opposite to each other. The first back surface of the uncut wafer is in direct contact with the adhesive layer with the second back surface of the cut wafer.
In the method for manufacturing the chip package structure according to the embodiment of the invention, the plate has an upper surface, and the first active surface of the uncut wafer and the second active surface of the cut wafer are aligned to the upper surface of the plate.
In the method for manufacturing the chip package structure according to the embodiment of the invention, the uncut wafer includes a plurality of first pads disposed on the first active surface. The diced wafer includes a plurality of second pads disposed on the second active surface. The first and second pads are electrically connected to the reconfiguration circuit layer respectively.
In the method for manufacturing a chip package structure according to an embodiment of the present invention, the method for manufacturing a chip package structure further includes: before the singulated wafer and the reconfiguration circuit layer are subjected to the singulation process, a plurality of solder balls are formed on the reconfiguration circuit layer. The solder balls are electrically connected with the diced wafer through the reconfiguration circuit layer.
In the method for manufacturing a chip package structure according to an embodiment of the present invention, the method for manufacturing a chip package structure further includes: after forming solder balls on the reconfiguration circuit layer and before performing a singulation process on the diced wafer and the reconfiguration circuit layer, the carrier plate and the adhesive layer are removed.
In the method for manufacturing a chip package according to the embodiment of the invention, the outline of the diced wafer is at least composed of a straight line and an arc line connecting the straight line.
According to an embodiment of the invention, a method for manufacturing a chip package structure includes the following steps. At least one diced wafer is provided. A carrier plate having an adhesive layer disposed thereon is provided. The diced wafer is positioned on the carrier plate by the adhesive layer. The diced wafer is subjected to a first singulation process to form a plurality of chips that are positioned on the carrier plate by the adhesive layer. Forming an encapsulation colloid on the adhesion layer, wherein the encapsulation colloid encapsulates the chip. The carrier and the adhesive layer are removed to expose the bottom surface of the encapsulant. And forming a reconfiguration circuit layer on the bottom surface of the packaging colloid, wherein the reconfiguration circuit layer is electrically connected with the chip. And performing a second singulation process on the encapsulant, the chip and the reconfiguration circuit layer to form a plurality of chip package structures.
In the method for manufacturing the chip packaging structure according to the embodiment of the invention, the method further comprises the following steps: when the cut wafer is provided, at least one uncut wafer is provided at the same time. The uncut wafer has a first active surface and a first back surface opposite to each other. The diced wafer has a second active surface and a second back surface opposite to each other. The first active surface of the uncut wafer and the second active surface of the cut wafer are in direct contact with the adhesive layer.
In the method for manufacturing the chip package structure according to the embodiment of the invention, the two adjacent chips have a horizontal spacing therebetween, and the horizontal spacing is 30 micrometers to 100 micrometers.
In the method for manufacturing the chip package structure according to the embodiment of the invention, the method for manufacturing the adjacent chip package structure further includes: before the second monomer process is performed on the packaging colloid, the chip and the reconfiguration circuit layer, a plurality of solder balls are formed on the reconfiguration circuit layer, wherein the solder balls are electrically connected with the chip through the reconfiguration circuit layer.
In the method for manufacturing the chip packaging structure according to the embodiment of the invention, a horizontal distance is formed between the edge of the adjacent packaging colloid and the peripheral surface of the chip, and the horizontal distance is 15 micrometers to 50 micrometers.
In the method for manufacturing a chip package according to the embodiment of the invention, the outline of the adjacent cut wafers is at least formed by straight lines and arcs connecting the straight lines.
According to an embodiment of the invention, a chip package structure includes a chip and a reconfiguration line layer. The chip has an active surface and a back surface opposite to each other, and includes a plurality of pads disposed on the active surface. The reconfiguration circuit layer is configured on the active surface of the chip and is electrically connected with the connecting pad.
In the chip package structure according to an embodiment of the present invention, further comprising: the solder balls are configured on the reconfiguration circuit layer and are electrically connected with the connecting pads of the chip through the reconfiguration circuit layer.
In the chip package structure according to the embodiment of the invention, the edges of the chip are aligned with the edges of the reconfiguration line layer.
In the chip package structure according to an embodiment of the present invention, further comprising: the packaging colloid is configured on the reconfiguration circuit layer and coats the chip, wherein the packaging colloid covers the back surface of the chip.
In the chip package structure according to the embodiment of the invention, the edge of the encapsulant is aligned with the edge of the reconfiguration line layer.
Based on the above, in the method for manufacturing a chip package structure of the present invention, a plurality of chip packages are formed by forming a reconfiguration circuit layer on at least one diced wafer and performing a singulation process. Compared with the existing manufacturing method of wafer-level chip size package for only one complete uncut wafer at a time, the manufacturing method of the chip package structure of the invention has higher yield and can effectively reduce the production cost.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
Fig. 1A to 1F are schematic diagrams illustrating a method for manufacturing a chip package structure according to an embodiment of the invention;
fig. 2A to fig. 2G are schematic diagrams illustrating a method for manufacturing a chip package structure according to another embodiment of the invention.
Description of the reference numerals
10, a bearing plate;
12, an adhesive layer;
20, a plate;
an upper surface;
22a, a first opening;
22b, a second opening;
100, a chip packaging structure;
110. 210, a chip;
110a, 210b, uncut wafer;
110b, 210c, 210d, 210e, 210f: diced wafers;
111. 211, an active surface;
111a, 211 a;
111b, 211 c;
112. 212, a connecting pad;
112a, a first pad;
112b, a second pad;
113. 213, back;
113a, 213a, a first back side;
113b, 213c, a second back side;
115. 121, 221, 231;
120. 120', 230' reconfigure the line layer;
130. 240, solder balls;
215 a peripheral surface;
220. 220';
222: a bottom surface;
C. c1 and C2 are arcs;
g, horizontal spacing;
h, horizontal distance;
s, S1, S2.
Detailed Description
Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
Fig. 1A to 1F are schematic diagrams illustrating a method for manufacturing a chip package structure according to an embodiment of the invention. For convenience of explanation, fig. 1A and 1C are shown in top view, and fig. 1B, 1D to 1F are shown in cross section.
Referring to fig. 1A, at least one diced wafer (schematically shown as a diced wafer 110 b) is provided. Here, the outline of the diced wafer 110b is specifically formed by a straight line S and an arc line C connecting the straight line S, but not limited thereto.
As shown in fig. 1A, the present embodiment provides at least one uncut wafer (schematically shown as an uncut wafer 110 a) along with a cut wafer 110 b. Here, the size of the uncut wafer 110a is larger than the size of the cut wafer 110b, wherein the outline of the uncut wafer 110a is embodied as a circle.
Next, referring to fig. 1B, a carrier plate 10 having an adhesive layer 12 disposed thereon is provided. Here, the adhesive layer 12 is, for example, a double-sided thermal adhesive tape (thermal release tape), and the carrier board 10 is, for example, a printed circuit board or a temporary substrate without electrical functions, but not limited thereto.
Next, referring to fig. 1C, in order to increase the yield of the subsequent process, a plate 20 having at least one first opening (schematically shown as a first opening 22 a) and at least one second opening (schematically shown as a second opening 22 b) may be selectively provided. Here, the board 20 is, for example, a printed circuit board or a temporary substrate without electrical functions, but not limited thereto.
Next, referring to fig. 1A, 1C and 1D, the plate 20 is disposed on the adhesive layer 12 of the carrier plate 10, wherein the plate 20 is positioned on the carrier plate 10 by the adhesive layer 12. Then, the uncut wafer 110a and the cut wafer 110b are positioned on the carrier plate 10 by the adhesive layer 12. Here, the uncut wafer 110a and the cut wafer 110b are disposed in the first opening 22a and the second opening 22b, respectively, and are positioned on the carrier plate 10 by the adhesive layer 12. Preferably, the profile of the first opening 22a is equal to or greater than the profile of the uncut wafer 110 a. The second opening 22b has a contour equal to or greater than the contour of the diced wafer 110 b.
Further, in the present embodiment, the uncut wafer 110a has a first active surface 111a and a first back surface 113a opposite to each other. The diced wafer 110b has a second active surface 111b and a second backside surface 113b opposite to each other. The first backside 113a of the uncut wafer 110a and the second backside 113b of the diced wafer 110b are in direct contact with the adhesive layer 12. That is, the uncut wafer 110a and the cut wafer 110b of the present embodiment are disposed on the carrier plate 10 in an active-face-up (face-up) manner.
Furthermore, the plate 20 of the present embodiment has an upper surface 21, and the first active surface 111a of the uncut wafer 110a and the second active surface 111b of the cut wafer 110b are aligned with the upper surface 21 of the plate 20. That is, the upper surface 21 of the plate 20, the first active surface 111a of the uncut wafer 110a, and the second active surface 111b of the cut wafer 110b are coplanar, so as to improve the process yield of the subsequent reconfiguration circuit layer 120 (see fig. 1E). In addition, the uncut wafer 110a of the present embodiment further includes a plurality of first pads 112a disposed on the first active surface 111a, and the cut wafer 110b further includes a plurality of second pads 112b disposed on the second active surface 111 b.
Thereafter, referring to fig. 1E, a redistribution layer 120 is formed on the uncut wafer 110a and the diced wafer 110b, wherein the first pads 112a of the uncut wafer 110a and the second pads 112b of the diced wafer 110b are electrically connected to the redistribution layer 120, respectively. Next, a plurality of solder balls 130 are formed on the redistribution layer 120, wherein the solder balls 130 are electrically connected to the uncut wafer 110a and the diced wafer 110b through the redistribution layer 120.
Finally, referring to fig. 1E and fig. 1F, the plate 20, the carrier 10 and the adhesive layer 12 on the carrier 10 are removed, and the dicing process is performed on the uncut wafer 110a and the redistribution layer 120, and the diced wafer 110b and the redistribution layer 120 to form a plurality of chip packages (a chip package 100 is schematically shown). Thus, the method for manufacturing the chip package structure 100 is completed.
In terms of structure, referring to fig. 1F again, the chip package structure 100 of the present embodiment includes a chip 110 and a reconfiguration circuit layer 120'. The chip 110 has an active surface 111 and a back surface 113 opposite to each other, and includes a plurality of pads 112 disposed on the active surface 111. The reconfiguration circuit layer 120 'is disposed on the active surface 111 of the chip 110 and electrically connected to the pads 112, wherein the reconfiguration circuit layer 120' is, for example, a fan-in circuit. Here, the edge 115 of the chip 110 is aligned with the edge 121 of the reconfiguration line layer 120'. In addition, the chip package structure 100 of the present embodiment further includes a plurality of solder balls 130 disposed on the redistribution layer 120', and electrically connected to the pads 112 of the chip 110 through the redistribution layer 120'.
In the method for manufacturing the chip package structure 100 of the present embodiment, the reconfiguration circuit layer 120 is formed on at least one uncut wafer 110a and at least one cut wafer 110b, and the singulation process is performed, so as to form the chip package structure 100. Compared to the conventional wafer-level chip-scale package manufacturing method for only one wafer at a time, the manufacturing method of the chip package structure 100 of the present embodiment can have a higher yield. In addition, the chip package structure 100 is manufactured by the circuit board process and the apparatus thereof, so that the production cost can be effectively reduced.
It should be noted that in the above embodiment, only one uncut wafer 110a and one cut wafer 110b are schematically shown on the carrier plate 10, but not limited thereto. In essence, the number of the uncut wafers 110a and the cut wafers 110b may be determined according to the size of the carrier plate 10, and the profile shape of the cut wafers 110b may be determined according to the area of the carrier plate 10 left after the uncut wafers 110a are disposed, so that the maximum space can be utilized for disposition.
It should be noted that the following embodiments use the element numbers and part of the content of the foregoing embodiments, where the same numbers are used to denote the same or similar elements, and descriptions of the same technical content are omitted. For the description of the omitted parts, reference is made to the foregoing embodiments, and the following embodiments are not repeated.
Fig. 2A to fig. 2G are schematic diagrams illustrating a method for manufacturing a chip package structure according to another embodiment of the invention. For convenience of explanation, fig. 2A is shown in a top view, and fig. 2B to 2G are shown in cross-section.
Referring to fig. 2A, at least one diced wafer (four diced wafers 210c, 210d, 210e, 210f are schematically shown) is provided. Here, the outline of the diced wafer 210C, 210d, 210f is formed by the straight line S and the arc line C connecting the straight line S, and the outline of the diced wafer 210e is formed by the two straight lines S1, S2 and the two arc lines C1, C2 connecting the two straight lines S1, S2, but not limited thereto.
As shown in fig. 2A, at least one uncut wafer (two uncut wafers 210a, 210b are schematically shown) is provided along with cut wafers 210c, 210d, 210e, 210 f. Here, the dimensions of the uncut wafers 210a, 210b are larger than those of the cut wafers 210c, 210d, 210e, 210f, wherein the outline of the uncut wafers 210a, 210b is embodied as a circle.
Next, referring to fig. 2B, a carrier plate 10 having an adhesive layer 12 disposed thereon is provided. Here, the adhesive layer 12 is, for example, but not limited to, a double-sided thermal adhesive tape (thermal release tape). Next, the uncut wafer (only the uncut wafer 210a is schematically shown) and the cut wafer (only the cut wafer 210c is schematically shown) are positioned on the carrier plate 10 through the adhesive layer 12. Here, the uncut wafer 210a has a first active surface 211a and a first back surface 213a opposite to each other. The diced wafer 210c has a second active surface 211c and a second backside surface 213c opposite to each other. The first active surface 211a of the uncut wafer 210a and the second active surface 211c of the diced wafer 210c directly contact the adhesive layer 12. In other words, the uncut wafer 210a and the cut wafer 210c of the present embodiment are disposed on the carrier 10 in an active-down (face-down) manner.
Next, referring to fig. 2C, a first singulation process is performed on the uncut wafer (only the uncut wafer 210a is schematically shown) and the cut wafer (only the cut wafer 210C is schematically shown) to form a plurality of chips 210 positioned on the carrier plate 10 by the adhesive layer 12. Here, the adjacent two chips 210 have a horizontal pitch G, and the horizontal pitch G is 30 micrometers to 100 micrometers, which may have a better package margin.
Next, referring to fig. 2D, an encapsulant 220 is formed on the adhesive layer 12, wherein the encapsulant 220 encapsulates the chip 210.
Next, referring to fig. 2E, the carrier 10 and the adhesive layer 12 are removed, so as to expose the bottom surface 222 of the encapsulant 220. At this time, the active surface 211 of the chip 210 is aligned with the bottom surface 222 of the encapsulant 220.
Then, referring to fig. 2F, a redistribution layer 230 is formed on the bottom surface 222 of the encapsulant 220, wherein the redistribution layer 230 is electrically connected to the chip 210. Next, a plurality of solder balls 240 are formed on the redistribution layer 230, wherein the solder balls 230 are electrically connected to the pads 212 of the chip 210 through the redistribution layer 230.
Finally, referring to fig. 2G, a second singulation process is performed on the encapsulant 220, the chip 210, and the reconfiguration wire layer 230 to form a plurality of chip packages 200. Thus, the chip package structure 200 with the encapsulant 220 is completed.
In terms of structure, referring to fig. 2G again, the chip package structure 200 of the present embodiment includes a chip 210 and a reconfiguration line layer 230'. The chip 210 has an active surface 211 and a back surface 213 opposite to each other, and includes a plurality of pads 212 disposed on the active surface 211. The redistribution layer 230 'is disposed on the active surface 211 of the chip 210 and electrically connected to the pad 212, wherein the redistribution layer 230' is, for example, a fan-out line. Furthermore, the chip package structure 200 of the present embodiment further includes a molding compound 220' disposed on the redistribution layer 230' and encapsulating the chip 210, wherein the molding compound 220' covers the back surface 213 of the chip 210. Here, the edge 221 of the encapsulant 220' is aligned with the edge 231 of the redistribution layer 230. The edge 221 of the encapsulant 220' has a horizontal distance from the peripheral surface 215 of the chip 210, and the horizontal distance H is 15 micrometers to 50 micrometers to protect the chip 210. In addition, the chip package structure 200 of the present embodiment further includes a plurality of solder balls 240 disposed on the redistribution layer 230', and electrically connected to the pads 212 of the chip 210 through the redistribution layer 230'.
In summary, in the method for manufacturing a chip package according to the present invention, a plurality of chip packages are formed by forming a redistribution layer on at least one diced wafer and performing a singulation process. Compared with the existing manufacturing method of wafer-level chip size package for one wafer at a time, the manufacturing method of the chip package structure can have higher yield and can effectively reduce the production cost.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims (18)

1. The manufacturing method of the chip packaging structure is characterized by comprising the following steps:
providing at least one diced wafer;
providing a bearing plate provided with an adhesive layer;
positioning the at least one diced wafer on the carrier plate through the adhesive layer;
forming a reconfiguration circuit layer on the at least one diced wafer, wherein the at least one diced wafer is electrically connected with the reconfiguration circuit layer;
performing a singulation process on the at least one diced wafer and the reconfiguration circuitry layer to form a plurality of chip package structures;
providing at least one uncut wafer while providing the at least one cut wafer;
providing a plate having at least one first opening and at least one second opening on the adhesive layer before the at least one diced wafer is positioned on the carrier plate by the adhesive layer, the plate being positioned on the carrier plate by the adhesive layer; and
the at least one uncut wafer and the at least one cut wafer are respectively arranged in the at least one first opening and the at least one second opening and are positioned on the bearing plate through the adhesive layer.
2. The method of claim 1, wherein the at least one first opening has an outline equal to or greater than an outline of the at least one uncut wafer, and the at least one second opening has an outline equal to or greater than an outline of the at least one cut wafer.
3. The method of claim 1, wherein the at least one uncut wafer has a first active surface and a first back surface opposite to each other, and the at least one diced wafer has a second active surface and a second back surface opposite to each other, the first back surface of the at least one uncut wafer and the second back surface of the at least one diced wafer directly contact the adhesive layer.
4. The method of claim 3, wherein the plate has an upper surface, and the first active surface of the at least one uncut wafer and the second active surface of the at least one cut wafer are aligned with the upper surface of the plate.
5. The method of claim 3, wherein the at least one uncut wafer includes a plurality of first pads disposed on the first active surface, and the at least one diced wafer includes a plurality of second pads disposed on the second active surface, the plurality of first pads and the plurality of second pads being electrically connected to the redistribution layer.
6. The method of manufacturing a chip package structure according to claim 1, further comprising:
before the singulation process is performed on the at least one diced wafer and the reconfiguration circuit layer, a plurality of solder balls are formed on the reconfiguration circuit layer, wherein the plurality of solder balls are electrically connected with the at least one diced wafer through the reconfiguration circuit layer.
7. The method of manufacturing a chip package structure according to claim 6, further comprising:
after forming the solder balls on the reconfiguration circuit layer and before performing the singulation process on the at least one diced wafer and the reconfiguration circuit layer, the carrier plate and the adhesive layer are removed.
8. The method of claim 1, wherein the at least one diced wafer has an outline that is formed of at least a straight line and an arc line connecting the straight line.
9. The manufacturing method of the chip packaging structure is characterized by comprising the following steps:
providing at least one diced wafer;
providing a bearing plate provided with an adhesive layer;
positioning the at least one diced wafer on the carrier plate through the adhesive layer;
performing a first singulation process on the at least one diced wafer to form a plurality of chips positioned on the carrier plate by the adhesive layer;
forming an encapsulation colloid on the adhesion layer, wherein the encapsulation colloid encapsulates the plurality of chips;
removing the bearing plate and the adhesive layer to expose the bottom surface of the packaging colloid;
forming a reconfiguration circuit layer on the bottom surface of the packaging colloid, wherein the reconfiguration circuit layer is electrically connected with the chips;
performing a second singulation process on the encapsulant, the plurality of chips, and the reconfiguration circuit layer to form a plurality of chip package structures; and
providing at least one cut wafer, and simultaneously providing at least one uncut wafer, wherein the at least one uncut wafer is provided with a first active surface and a first back surface which are opposite to each other, and the at least one cut wafer is provided with a second active surface and a second back surface which are opposite to each other, and the first active surface of the at least one uncut wafer and the second active surface of the at least one cut wafer are in direct contact with the adhesive layer.
10. The method of claim 9, wherein two adjacent chips have a horizontal pitch between them, and the horizontal pitch is 30 micrometers to 100 micrometers.
11. The method of manufacturing a chip package structure according to claim 9, further comprising:
before the second singulation process is performed on the encapsulant, the plurality of chips, and the reconfiguration circuit layer, a plurality of solder balls are formed on the reconfiguration circuit layer, where the plurality of solder balls are electrically connected with the plurality of chips through the reconfiguration circuit layer.
12. The method of claim 9, wherein the edge of the encapsulant has a horizontal distance from the peripheral surface of the chip, and the horizontal distance is 15 micrometers to 50 micrometers.
13. The method of claim 9, wherein the at least one diced wafer has an outline that is formed of at least a straight line and an arc line connecting the straight line.
14. A chip package structure manufactured by the method for manufacturing a chip package structure according to any one of claims 1 to 13, comprising:
the chip is provided with an active surface and a back surface which are opposite to each other, and comprises a plurality of connecting pads arranged on the active surface; and
the reconfiguration circuit layer is configured on the active surface of the chip and is electrically connected with the plurality of connection pads.
15. The chip package structure of claim 14, further comprising:
the solder balls are configured on the reconfiguration circuit layer and are electrically connected with the plurality of connection pads of the chip through the reconfiguration circuit layer.
16. The chip package structure of claim 14, wherein an edge of the chip is aligned with an edge of the reconfiguration line layer.
17. The chip package structure of claim 14, further comprising:
and the packaging colloid is configured on the reconfiguration circuit layer and coats the chip, wherein the packaging colloid covers the back surface of the chip.
18. The chip package structure of claim 17, wherein an edge of the encapsulant is aligned with an edge of the redistribution trace layer.
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