CN100373614C - Packing structure of multichip - Google Patents
Packing structure of multichip Download PDFInfo
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- CN100373614C CN100373614C CNB2004100888870A CN200410088887A CN100373614C CN 100373614 C CN100373614 C CN 100373614C CN B2004100888870 A CNB2004100888870 A CN B2004100888870A CN 200410088887 A CN200410088887 A CN 200410088887A CN 100373614 C CN100373614 C CN 100373614C
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
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Abstract
The present invention relates to a packaging structure of multiple wafers, which comprises a first base plate, a first wafer, a primary packaging structure and first sealing glue, wherein the first wafer is attached to the first base plate; the first chip, a secondary packaging structure and the upper surface of the first base plate are covered with the first sealing glue; the lower surface of the secondary packaging structure is attached to the first chip. The secondary packaging structure comprises a second base plate, a second wafer and second sealing glue, wherein the second base plate which is provided with an upper surface and a lower surface is electrically connected with the first wafer; the second wafer which is attached to the upper surface of the second base plate is electrically connected with the second base plate; the second wafer and part of the upper surface of the second base plate are covered with the second sealing glue. Furthermore, the present invention solves the problem of larger area occupied by a plurality of packaging structures which are arranged in parallel; the paths for signal transmission between the wafers do not need designing again.
Description
Technical field
The invention relates to a kind of semiconductor package, particularly a kind of encapsulating structure that contains one encapsulating structure.
Background technology
High density for electronic product, the demand of high-performance and cost control has been quickened SoC (System On a Chip, SOC) and single encapsulation (the System In a Package of system, SIP) development, present most widely used encapsulation technology is polycrystalline sheet module encapsulation construction (Multi-ChipModule, MCM), it is the wafer of integrated difference in functionality, microprocessor (microprocessors) for example, internal memory (memory), logic element (logic), optical integrated circuit (optic ICs) and capacitor (capacitors) placed the individual package structure on one circuit board to replace before.
With reference to figure 1 and Fig. 2, show the solid and the generalized section of polycrystalline sheet module encapsulation construction commonly used respectively.Polycrystalline sheet module encapsulation construction 10 commonly used comprises: one first substrate 11, one first encapsulating structure 12, one second encapsulating structure 13 and a plurality of first soldered ball 14.
This first substrate 11 has a upper surface 111 and a lower surface 112.
This first encapsulating structure 12 comprises one first wafer 121, a plurality of first leads 122 and one first sealing 123.This first wafer 121 is attached to the upper surface 111 of this first substrate 11, and utilizes these first leads 122 to be electrically connected with this first substrate 11.This first sealing 123 coats these first substrate, 11 upper surfaces 111 of this first wafer 121, these first leads 122 and part.
This second encapsulating structure 13 comprises one second substrate 131, one second wafer 132, a plurality of second leads 133, one second sealing 134 and a plurality of second soldered ball 135.This second substrate 131 has a upper surface 1311 and a lower surface 1312.This second wafer 132 is attached to the upper surface 1311 of this second substrate 131, and utilizes these second leads 133 to be electrically connected with this second substrate 131.This second sealing 134 coats this second wafer 132, these second leads 133 and this second substrate 131 upper surfaces 1311.These second soldered balls 135 are formed on the lower surface 1312 of this second substrate 131.This second encapsulating structure 13 be in itself the encapsulation finish after, utilize these second soldered balls 135 to be incorporated on the upper surface 111 of this first substrate 11 in the mode of mounted on surface (surface mounting).
First soldered ball 14 is formed at the lower surface 112 of this first substrate 11.
In this polycrystalline sheet module encapsulation construction 10 commonly used, this first wafer 121 is a little processing wafer, this second wafer 132 is an internal memory wafer, because the size of this different internal memory wafers is all different, and the number of I/O pin is also different, when therefore different internal memory wafers is made signal integration with different little processing wafers, need its signaling path of redesign, cause cost to increase and the research and development time lengthening.In addition, in this polycrystalline sheet module encapsulation construction 10 commonly used, this first encapsulating structure 12 and this second encapsulating structure 13 are to be arranged in parallel, and shared area is bigger.
Therefore, be necessary to provide the packaging structure of multiple wafers of an innovation and rich progressive, to address the above problem.
Summary of the invention
Main purpose of the present invention provides a kind of encapsulating structure that contains one encapsulating structure, and it produces with stack manner, the bigger problem of area occupied when being arranged in parallel to reduce a plurality of encapsulating structures.
Another object of the present invention provides a kind of encapsulating structure that contains one encapsulating structure, has at least two wafers in this encapsulating structure, does not need to redesign the signaling path between these wafers again.
Another purpose of the present invention provides a kind of packaging structure of multiple wafers, and it comprises: one first substrate, one first wafer, encapsulating structure and one first sealing.
This first substrate has a upper surface and a lower surface.This first die attach is in the upper surface of this first substrate, and is electrically connected with this first substrate.
This time encapsulating structure has a upper surface and a lower surface, and the lower surface of this time encapsulating structure is attached on this first wafer, and this time encapsulating structure comprises: one second substrate, one second wafer and one second sealing.This second substrate has a upper surface and a lower surface, and is electrically connected with this first wafer.This second die attach is in the upper surface of this second substrate, and is electrically connected with this second substrate.This second wafer of this second sealant covers and this second upper surface of base plate of part.
This first wafer of this first sealant covers, this time encapsulating structure and this first upper surface of base plate.
Description of drawings
Fig. 1 shows the schematic perspective view of polycrystalline sheet module encapsulation construction commonly used;
Fig. 2 shows the generalized section of polycrystalline sheet module encapsulation construction commonly used;
Fig. 3 shows the generalized section of first embodiment of the invention;
Fig. 4 shows the generalized section of second embodiment of the invention;
Fig. 5 shows the generalized section of third embodiment of the invention; And
Fig. 6 shows the generalized section of fourth embodiment of the invention.
Embodiment
With reference to figure 3, show the generalized section of first embodiment of the invention.The packaging structure of multiple wafers 20 of present embodiment, it comprises: one first substrate 21, one first wafer 22, a plurality of first lead 23, encapsulating structure 24, a plurality of privates 25, one first sealing 26 and an a plurality of soldered ball 27.
This first substrate 21 has a upper surface 211 and a lower surface 212.This first wafer 22 is attached to the upper surface 211 of this first substrate 21, and utilizes these first leads 23 to be electrically connected with this first substrate 21.Be understandable that, then not have the setting of these first leads 23 if this first wafer 22 is to be attached to this first substrate 21 in flip chip mode (flip-chip).
This time encapsulating structure 24 has a upper surface 241 and a lower surface 242, on this first wafer 22, this time encapsulating structure 24 comprises the lower surface 242 of this time encapsulating structure 24 with an adhesive bond: one second substrate 243, one second wafer 244, a plurality of second lead 245 and one second sealing 246.
This second substrate 243 has a upper surface 2431 and a lower surface 2432, and utilizes these privates 25 to be electrically connected with this first wafer 22, and perhaps these privates 25 are electrically connected with this first substrate 21.This second wafer 244 is attached to the upper surface 2431 of this second substrate 243, and utilizes these second leads 245 to be electrically connected with this second substrate 243.This second sealing 246 coats these second substrate, 243 upper surfaces 2431 of this second wafer 244 and part.It should be noted that, this second sealing 246 does not cover this second substrate, 243 upper surfaces 2431 fully, and the part that these second substrate, 243 upper surfaces 2431 are not covered by this second sealing 246 is provided with a plurality of weld pads (not shown), for the usefulness of these privates 25 connections.
This time encapsulating structure 24 is a kind of being selected from by Land Grid Array (Land Grid Array, LGA), square flat non-pin formula (Quad Flat Non-leaded, QFN), double little outward appearance do not have pinned (Small Outline Non-leaded, SON) and the group that forms of upside-down mounting film encapsulating structures such as (Chip On Film).In the present embodiment, this time encapsulating structure 24 is the Land Grid Array encapsulating structure, its lower surface 2432 has the usefulness of a plurality of bond pads (landing pad) for test, and this time encapsulating structure 24 is by adhering on this first wafer 22, to cut the waste after the test again.
This first sealing 26 coats this first wafer 22, this time encapsulating structure 24, these first leads 23, these privates 25 and this first upper surface of base plate 211.These soldered balls 27 are formed at the lower surface 212 of this first substrate 21, use for this first wafer 22 to be electrically connected with external device whereby.
This first wafer 22 and second wafer 244 can be optical crystal chip, logic wafer, little processing wafer or internal memory wafer.In the present embodiment, this first wafer 22 is a little processing wafer, and this second wafer 244 is an internal memory wafer.
With reference to figure 4, show the generalized section of second embodiment of the invention.The present embodiment and first embodiment are roughly the same, do not exist together and only add a fin 28 for present embodiment, it comprises a heat sink body 281 and a support portion 282, this support portion 282 is outwards to be extended downwards by this heat sink body 281, in order to support this heat sink body 281 and to form an accommodation space with ccontaining this time encapsulating structure.The upper surface of this heat sink body 281 is exposed in the air, to increase radiating efficiency.
With reference to figure 5, show the generalized section of third embodiment of the invention.The present embodiment and first embodiment are roughly the same, do not exist together only in the present embodiment, this first wafer 22 is exchanged with the position of this time encapsulating structure 24, promptly this first wafer 22 is the upper surfaces 241 that are stacked at this time encapsulating structure 24, and the lower surface 242 of this time encapsulating structure 24 adheres to the upper surface 211 of this first substrate 21.In addition, in the present embodiment, these privates 25 are electrically connected the upper surface 211 of these second substrate, 243 upper surfaces 2431 and this first substrate 21.In addition, these privates 25 can electrically connect this first wafer 22 and this first substrate 21, and perhaps these privates 25 can electrically connect this first wafer 22 and this second substrate 243.
With reference to figure 6, show the generalized section of fourth embodiment of the invention.Present embodiment is to add a wafer in first embodiment.The packaging structure of multiple wafers 30 of present embodiment, it comprises: one first substrate 31, one first wafer 32, a plurality of first lead 33, encapsulating structure 34, a plurality of privates 35, one first sealing 36, a plurality of soldered ball 37, one the 3rd wafer 38 and a plurality of privates 39.
This first substrate 31 has a upper surface 311 and a lower surface 312.This first wafer 32 is attached to the upper surface 311 of this first substrate 31, and utilizes these first leads 33 to be electrically connected with this first substrate 31.Be understandable that, then not have the setting of these first leads 33 if this first wafer 32 is to be attached to this first substrate 31 in flip chip mode (flip-chip).
This time encapsulating structure 34 has a upper surface 341 and a lower surface 342, the lower surface 342 of this time encapsulating structure 34 be with an adhesive bond on this first wafer 32, this time encapsulating structure 34 comprises: one second substrate 343, one second wafer 344, a plurality of second lead 345 and one second sealing 346.
This second substrate 343 has a upper surface 3431 and a lower surface 3432, and utilizes these privates 35 to be electrically connected with this first wafer 32.This second wafer 344 is attached to the upper surface 3431 of this second substrate 343, and utilizes these second leads 345 to be electrically connected with this second substrate 343.This second sealing 346 coats these second substrate, 343 upper surfaces 3431 of this second wafer 344 and part.It should be noted that, this second sealing 346 does not cover this second substrate, 343 upper surfaces 3431 fully, and the part that these second substrate, 343 upper surfaces 3431 are not covered by this second sealing 346 is provided with a plurality of weld pads (not shown), for the usefulness of these privates 35 connections.
This time encapsulating structure 34 is that a kind of being selected from by Land Grid Array, square flat non-pin formula, double little outward appearance do not have the group that encapsulating structures such as pinned and upside-down mounting film are formed.In the present embodiment, this time encapsulating structure 34 is the Land Grid Array encapsulating structure, its lower surface 3432 has the usefulness of a plurality of bond pads (landing pad) for test, and this time encapsulating structure 34 is by adhering on this first wafer 32, to cut the waste after the test again.
The 3rd wafer 38 is attached to the upper surface 341 of this time encapsulating structure 34, and utilizes these privates 39 to be electrically connected with this first substrate 31.
This first sealing 36 coats this first wafer 32, this time encapsulating structure 34, these first leads 33, these privates 35, the 3rd wafer 38, these privates 39 and this first upper surface of base plate 311.These soldered balls 37 are formed at the lower surface 312 of this first substrate 31.
This first wafer 32, second wafer 344 and the 3rd wafer 38 can be optical crystal chip, logic wafer, little processing wafer or internal memory wafer.In the present embodiment, this first wafer 32 is a little processing wafer, and this second wafer 344 is an internal memory wafer, and the 3rd wafer 38 is another little processing wafer.
The foregoing description only is explanation principle of the present invention and effect thereof, and unrestricted the present invention, so the those skilled in the art makes amendment to the foregoing description and changes and still do not take off spirit of the present invention.Interest field of the present invention should be as listed in the above-mentioned claim.
Claims (22)
1. packaging structure of multiple wafers, it comprises:
One first substrate, it has a upper surface and a lower surface;
One first wafer, it is attached to the upper surface of this first substrate;
A plurality of first leads are in order to be electrically connected this first substrate and this first wafer;
An encapsulating structure, it has a upper surface and a lower surface, and the lower surface of this time encapsulating structure is attached on this first wafer, and this time encapsulating structure comprises:
One second substrate, it has a upper surface and a lower surface, and one of them is electrically connected with this first wafer and this first substrate;
One second wafer, it is attached to the upper surface of this second substrate, and is electrically connected with this second substrate; And
One second sealing, it coats this second upper surface of base plate of this second wafer and part; And
One first sealing, it coats this first wafer, this time encapsulating structure and this first upper surface of base plate.
2. structure according to claim 1, wherein this time encapsulating structure more comprises a plurality of second leads, in order to be electrically connected this second substrate and this second wafer.
3. structure according to claim 1, it more comprises a plurality of privates, in order to be electrically connected this second substrate and this first wafer.
4. structure according to claim 1, it more comprises a plurality of privates, in order to be electrically connected this first substrate and this second substrate.
5. structure according to claim 1, it more comprises one the 3rd wafer, is attached to the upper surface of this time encapsulating structure, and is electrically connected with this first substrate.
6. structure according to claim 5, it more comprises a plurality of privates, in order to be electrically connected the 3rd wafer and this first substrate.
7. structure according to claim 5, it more comprises a fin, this fin comprises a heat sink body and a support portion, and this support portion is outwards to be extended downwards by this heat sink body, in order to support this heat sink body and to form an accommodation space with ccontaining this time encapsulating structure.
8. structure according to claim 1, it more comprises a fin, this fin comprises a heat sink body and a support portion, and this support portion is outwards to be extended downwards by this heat sink body, in order to support this heat sink body and to form an accommodation space with ccontaining this time encapsulating structure.
9. structure according to claim 1, it more comprises a plurality of soldered balls, is the lower surface that is formed at this first substrate, is electrically connected with external device whereby for this first wafer.
10. structure according to claim 1, wherein this time encapsulating structure is that a kind of being selected from by Land Grid Array, square flat non-pin formula, double little outward appearance do not have the group that encapsulating structures such as pinned and upside-down mounting film are formed.
11. structure according to claim 1, wherein this first wafer is a kind of group that is made up of optical crystal chip, logic wafer, little processing wafer and internal memory wafer that is selected from.
12. structure according to claim 1, wherein this second wafer is a kind of group that is made up of optical crystal chip, logic wafer, little processing wafer and internal memory wafer that is selected from.
13. a packaging structure of multiple wafers, it comprises:
One first substrate, it has a upper surface and a lower surface;
An encapsulating structure, it has a upper surface and a lower surface, and the lower surface of this time encapsulating structure is attached on this first substrate, and this time encapsulating structure comprises:
One second substrate, it has a upper surface and a lower surface, and is electrically connected with this first substrate;
One second wafer, it is attached to the upper surface of this second substrate, and is electrically connected with this second substrate; And
One second sealing, it coats this second upper surface of base plate of this second wafer and part;
One first wafer, it is attached to the upper surface of this time encapsulating structure, and one of them is electrically connected with this first substrate and second substrate; And
One first sealing, it coats this first wafer, this time encapsulating structure and this first upper surface of base plate.
14. structure according to claim 13, it more comprises a plurality of first leads, in order to be electrically connected this first substrate and this first wafer.
15. structure according to claim 13, wherein this time encapsulating structure more comprises a plurality of second leads, in order to be electrically connected this second substrate and this second wafer.
16. structure according to claim 13, it more comprises a plurality of privates, in order to be electrically connected this second substrate and this first wafer.
17. structure according to claim 13, it more comprises a plurality of privates, in order to be electrically connected this first substrate and this second substrate.
18. structure according to claim 13, it more comprises a fin, this fin comprises a heat sink body and a support portion, and this support portion is outwards to be extended downwards by this heat sink body, in order to support this heat sink body and to form an accommodation space with ccontaining this time encapsulating structure.
19. structure according to claim 13, it more comprises a plurality of soldered balls, is formed at the lower surface of this first substrate.
20. structure according to claim 13, wherein this time encapsulating structure is that a kind of being selected from by Land Grid Array, square flat non-pin formula, double little outward appearance do not have the group that encapsulating structures such as pinned and upside-down mounting film are formed.
21. structure according to claim 13, wherein this first wafer is a kind of group that is made up of optical crystal chip, logic wafer, little processing wafer and internal memory wafer that is selected from.
22. structure according to claim 13, wherein this second wafer is a kind of group that is made up of optical crystal chip, logic wafer, little processing wafer and internal memory wafer that is selected from.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100888870A CN100373614C (en) | 2004-11-08 | 2004-11-08 | Packing structure of multichip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100888870A CN100373614C (en) | 2004-11-08 | 2004-11-08 | Packing structure of multichip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1773700A CN1773700A (en) | 2006-05-17 |
| CN100373614C true CN100373614C (en) | 2008-03-05 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100888870A Active CN100373614C (en) | 2004-11-08 | 2004-11-08 | Packing structure of multichip |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102263077A (en) * | 2011-06-13 | 2011-11-30 | 西安天胜电子有限公司 | Double flat carrier-free pin-free IC chip packaging part |
| US9379034B1 (en) * | 2014-12-30 | 2016-06-28 | Stmicroelectronics Pte Ltd | Method of making an electronic device including two-step encapsulation and related devices |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040063242A1 (en) * | 2002-09-17 | 2004-04-01 | Chippac, Inc. | Semiconductor multi-package module having package stacked over ball grid array package and having wire bond interconnect between stacked packages |
| CN1531090A (en) * | 2003-03-18 | 2004-09-22 | ������������ʽ���� | Semiconductor device, electronic apparatus and their manufacturing methods, electronic equipment |
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2004
- 2004-11-08 CN CNB2004100888870A patent/CN100373614C/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040063242A1 (en) * | 2002-09-17 | 2004-04-01 | Chippac, Inc. | Semiconductor multi-package module having package stacked over ball grid array package and having wire bond interconnect between stacked packages |
| CN1531090A (en) * | 2003-03-18 | 2004-09-22 | ������������ʽ���� | Semiconductor device, electronic apparatus and their manufacturing methods, electronic equipment |
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| Publication number | Publication date |
|---|---|
| CN1773700A (en) | 2006-05-17 |
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