CN111755409A - Semiconductor package substrate and manufacturing method thereof, and electronic package and manufacturing method thereof - Google Patents

Semiconductor package substrate and manufacturing method thereof, and electronic package and manufacturing method thereof Download PDF

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Publication number
CN111755409A
CN111755409A CN201910237275.XA CN201910237275A CN111755409A CN 111755409 A CN111755409 A CN 111755409A CN 201910237275 A CN201910237275 A CN 201910237275A CN 111755409 A CN111755409 A CN 111755409A
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China
Prior art keywords
solder
layer
circuit
package substrate
semiconductor package
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Pending
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CN201910237275.XA
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Chinese (zh)
Inventor
周保宏
余俊贤
许诗滨
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Phoenix Pioneer Technology Co Ltd
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Phoenix Pioneer Technology Co Ltd
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Priority to CN201910237275.XA priority Critical patent/CN111755409A/en
Publication of CN111755409A publication Critical patent/CN111755409A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)

Abstract

A method for preparing semiconductor package substrate includes forming solder-proof structure with open hole on circuit structure to expose circuit structure to open hole for forming cup-shaped soldering seat on exposed circuit layer and hole wall of open hole.

Description

Semiconductor package substrate and manufacturing method thereof, and electronic package and manufacturing method thereof
Technical Field
The present invention relates to a package substrate, and more particularly, to a semiconductor package substrate and an electronic package thereof capable of improving reliability of a product.
Background
With the development of industrial applications, in recent years, development is gradually carried out toward the trend of packaging specifications of large-sized chips such as Artificial Intelligence (AI) chips, advanced chips or stacked chips, such as 3D or 2.5D IC processes, so as to be applied to high-density lines/high transmission speed/high layer number of stacked layers/large-sized designed advanced products such as Artificial Intelligence (AI) chips, GPUs, and the like.
Therefore, flip chip packaging substrates with large-sized boards, such as 40 × 40, 70 × 70 or other thicker and large-structured boards, are used instead to carry large-sized chips, such as Artificial Intelligence (AI) chips, advanced chips or stacked chips.
As shown in fig. 1A, the electronic apparatus 1 includes: a circuit board 18, a package substrate 1a disposed on the circuit board 18, and a semiconductor chip 19 bonded to the package substrate 1 a. Specifically, as shown in fig. 1B, the package substrate 1a includes a core layer 10, a circuit build-up portion 11 disposed on the core layer 10, and solder masks 12a and 12B disposed on the circuit build-up portion 11, wherein the solder masks 12a and 12B are exposed out of the outermost circuit layer of the circuit build-up portion 11 to serve as contacts (I/O) 11a and 11B, so as to mount a semiconductor chip 19 on the upper side (the die-mounting side shown in fig. 1C) via a solder bump 13a and mount a circuit board 18 on the lower side (the ball-mounting side or BGA shown in fig. 1D) via a solder ball 13B, thereby forming an electronic package product.
In the manufacture of the core layer 10, a substrate made of glass fiber and epoxy resin, such as bt (bimoleimide) and FR4 or FR5, is used, and a via hole process, such as mechanical drilling, laser drilling or a hole forming step of a biconical blind hole, is performed thereon, and then a conductive material and a filling resin (plug) are formed by electroplating in the hole. In addition, the build-up method of the wiring build-up portion 11 uses ABF type material as the dielectric layer, and the material of the solder masks 12a and 12b is selected from green paint, ink, and the like.
However, since the metal contact surface between the solder ball 13b and the contact 11b is only a single surface (e.g., the top surface of the contact 11 b), the metal contact area is very small, so that the solder ball 13b is prone to be broken at the contact 11b, even if the solder ball is broken or dropped due to poor bonding force (e.g., the top surface of the solder ball 13 ").
In addition, as shown in fig. 1A, in the conventional electronic device 1, when the package substrate 1A is applied to a large size during the packaging process, the rigidity of the package substrate 1A is insufficient, so that warpage (warp) may occur due to the inconsistent Coefficient of Thermal Expansion (CTE) of the materials between the layers of the package substrate 1A during the packaging high temperature process, which may cause poor connection between the package substrate 1A and the semiconductor chip 19 (e.g. the solder material 13' is not bonded), or poor connection between the package substrate 1A and the circuit board 18 during soldering (e.g. the solder ball 13 is not bonded), and even worse, the electrical failure or fracture of the semiconductor chip 19 itself may be caused by the stress relationship.
On the other hand, if the thickness of the core layer 10 is increased to increase the rigidity of the package substrate 1a and reduce the warpage of the package substrate 1a, other disadvantages may occur, such as the need for a thinner or miniaturized package design due to the increased thickness of the core layer 10. Specifically, in order to prevent the package substrate 1a from warping and further increase the thickness of the core layer 10, the entire package substrate 1a becomes thicker, which is not favorable for substrate manufacturing and increases the processing cost.
Therefore, how to overcome the above problems of the prior art has become a problem to be overcome in the industry.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present invention provides a semiconductor package substrate and a method for fabricating the same, and an electronic package and a method for fabricating the same, which can effectively avoid the solder balls from breaking or falling off.
The semiconductor packaging substrate comprises a circuit structure, a solder mask structure and a solder seat. The circuit structure is provided with a circuit layer; the welding-proof structure is arranged on the circuit structure and is provided with an opening so that the circuit layer is partially exposed out of the opening; the soldering base is in a cup-shaped structure, is formed by electroplating and extends from the exposed surface of the circuit layer to the hole wall of the opening, and is made of the same material as the circuit layer, such as copper.
The invention also provides a method for manufacturing the semiconductor packaging substrate, which comprises the following steps: providing a circuit structure with a circuit layer; forming a solder mask structure on the circuit structure, wherein an opening is formed in the solder mask structure so that part of the circuit layer is exposed out of the opening; and forming a solder seat on the exposed circuit layer and the hole wall of the opening.
In the semiconductor package substrate and the method for fabricating the same, the solder mask structure is a single insulating layer.
In the foregoing manufacturing method, the solder socket is formed in a cup-shaped structure, and is formed by electroplating on the exposed surface of the circuit layer and extends to the hole wall of the opening, and the material of the solder socket is the same as that of the circuit layer, such as copper.
In the semiconductor package substrate and the method for manufacturing the same, the solder mask structure further includes a metal supporting layer and an insulating layer covering the metal supporting layer, and the metal supporting layer is combined with the circuit structure by a bonding material.
The semiconductor package substrate and the method for manufacturing the same further include a conductive element disposed on the solder pad.
The semiconductor package substrate and the method for manufacturing the same further include a solder ball disposed on the solder mount, wherein the solder ball has a volume smaller than that of the opening.
In the semiconductor package substrate and the method for fabricating the same, the contact portion of the solder pad and the circuit layer is formed with a bump bottom having a suitable thickness.
The invention also provides an electronic package which comprises the semiconductor package substrate and an electronic element. The circuit structure is provided with a first side and a second side which are opposite, the circuit layer is arranged on the first side and the second side, and the welding-proof structure is arranged on the second side of the circuit structure; and the electronic element is arranged on the first side of the circuit structure and is electrically connected with the circuit layer on the first side of the circuit structure.
The invention also provides a method for manufacturing the electronic packaging piece, which comprises the following steps: providing the semiconductor package substrate, wherein the circuit structure has a first side and a second side opposite to each other, the circuit layer is disposed on the first side and the second side, and the solder mask structure is disposed on the second side of the circuit structure; and arranging an electronic element on the first side of the circuit structure, wherein the electronic element is electrically connected with the circuit layer on the first side of the circuit structure.
The electronic package and the method for manufacturing the same further include a packaging layer disposed on the semiconductor package substrate to combine the electronic component and the semiconductor package substrate.
In the electronic package and the method for manufacturing the same, the electronic component is disposed on the first side of the circuit structure by a plurality of conductive bumps.
In view of the above, the semiconductor package substrate and the fabrication method thereof, and the electronic package and the fabrication method thereof of the present invention, mainly form the solder seat on the exposed circuit layer and the hole wall of the opening of the solder mask structure to increase the metal contact area of the conductive element, thereby improving the bonding force between the conductive element (solder ball) and the solder seat.
Drawings
Fig. 1A is a schematic cross-sectional view of a conventional electronic device.
Fig. 1B is a schematic cross-sectional view of a conventional flip-chip package substrate.
Fig. 1C is a schematic top view of fig. 1B.
FIG. 1D is a schematic bottom view of FIG. 1B.
Fig. 2A to 2B are schematic cross-sectional views illustrating a method for manufacturing a semiconductor package substrate according to a first embodiment of the invention.
Fig. 2C is a schematic cross-sectional view of the electronic package according to the first embodiment of the invention.
Fig. 3A to 3C are schematic cross-sectional views illustrating a method for manufacturing a semiconductor package substrate according to a second embodiment of the invention.
Fig. 3A' is another embodiment of fig. 3A.
FIGS. 3C' and 3C "illustrate other embodiments of FIG. 3C.
Fig. 3D is a schematic cross-sectional view of a second embodiment of the electronic package of the present invention.
Fig. 3D' is another embodiment of fig. 3D.
The reference numbers are as follows:
1 electronic device
1a packaging substrate
10 core layer
11 line build-up part
11a,11b contact
12a,12b solder mask
13a solder bump
13b, 13' solder ball
13' solder material
18 circuit board
19 semiconductor chip
2,3 semiconductor package substrate
2a circuit structure
20 core layer
20a first side
20b second side
200 conductive part
21 build-up part
210 dielectric layer
211 line layer
212 pad
22a,22b,32a,32b solder mask structure
220 open pore
23,36, 36' welding seat
32 insulating layer
320 second opening hole
33 metallic support layer
330 first opening hole
34 bonding material
361' bottom of bump
37 guide connecting block
4, 4' electronic package
40 electronic component
400 conductive bump
41 encapsulation layer
42 conductive elements.
Detailed Description
Other advantages and technical effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein, by describing the embodiments of the present invention with specific examples.
It should be understood that the structures, proportions, sizes, and other elements shown in the drawings and described in the specification are illustrative only and are not intended to limit the scope of the invention, which is defined by the claims, since the same are understood and read by those skilled in the art, it is not necessary to limit the scope of the invention to the exact construction and operation, and any structural modifications, changes in proportions, or adjustments in size, can be made without affecting the technical effects and objectives of the invention. In addition, the terms "above", "first", "second" and "a" as used herein are for the sake of clarity only, and are not intended to limit the scope of the present invention, and changes or modifications of the relative relationship between them are considered to be within the scope of the present invention without substantial technical changes.
Fig. 2A to 2B are schematic cross-sectional views illustrating a method for manufacturing a semiconductor package substrate 2 according to a first embodiment of the invention.
As shown in fig. 2A, a circuit structure 2A is provided, the circuit structure 2A has a first side 20a and a second side 20b opposite to each other, both sides can be used for placing electronic components (such as semiconductor chips, passive components, etc.), and the external side where the semiconductor chips are placed is referred to as a die side, so for convenience of the following description, the first side 20a is referred to as the die side.
In the present embodiment, the circuit structure 2a has a core layer 20 in which a plurality of conductive portions 200 are formed. For example, the core layer 20 may be formed by using a base material containing glass fibers and organic resin, such as BT (bismuth triazine), FR4 or FR5, or by using a filler (such as SiO) with high rigidity and no glass fibers2) The organic substrate is then subjected to a via process, such as mechanical drilling or laser drilling, to form a hole, and a conductive material is formed in the hole. Alternatively, in another embodiment, the core layer 20 is formed of an organic insulating material, which may be ABF (ajinomoto build-up Film), a Prepreg with or without glass fibers (Prepreg), a mold compound (Moldi)ng Compound), such as a core substrate formed of Epoxy Molding Compound (EMC), preferably, EMC with high rigidity and low Coefficient of Thermal Expansion (CTE) is used, in which case the conductive part 200 may be composed of a single conductive pillar or a plurality of conductive pillars stacked in contact with each other.
In addition, the circuit structure 2a further includes a build-up portion 21 disposed on the core layer 20, which has at least one dielectric layer 210 and a plurality of circuit layers 211 combined with the dielectric layer 210. For example, the dielectric layer 210 may be formed of liquid epoxy, film-shaped ABF, prepreg, molding resin (EMC), or photosensitive resin. It should be understood that the number of layers of the circuit layer 211 can be designed according to the requirement.
In addition, an insulating layer having a plurality of openings 220 may be formed on the build-up portion 21 of the circuit structure 2a to serve as the solder mask structure 22a and the solder mask structure 22b, and the outermost circuit layer 211 of the circuit structure 2a is exposed to the plurality of openings 220 to serve as the bonding pads 212. Specifically, the solder mask structure 22a and the solder mask structure 22b may be made of graphene, ink, green paint, ABF, or a non-photosensitive dielectric material (such as EMC) or other suitable materials, but are not particularly limited.
In other embodiments, the core layer 20 may be replaced by a silicon substrate, so that the build-up portion 21 is disposed on the silicon substrate, and the circuit structure 2a is in the form of a silicon interposer (silicon interposer). Alternatively, in other embodiments, the line structure 2a may be in the form of a coreless layer (core).
As shown in fig. 2B, the solder pads 23 are formed on the second side 20B of the circuit structure 2a and on the walls of the openings 220 of the solder mask structure 22B.
In the present embodiment, the material of the solder seat 23 is the same as the material of the solder pad 212, such as copper. For example, the solder pads 212 are formed on the exposed surface of the circuit layer 211 by electroplating and extend to the walls of the openings 220.
In addition, when the semiconductor package substrate 2 is applied subsequently, as shown in fig. 2C, in the electronic package 4, at least one electronic component 40 is disposed on the exposed bonding pad 212 of the first side 20a of the circuit structure 2a, a package layer 41 is formed on the first side 20a of the circuit structure 2a to bond the electronic component 40, and a conductive element 42 such as a solder ball is disposed on the pad 23 of the second side 20b of the circuit structure 2a to bond to a circuit board (not shown).
The electronic component 40 is an active component, such as a semiconductor chip, a passive component, such as a resistor, a capacitor, or an inductor, or a combination thereof. For example, the electronic component 40 is a semiconductor chip electrically connected to the pads 212 by flip-chip bonding via a plurality of conductive bumps 400 containing solder. Alternatively, the electronic device 40 can be electrically connected to the bonding pad 212 by wire bonding via a plurality of bonding wires (not shown). However, the way of electrically connecting the electronic component to the semiconductor package substrate 2 is not limited to the above, and the electronic component may be disposed on the second side 20b of the circuit structure 2a or embedded in the enlarged portion 21.
The package layer 41 may be an underfill, which is formed between the first side 20a of the circuit structure 2a and the electronic component 40 to encapsulate the plurality of conductive bumps 400. Alternatively, the package layer 41 may be a film for a lamination process, a molding compound for a molding process, or a printing compound for a printing process, etc. to cover the electronic component 40 and the conductive bumps 400, and the material forming the package layer 41 is Polyimide (PI), epoxy (epoxy) or a molding compound. It should be understood that the packaging method of the electronic component 40 is not limited to the above.
The conductive elements 42 are formed on a plurality of solder pads 23.
In the present embodiment, the conductive elements 42 comprise a solder material, such as solder balls.
Therefore, in the manufacturing method of the semiconductor package substrate 2 of the present embodiment, the copper material (i.e. the solder seat 23) with the same material as the circuit layer 211 and the solder pad 212 is plated on the hole walls of the opening 220 of the solder-ball-mounting side (the second side 20b of the circuit structure 2 a) and the solder-preventing structure 22b, so that in the subsequent ball-mounting packaging operation, the conductive element 42 (solder ball) contacts the bottom surface and the sidewall of the solder seat 23, thereby increasing the metal contact area between the conductive element 42 and the solder seat 23, and further improving the bonding force between the conductive element 42 (solder ball) and the solder seat 23, so compared with the prior art, the conductive element 42 of the present invention is not broken at the bonding position between the conductive element and the solder seat 23, and can avoid the occurrence of ball dropping or falling off.
Fig. 3A to 3C are schematic cross-sectional views illustrating a manufacturing method of a semiconductor package substrate 3 according to a second embodiment of the invention. The difference between this embodiment and the first embodiment is the solder mask structure, and the other structures are substantially the same, so only the differences will be described below.
As shown in fig. 3A, a metal supporting layer 33 is bonded on the second side 20b of the circuit structure 2a by a bonding material 34, a plurality of first openings 330 are formed on the metal supporting layer 33, and the plurality of first openings 330 extend through the bonding material 34, so that the plurality of bonding pads 212 are exposed to the plurality of first openings 330. Next, an insulating layer 32 is formed on the pad 212, the metal supporting layer 33 and the first opening 330.
In the present embodiment, the metal supporting layer 33 is a steel plate, a nickel alloy (alloy 42) sheet, etc., and the bonding material 34 is an adhesive material, and the material for forming the insulating layer 32 can be graphene, ink, green paint, ABF, or a non-photosensitive dielectric material (such as EMC) or other suitable materials, but is not limited thereto.
In addition, the insulating layer 32 is disposed along the sidewalls of the first opening 330. Alternatively, the insulating layer 32 can fill the first opening 330, as shown in FIG. 3A'.
In addition, the insulating layer 32 is also formed on the first side 20a of the line structure 2 a.
As shown in fig. 3B, a plurality of second openings 320 are formed in the insulating layer 32 on the second side 20B of the circuit structure 2a, so that a plurality of bonding pads 212 are exposed out of the plurality of second openings 320, the insulating layer 32 and the metal supporting layer 33 are used as solder mask structures 32a, and the insulating layer 32 covers the metal supporting layer 33.
As shown in fig. 3C, the solder pads 36 are formed on the second side 20b of the circuit structure 2a and the walls of the second openings 320 of the solder mask structure 32b, so as to increase the bonding contact area between the solder pads and the conductive elements 42, thereby effectively improving the bonding force therebetween.
In other embodiments, a conductive block 37 may be formed on the cup-shaped soldering base 36 according to requirements, and the material of the conductive block 37 is, for example, tin or other metal materials. Specifically, as shown in fig. 3C', a solder ball having a volume smaller than that of the second opening 320 is attached to the cup-shaped solder seat 36 to form a conductive bump 37, so that the size of the conductive element 42 to be attached later can be effectively reduced (see fig. 3D later), thereby meeting the requirement of fine pitch package.
In other embodiments, a bump bottom 361 '(please refer to fig. 3C ″) with a suitable thickness (e.g., 1/2 depth of the second opening 320) may be formed on the pad 212 in the second opening 320 by electroplating, and then the bump bottom 361' is continuously electroplated on the remaining hole wall of the second opening 320 by electroplating, so as to form a cup-shaped solder seat 36 '(made of the same material as the circuit layer 211 and the pad 212, such as copper) with the bump bottom 361', thereby effectively reducing the size of the subsequently connected conductive element 42 (please refer to fig. 3D '), so as to satisfy the requirement of fine pitch package and further optimize the electrical quality (by replacing a portion of the tin material conductive element 42 with the copper bump bottom 361' with good electrical quality).
In addition, in the subsequent application, if the semiconductor package substrate 3 shown in fig. 3C and 3C 'is used, the electronic package 4' shown in fig. 3D is formed. Specifically, the electronic component 40 is disposed on the exposed pad 212 of the first side 20a of the circuit structure 2a, the packaging layer 41 is formed on the first side 20a to combine with the electronic component 40, and the plurality of conductive elements 42 are mounted on the pad 36 with the conductive bump 37 on the second side 20b of the semiconductor package substrate 3.
On the other hand, when the semiconductor package substrate 3 shown in fig. 3C ″ is used, the electronic package 4 ″ shown in fig. 3D ' is formed, wherein the plurality of conductive elements 42 are mounted on the solder socket 36 ' having the bump bottom 361 '.
Therefore, the method for manufacturing the semiconductor package substrate 3 of the present embodiment is to plate a layer of copper material (i.e. forming the cup-shaped solder seat 36, the solder seat 36 ') on the wall of the pad 212 on the ball-mounting side (the second side 20b of the circuit structure 2 a) and the wall of the second opening 320 of the solder-preventing structure 32b, so as to make the conductive element 42 (solder ball) contact the solder seat 36, the bottom surface and the sidewall of the solder seat 36 ', thereby increasing the metal contact area and further improving the bonding force between the conductive element 42 (solder ball) and the solder seat 36, the solder seat 36 '. Compared with the prior art, the bonding force between the conductive element 42 and the solder socket 36 is stronger, so that the conductive element 42 is prevented from breaking at the bonding position with the solder socket 36 and the solder socket 36', and the ball falling or falling off can be avoided.
In addition, the metal supporting layer 33 is disposed on the second side 20b of the circuit structure 2a to increase the rigidity and strength of the semiconductor package substrate 3, so that compared with the prior art, when the semiconductor package substrate 3 is used in a large package size, even if the semiconductor package substrate 3 is thinned, the semiconductor package substrate 3 still has high rigidity, so that the electronic package 4 ', 4 ″ can be prevented from being warped during a subsequent high-temperature packaging process or product use, and the problem of poor connection between the electronic package 4' and the electronic element 40 or the circuit board can be avoided.
In addition, when the semiconductor package substrate 3 is used for a large package size, the number of layers of the build-up portion 21 of the circuit structure 2a can be designed as required, so that the circuit structure 2a can generate various warpage changes, and the rigidity of the semiconductor package substrate 3 can be controlled by adjusting the thickness of the metal supporting layer 33 or the material of the metal supporting layer 33. Therefore, the thickness of the core layer 20 does not need to be increased, and even the thickness of the core layer 20 can be reduced or the core layer 20 does not need to be configured, so that the problem of warpage of the semiconductor package substrate 3 can be avoided.
In addition, by designing the cup-shaped solder pad 36 ' with the bottom 361 ' of the bump (which is made of the same material as the circuit layer 211 and the solder pad 212, such as copper), the size and material of the conductive element 42 can be effectively reduced to meet the requirement of fine pitch package, and the electrical quality of the semiconductor package substrate 3 can be further optimized (by replacing a part of the conductive element 42 made of tin material with the bottom 361 ' of the copper material with good electrical quality).
In summary, the semiconductor package substrate and the electronic package packaged thereby according to the present invention utilize the design of the solder socket 23, the solder socket 36, and the solder socket 36 ' to increase the contact area between the conductive element 42 and the metal, so as to improve the bonding force between the conductive element 42 (solder ball) and the solder socket 23, the solder socket 36, and the solder socket 36 ', thereby effectively preventing the conductive element 42 from breaking at the bonding position between the conductive element 42 and the solder socket 23, the solder socket 36, and the solder socket 36 ', and preventing the ball from dropping or falling off.
The above embodiments are merely illustrative of the principles and technical effects of the present invention, and are not intended to limit the present invention. Those skilled in the art can modify the above-described embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.

Claims (18)

1. A semiconductor package substrate, comprising:
a line structure having a line layer;
the welding-proof structure is arranged on the circuit structure and is provided with an opening so that the circuit layer is partially exposed out of the opening; and
and the welding seat is of a cup-shaped structure, is formed by electroplating and extends to the hole wall of the opening from the exposed surface of the circuit layer, wherein the material for forming the welding seat is the same as the material for forming the circuit layer.
2. The semiconductor package substrate of claim 1, wherein the solder mask structure is a single insulating layer.
3. The semiconductor package substrate of claim 1, wherein the solder mask structure further comprises a metal support layer and an insulating layer covering the metal support layer, the metal support layer being bonded to the circuit structure with a bonding material.
4. The semiconductor package substrate of claim 1, further comprising a conductive element disposed on the solder pad, wherein the conductive element is a solder ball.
5. The semiconductor package substrate of claim 1, further comprising a solder bump disposed on the solder socket, wherein the solder bump is a solder ball having a volume smaller than the opening.
6. The substrate of claim 1, wherein the contact portion of the pad and the circuit layer is formed with a bottom bump having a suitable thickness, and the suitable thickness is not greater than or greater than the depth 1/2 of the opening.
7. An electronic package, comprising:
the semiconductor package substrate according to one of claims 1 to 6, wherein the circuit structure has a first side and a second side opposite to each other, and the circuit layer is disposed on the first side and the second side, such that the solder mask structure is disposed on the second side of the circuit structure; and
and the electronic element is arranged on the first side of the circuit structure and is electrically connected with the circuit layer on the first side of the circuit structure.
8. The electronic package according to claim 7, further comprising a packaging layer disposed on the semiconductor package substrate for bonding the electronic component and the semiconductor package substrate.
9. The electronic package of claim 7, wherein the electronic component is disposed on the first side of the circuit structure with a plurality of conductive bumps.
10. A method for manufacturing a semiconductor package substrate, the method comprising:
providing a circuit structure with a circuit layer;
forming a solder mask structure on the circuit structure, wherein the solder mask structure has an opening to expose the circuit layer out of the opening; and
and forming a welding seat in the opening, wherein the welding seat is of a cup-shaped structure, is formed by electroplating and extends to the hole wall of the opening from the exposed surface of the circuit layer, and the material for forming the welding seat is the same as the material for forming the circuit layer.
11. The method of claim 10, wherein the solder mask structure is a single insulating layer.
12. The method of claim 10, wherein the solder mask structure further comprises a metal supporting layer and an insulating layer covering the metal supporting layer, and the metal supporting layer is bonded to the circuit structure by a bonding material.
13. The method of claim 10, further comprising forming conductive elements on the solder pad, wherein the conductive elements are solder balls.
14. The method of claim 10, further comprising forming a solder bump on the pad, wherein the solder bump is a solder ball having a volume smaller than the opening.
15. The method of claim 10, wherein the contact portion of the solder pad and the circuit layer is electroplated with a bump bottom having a suitable thickness, and the suitable thickness is not greater than or greater than the 1/2 depth of the opening.
16. A method of fabricating an electronic package, the method comprising:
providing a semiconductor package substrate according to one of claims 1 to 6, wherein the circuit structure has a first side and a second side opposite to each other, and the circuit layer is disposed on the first side and the second side, and the solder mask structure is disposed on the second side of the circuit structure; and
an electronic element is arranged on the first side of the circuit structure and electrically connected with the circuit layer on the first side of the circuit structure.
17. The method of claim 16, further comprising forming an encapsulation layer on the semiconductor package substrate to bond the electronic component and the semiconductor package substrate.
18. The method of claim 16, wherein the electronic component is disposed on the first side of the circuit structure with a plurality of conductive bumps.
CN201910237275.XA 2019-03-27 2019-03-27 Semiconductor package substrate and manufacturing method thereof, and electronic package and manufacturing method thereof Pending CN111755409A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114630494A (en) * 2022-05-12 2022-06-14 之江实验室 Interconnection structure of wafer integrated system and top PCB and manufacturing method thereof
WO2023201598A1 (en) * 2022-04-20 2023-10-26 华为技术有限公司 Chip, preparation method therefor and electronic device

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002033355A (en) * 2000-07-14 2002-01-31 Mitsui Mining & Smelting Co Ltd Film carrier tape for mounting electronic component
TW200816428A (en) * 2006-09-19 2008-04-01 Phoenix Prec Technology Corp Surface structure of package substrate and method of manufacturing the same
US20080135279A1 (en) * 2006-12-11 2008-06-12 Nec Electronics Corporation Printed wiring board having plural solder resist layers and method for production thereof
CN101409273A (en) * 2007-10-08 2009-04-15 全懋精密科技股份有限公司 Ball-placing side surface structure for package substrate and manufacturing method thereof
JP2009081356A (en) * 2007-09-27 2009-04-16 Shinko Electric Ind Co Ltd Method of manufacturing wiring board and wiring board
WO2012169162A1 (en) * 2011-06-06 2012-12-13 住友ベークライト株式会社 Reinforcing member, semiconductor package, semiconductor device, and fabrication method for semiconductor package
WO2013065287A1 (en) * 2011-11-01 2013-05-10 住友ベークライト株式会社 Method for manufacturing semiconductor package
CN106981473A (en) * 2016-01-19 2017-07-25 矽品精密工业股份有限公司 Substrate structure and method for fabricating the same

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002033355A (en) * 2000-07-14 2002-01-31 Mitsui Mining & Smelting Co Ltd Film carrier tape for mounting electronic component
TW200816428A (en) * 2006-09-19 2008-04-01 Phoenix Prec Technology Corp Surface structure of package substrate and method of manufacturing the same
US20080135279A1 (en) * 2006-12-11 2008-06-12 Nec Electronics Corporation Printed wiring board having plural solder resist layers and method for production thereof
JP2009081356A (en) * 2007-09-27 2009-04-16 Shinko Electric Ind Co Ltd Method of manufacturing wiring board and wiring board
CN101409273A (en) * 2007-10-08 2009-04-15 全懋精密科技股份有限公司 Ball-placing side surface structure for package substrate and manufacturing method thereof
WO2012169162A1 (en) * 2011-06-06 2012-12-13 住友ベークライト株式会社 Reinforcing member, semiconductor package, semiconductor device, and fabrication method for semiconductor package
WO2013065287A1 (en) * 2011-11-01 2013-05-10 住友ベークライト株式会社 Method for manufacturing semiconductor package
TW201340270A (en) * 2011-11-01 2013-10-01 Sumitomo Bakelite Co Method of manufacturing semiconductor package
CN106981473A (en) * 2016-01-19 2017-07-25 矽品精密工业股份有限公司 Substrate structure and method for fabricating the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023201598A1 (en) * 2022-04-20 2023-10-26 华为技术有限公司 Chip, preparation method therefor and electronic device
CN114630494A (en) * 2022-05-12 2022-06-14 之江实验室 Interconnection structure of wafer integrated system and top PCB and manufacturing method thereof
CN114630494B (en) * 2022-05-12 2022-08-09 之江实验室 Interconnection structure of wafer integration system and top PCB and manufacturing method thereof

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Application publication date: 20201009