WO2013065287A1 - Method for manufacturing semiconductor package - Google Patents

Method for manufacturing semiconductor package Download PDF

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Publication number
WO2013065287A1
WO2013065287A1 PCT/JP2012/006936 JP2012006936W WO2013065287A1 WO 2013065287 A1 WO2013065287 A1 WO 2013065287A1 JP 2012006936 W JP2012006936 W JP 2012006936W WO 2013065287 A1 WO2013065287 A1 WO 2013065287A1
Authority
WO
WIPO (PCT)
Prior art keywords
reinforcing member
conductor pattern
semiconductor package
insulating layer
step
Prior art date
Application number
PCT/JP2012/006936
Other languages
French (fr)
Japanese (ja)
Inventor
岡田 亮一
賢也 橘
小野塚 偉師
猛 八月朔日
Original Assignee
住友ベークライト株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP2011-240433 priority Critical
Priority to JP2011240434 priority
Priority to JP2011240433 priority
Priority to JP2011-240434 priority
Application filed by 住友ベークライト株式会社 filed Critical 住友ベークライト株式会社
Publication of WO2013065287A1 publication Critical patent/WO2013065287A1/en

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