CN114630494B - Interconnection structure of wafer integration system and top PCB and manufacturing method thereof - Google Patents
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Abstract
本发明公开了晶圆集成系统与顶部PCB板的互连结构及其制造方法,包括金属结构件,所述金属结构件内设置有凹槽,所述凹槽内设置有晶圆集成系统,所述晶圆集成系统的下表面与所述凹槽的上表面还设置有导热材料,所述金属结构件的顶端连接有刚性板,所述刚性板上连接有PCB板,所述PCB板上连接有电源模块和I/O模块,所述刚性板中设置有电气连接装置,所述电气连接装置的下表面连接所述晶圆集成系统,所述电气连接装置的上表面连接所述PCB板。本发明解决晶圆集成系统与传统PCB集成系统互通互连的关键技术难题,尤其能解决因PCB板翘曲引起的互连失效问题,从而为晶圆集成系统与传统印制电路集成系统混合集成提供可靠的技术保障。
The invention discloses an interconnection structure between a wafer integrated system and a top PCB board and a manufacturing method thereof, including a metal structural member, wherein a groove is arranged in the metal structural member, and a wafer integrated system is arranged in the groove, so that the The lower surface of the wafer integration system and the upper surface of the groove are also provided with thermally conductive materials, the top of the metal structure is connected to a rigid board, the rigid board is connected to a PCB board, and the PCB board is connected to There are a power module and an I/O module, an electrical connection device is arranged in the rigid board, the lower surface of the electrical connection device is connected to the wafer integrated system, and the upper surface of the electrical connection device is connected to the PCB board. The invention solves the key technical problem of interconnection between the wafer integrated system and the traditional PCB integrated system, especially the problem of interconnection failure caused by the warping of the PCB board, so as to provide a hybrid integration of the wafer integrated system and the traditional printed circuit integrated system Provide reliable technical support.
Description
技术领域technical field
本发明涉及一种晶圆集成系统技术领域,尤其涉及发明晶圆集成系统与顶部PCB板的互连结构及其制造方法。The present invention relates to the technical field of a wafer integrated system, in particular to an interconnection structure between the wafer integrated system and a top PCB board and a manufacturing method thereof.
背景技术Background technique
随着摩尔定律和登纳德缩放定律逐渐失效,工艺进步对计算性能的提升明显放缓,而万物互联的数据量却在指数级爆炸式增长,数据规模和计算能力的“剪刀差”鸿沟越来越大,集成电路正在迎来“后摩尔时代”的技术与产业重大变革期,体系架构的发展也出现了新的趋势。当前,软硬件协同计算正在成为新的计算模式,以面向应用的软件定义为中心,通过软件去定义硬件系统、网络平台乃至基础设施成为了新的服务模式。在2018年世界计算机体系结构大会(ISCA,International Symposium on Computer Architecture)上,图灵奖得主John L. Hennessy、David A. Patterson也指出,领域专用软硬件协同计算成为计算机体系结构发展的新方向。With the gradual failure of Moore's Law and Dennard's Law of Scaling, the improvement of computing performance by technological progress has slowed down significantly, while the amount of data in the Internet of Everything has exploded exponentially, and the "scissors" gap between data scale and computing power is getting wider and wider. The bigger the integrated circuit is, the "post-Moore era" is ushering in a period of major technological and industrial changes, and a new trend has emerged in the development of the system architecture. At present, software-hardware collaborative computing is becoming a new computing model, centering on application-oriented software definition, and defining hardware systems, network platforms and even infrastructure through software has become a new service model. At the 2018 World Conference on Computer Architecture (ISCA, International Symposium on Computer Architecture), Turing Award winners John L. Hennessy and David A. Patterson also pointed out that domain-specific software and hardware collaborative computing has become a new direction for the development of computer architecture.
针对摩尔定律已存在不可延续的难题,学术界和产业界主要采用系统级封装(SIP),基于封装的系统(SOP)或者芯片级集成(SOC)技术对摩尔定律进行扩展。高密度基板是SIP集成的物理载体,其功能包括元器件之间的电气互连,传输射频、模拟、数字等信号,并且可内埋集成部分无源元件以及功分器、滤波器等,为元器件提供散热通道。SIP封装技术本质上是采用多颗芯片利用flip chip工艺或者wire bonding工艺进行2D封装,封装后的器件仍需要贴装在PCB上与其它器件(如电源管理、接口驱动、I/O接口器件)协同工作。因此,由于SIP其本身集成规模的限制,以及部分功能集成手段的制约,仍很难综合解决散热、电源、外部互连和平台集成等系统必备需求,也无法构成独立的系统;SOC技术本质上仍是芯片设计技术,把不同功能相同工艺的芯片集成在一起,受制于芯片加工技术和半导体材料的性能,SOC难以形成功能强大的独立系统;SOP则是面向系统应用,基于系统主板将SIP、元器件和连接器、散热结构等部件集成到一个具备系统功能的广义封装内,SOP可以加载系统软件,可以具有完整的系统功能,是功能集成微系统最合理、最直观的集成形势,也是整机和系统的核心集成能力,但其尺寸较大,其设计理念仍基于传统组装技术。In view of the unsustainable problem of Moore's Law, academia and industry mainly use system-in-package (SIP), system-on-package (SOP) or chip-level integration (SOC) technology to expand Moore's Law. The high-density substrate is the physical carrier of SIP integration. Its functions include electrical interconnection between components, transmission of radio frequency, analog, digital and other signals, and can be embedded to integrate some passive components, power dividers, filters, etc. Components provide heat dissipation channels. SIP packaging technology is essentially 2D packaging using multiple chips using flip chip process or wire bonding process. The packaged devices still need to be mounted on the PCB with other devices (such as power management, interface drivers, and I/O interface devices). Collaborative work. Therefore, due to the limitation of SIP's own integration scale and the restriction of some functional integration methods, it is still difficult to comprehensively solve the necessary system requirements such as heat dissipation, power supply, external interconnection and platform integration, and it cannot form an independent system; the essence of SOC technology It is still the chip design technology, which integrates chips with different functions and the same process. It is limited by the chip processing technology and the performance of semiconductor materials. It is difficult for SOC to form a powerful independent system; SOP is for system applications, based on the system motherboard. , components and connectors, heat dissipation structure and other components are integrated into a generalized package with system functions. SOP can load system software and have complete system functions. It is the most reasonable and intuitive integration situation for functional integrated microsystems. The core integration capability of the whole machine and system, but its size is large, and its design concept is still based on traditional assembly technology.
与SIP、SOC、SOP不同的是:晶圆级系统所使用的基板为整张半导体晶圆,如2至12英寸硅晶圆,晶圆不划片,晶圆使用RDL工艺进行布线,晶圆采用半导体工艺根据系统功能制备有源器件,如开关、运算放大器、ADC、逻辑单元电路等。也可根据系统应用需求不制备器件,仅使用RDL布线,使用整张晶圆替代传统基板。晶上系统贯穿到集成电路设计、加工和封装的全流程,融合预制件组装和晶圆集成等先进理念。借助晶圆级互连的高带宽、低延迟、低功耗等显著优势,可以实现单一晶圆上集成成千上万的传感、射频、计算、存储、通信等“预制件”颗粒。打破现有集成电路的设计方法、实现材料、集成方式等边界条件,将2D封装升级至2.5D/3D封装,将单一工艺拓展至多种工艺,将硅基材料拓展至多种异质基材,将刚性的系统结构提升至柔性的软件定义结构,有效破解当前芯片性能极限并打破关键信息基础设施依赖“堆砌式”工程技术路线面临的“天花板效应”。刷新传统装备或系统的技术物理形态,使系统综合技术指标获得连乘性增益,满足智能时代5G、大数据、云平台、AI、边缘计算、智慧网络等新一代基础设施的可持续发展需求。然而,受晶圆的机械强度及RDL布线规则约束,晶圆集成系统难度遇到前所未有的挑战,特别是8英寸以上晶圆集成系统的供电、散热等关键技术仍未得到有效地解决。主要技术难点在于供电系统与晶圆集成系统之间如何形成稳定可靠的电气连接,目前尚无很好的解决方案。The difference from SIP, SOC and SOP is that the substrate used in the wafer-level system is the entire semiconductor wafer, such as a 2- to 12-inch silicon wafer, the wafer is not diced, the wafer is wired using the RDL process, and the wafer is Active devices, such as switches, operational amplifiers, ADCs, logic cell circuits, etc., are fabricated according to system functions using semiconductor processes. It is also possible to not prepare devices according to the system application requirements, only use RDL wiring, and use the entire wafer to replace the traditional substrate. The on-chip system runs through the entire process of integrated circuit design, processing and packaging, integrating advanced concepts such as prefab assembly and wafer integration. With the significant advantages of wafer-level interconnection such as high bandwidth, low latency, and low power consumption, it is possible to integrate thousands of "prefabricated" particles such as sensing, radio frequency, computing, storage, and communication on a single wafer. Breaking the boundary conditions of existing integrated circuit design methods, realization materials, integration methods, etc., upgrade 2D packaging to 2.5D/3D packaging, expand a single process to a variety of processes, expand silicon-based materials to a variety of heterogeneous substrates, and expand The rigid system structure is upgraded to a flexible software-defined structure, effectively breaking the current chip performance limit and breaking the "ceiling effect" faced by key information infrastructures relying on "stacked" engineering technology routes. Refresh the technical and physical form of traditional equipment or systems, so that the comprehensive technical indicators of the system can obtain continuous gains, and meet the sustainable development needs of new-generation infrastructure such as 5G, big data, cloud platforms, AI, edge computing, and smart networks in the intelligent era. However, restricted by the mechanical strength of the wafer and the RDL wiring rules, the difficulty of the wafer integrated system has encountered unprecedented challenges, especially the key technologies such as power supply and heat dissipation of the wafer integrated system larger than 8 inches have not been effectively solved. The main technical difficulty is how to form a stable and reliable electrical connection between the power supply system and the wafer integrated system, and there is no good solution yet.
本发明针对基于半导体封装工艺的晶圆集成系统与基于丝网印刷工艺的PCB电路板如何形成有效、可靠的互连互通问题开展技术创新,通过弹性连接、PCB抗翘曲预制件制作等手段有效地解决了大尺寸晶圆与PCB之间的信息交互问题。The present invention carries out technical innovation for the problem of how to form an effective and reliable interconnection between the wafer integrated system based on the semiconductor packaging process and the PCB circuit board based on the screen printing process. It solves the problem of information interaction between large-size wafers and PCBs.
发明内容SUMMARY OF THE INVENTION
本发明为了解决上述技术问题,提供晶圆集成系统与顶部PCB板的互连结构及其制造方法。In order to solve the above technical problems, the present invention provides an interconnection structure between a wafer integrated system and a top PCB board and a manufacturing method thereof.
本发明采用的技术方案如下:The technical scheme adopted in the present invention is as follows:
晶圆集成系统与顶部PCB板的互连结构,包括金属结构件,所述金属结构件内设置有凹槽,所述凹槽内设置有晶圆集成系统,所述晶圆集成系统的下表面与所述凹槽的上表面还设置有导热材料,所述金属结构件的顶端连接有刚性板,所述刚性板上连接有PCB板,所述PCB板上连接有电源模块和I/O模块,所述刚性板中设置有电气连接装置,所述电气连接装置的下表面连接所述晶圆集成系统,所述电气连接装置的上表面连接所述PCB板。The interconnection structure of the wafer integrated system and the top PCB board includes a metal structure, a groove is arranged in the metal structure, and a wafer integrated system is arranged in the groove, and the lower surface of the wafer integrated system A thermally conductive material is also provided on the upper surface of the groove, a rigid board is connected to the top of the metal structure, a PCB board is connected to the rigid board, and a power module and an I/O module are connected to the PCB board. , the rigid board is provided with an electrical connection device, the lower surface of the electrical connection device is connected to the wafer integrated system, and the upper surface of the electrical connection device is connected to the PCB board.
进一步地,所述晶圆集成系统包括晶圆、芯粒、金属凸点和填充物,所述晶圆上连接若干所述芯粒,相邻所述芯粒之间连接有所述金属凸点,相邻所述芯粒、晶圆及金属凸点之间设置有所述填充物。Further, the wafer integration system includes a wafer, core particles, metal bumps and fillers, a plurality of the core particles are connected on the wafer, and the metal bumps are connected between adjacent core particles and the filler is arranged between the adjacent core particles, wafers and metal bumps.
进一步地,所述金属凸点的结构为球形、半球形、立方体或者圆柱体。Further, the structure of the metal bump is spherical, hemispherical, cube or cylinder.
进一步地,所述填充物为绝缘有机物、二氧化硅或氮化硅。Further, the filler is insulating organic matter, silicon dioxide or silicon nitride.
进一步地,所述电气连接装置包括绝缘介质、弹性金属连接器和PCB焊盘,所述刚性板中设置有若干绝缘通孔,所述绝缘通孔的侧壁设置有所述绝缘介质,所述绝缘介质内侧设置有所述弹性金属连接器,所述弹性金属连接器的底端与所述金属凸点连接,所述弹性金属连接器的顶端连接所述PCB焊盘,所述PCB焊盘与所述PCB板的下表面连接。Further, the electrical connection device includes an insulating medium, an elastic metal connector and a PCB pad, a plurality of insulating through holes are arranged in the rigid board, and the insulating medium is arranged on the sidewalls of the insulating through holes, and the The inner side of the insulating medium is provided with the elastic metal connector, the bottom end of the elastic metal connector is connected to the metal bump, the top end of the elastic metal connector is connected to the PCB pad, and the PCB pad is connected to the metal bump. The lower surface of the PCB board is connected.
进一步地,所述绝缘介质为绝缘油漆、金属氧化物、树脂或有机胶。Further, the insulating medium is insulating paint, metal oxide, resin or organic glue.
进一步地,所述弹性金属连接器为毛纽扣、弹性针或微弹簧。Further, the elastic metal connector is a wool button, an elastic needle or a micro spring.
进一步地,所述金属结构件内部设置有液体冷却通道,所述液体冷却通道呈蛇形。Further, a liquid cooling channel is arranged inside the metal structure, and the liquid cooling channel is serpentine.
进一步地,所述导热材料为导热硅脂、导热硅胶或导热油脂。Further, the thermally conductive material is thermally conductive silicone grease, thermally conductive silicone or thermally conductive grease.
进一步地,所述刚性板为铜板、钢板、陶瓷板、玻璃板或树脂板。Further, the rigid plate is a copper plate, a steel plate, a ceramic plate, a glass plate or a resin plate.
进一步地,所述PCB板为两层或者两层以上的印制电路板。Further, the PCB board is a printed circuit board with two or more layers.
进一步地,所述电源模块包含DC-DC模组、LDO、隔离变压器和电源滤波网络,所述DC-DC模组、LDO、隔离变压器和电源滤波网络相互电连接。Further, the power supply module includes a DC-DC module, an LDO, an isolation transformer and a power supply filter network, and the DC-DC module, the LDO, the isolation transformer and the power supply filter network are electrically connected to each other.
进一步地,所述I/O模块包含接插件、接口驱动器件和串并转换器件,所述接插件、接口驱动器件和串并转换器件相互电连接。Further, the I/O module includes a connector, an interface driving device and a serial-parallel conversion device, and the connector, the interface driving device and the serial-parallel conversion device are electrically connected to each other.
本发明还提供晶圆集成系统与顶部PCB板的互连结构的制造方法,包括以下步骤:The present invention also provides a manufacturing method of the interconnection structure of the wafer integrated system and the top PCB board, comprising the following steps:
步骤S1:在晶圆上焊接若干芯粒,并在相邻芯粒之间连接金属凸点,金属凸点高度不低于芯粒高度,在芯粒、晶圆及金属凸点之间填充填充物形成晶圆集成系统,并通过CMP工艺磨平,露出金属凸点;Step S1: Weld several cores on the wafer, and connect metal bumps between adjacent cores, the height of the metal bumps is not lower than the height of the cores, and fill the cores, wafers and metal bumps The material forms a wafer integrated system, and is smoothed by the CMP process to expose the metal bumps;
步骤S2:在金属结构件内部制作密封性良好的蛇形的液体冷却通道,并制作液体冷却通道的输入和输出口,在金属结构件内部制作与晶圆集成系统相互契合的凹槽;Step S2: forming a serpentine liquid cooling channel with good sealing performance inside the metal structure, making the input and output ports of the liquid cooling channel, and making a groove in the metal structure that fits with the wafer integration system;
步骤S3:凹槽内底部均匀涂覆导热材料,将步骤S1处理后的晶圆集成系统装入凹槽中并贴合导热材料,压实排出界面空气,使晶圆集成系统高度不超出凹槽外围,形成底部预制件;Step S3: the inner bottom of the groove is evenly coated with a thermally conductive material, the wafer integrated system processed in step S1 is loaded into the groove and the thermally conductive material is attached, and the interface air is compressed and discharged so that the height of the wafer integrated system does not exceed the groove the periphery, forming the bottom preform;
步骤S4:刚性板上制作绝缘通孔,并在绝缘通孔的内壁焊接绝缘介质,将弹性金属连接器的顶端穿过绝缘通孔并与PCB焊盘接触,弹性金属连接器的底端与金属凸点贴合,PCB焊盘的顶端与PCB板连接,PCB板的上表面贴合电源模块和I/O模块,并将刚性板与PCB板连接形成顶部预制件;Step S4: an insulating through hole is made on the rigid board, and an insulating medium is welded on the inner wall of the insulating through hole, and the top end of the elastic metal connector is passed through the insulating through hole and is in contact with the PCB pad, and the bottom end of the elastic metal connector is connected with the metal Bump bonding, the top of the PCB pad is connected to the PCB board, the upper surface of the PCB board is attached to the power module and the I/O module, and the rigid board is connected to the PCB board to form a top prefab;
步骤S5:将底部预制件和顶部预制件连接,完成装配。Step S5: Connect the bottom prefab and the top prefab to complete the assembly.
本发明的有益效果是:利用刚性板的抗弯曲能力和平整性,修正并改善PCB板在多次高温层压及正反面残铜率不同、内层走线不对称、过孔不对称导致的翘曲问题,使PCB板的翘曲率下降至少一个数量级。由于基于微纳工艺的晶圆集成系统具有加工精度高,线条宽度可在纳米级别,压焊点仅有10um至100um,这比印刷电路工艺的加工精度高出2个数量级。本发明基于印刷电路工艺和微纳工艺开展互连和互通创新,将两种工艺技术很好地结合在一起,通过弹性金属连接器降低工艺剪刀差,通过刚性结构消除柔性翘曲,通过金属结构件作为整体支撑,消除因振动、挤压对晶圆集成系统的破坏,显著提高了整体装配结构的可靠性。通过导热硅脂固定晶圆集成系统,一方面降低了晶圆集成系统的下表面与金属结构件凹槽上表面的界面热阻,可以显著提高晶圆集成系统的热扩散能力,另一方面,导热硅脂属于粘稠膏状物,能很好地缓冲来自弹性金属连接器传导至晶圆集成系统的压应力,可显著提高晶圆集成系统抗碎裂的性能。本发明从技术层面解决晶圆集成系统与传统PCB集成系统互通互连的关键技术难题,尤其能解决因PCB板翘曲引起的互连失效问题;从装配和可靠性层面解决了晶圆集成系统与外围电路(如电源管理、I/O接口)的连接和装配技术;从热管理角度解决了晶圆集成系统高密度热功率导热、散热问题。因此,本发明可为信息交换提供技术支撑,为晶圆集成系统与传统印制电路集成系统混合集成提供可靠的技术保障。The beneficial effects of the invention are: using the bending resistance and flatness of the rigid board to correct and improve the PCB board caused by multiple high-temperature laminations, different residual copper rates on the front and back sides, asymmetric inner layer wiring, and asymmetric via holes. The warpage problem reduces the warpage rate of the PCB board by at least an order of magnitude. Because the wafer integrated system based on the micro-nano process has high processing precision, the line width can be at the nanometer level, and the bonding point is only 10um to 100um, which is 2 orders of magnitude higher than the processing precision of the printed circuit process. The invention carries out interconnection and intercommunication innovation based on the printed circuit process and the micro-nano process, and combines the two process technologies well. As an overall support, it eliminates the damage to the wafer integrated system due to vibration and extrusion, and significantly improves the reliability of the overall assembly structure. By fixing the wafer integrated system with thermal grease, on the one hand, the interface thermal resistance between the lower surface of the wafer integrated system and the upper surface of the groove of the metal structure is reduced, which can significantly improve the thermal diffusion capacity of the wafer integrated system. Thermal grease is a viscous paste that can well buffer the compressive stress transmitted from the elastic metal connector to the wafer integrated system, which can significantly improve the chip integrated system's resistance to chipping. The invention solves the key technical problem of interconnection between the wafer integrated system and the traditional PCB integrated system from the technical level, especially the problem of interconnection failure caused by the warping of the PCB board; the wafer integrated system is solved from the assembly and reliability levels. Connection and assembly technology with peripheral circuits (such as power management, I/O interface); from the perspective of thermal management, it solves the heat conduction and heat dissipation problems of high-density thermal power in wafer integrated systems. Therefore, the present invention can provide technical support for information exchange, and provide reliable technical guarantee for the hybrid integration of the wafer integrated system and the traditional printed circuit integrated system.
附图说明Description of drawings
图1为本发明的结构示意图;Fig. 1 is the structural representation of the present invention;
图2为本发明实施例的金属结构件俯视图;2 is a top view of a metal structure according to an embodiment of the present invention;
图3为本发明实施例的金属结构件左视图;FIG. 3 is a left side view of a metal structure according to an embodiment of the present invention;
图4为本发明实施例的液体冷却通道示意图。FIG. 4 is a schematic diagram of a liquid cooling channel according to an embodiment of the present invention.
附图标记说明Description of reference numerals
1-金属结构件,11-凹槽,12-液体冷却通道,2-晶圆集成系统,21-晶圆,22-芯粒,23-金属凸点,24-填充物,3-导热材料,4-沉头螺栓,5-刚性板,51-绝缘通孔,6-螺栓,7-PCB板,8-电源模块,9-I/O模块,10-电气连接装置,101-绝缘介质,102-弹性金属连接器,103-PCB焊盘。1-metal structure, 11-groove, 12-liquid cooling channel, 2-wafer integrated system, 21-wafer, 22-die, 23-metal bump, 24-filler, 3-thermally conductive material, 4- Countersunk head bolt, 5- Rigid plate, 51- Insulation through hole, 6- Bolt, 7- PCB board, 8- Power module, 9- I/O module, 10- Electrical connection device, 101- Insulation medium, 102 -Elastic metal connector, 103-PCB pad.
具体实施方式Detailed ways
以下对至少一个示例性实施例的描述实际上仅仅是说明性的,决不作为对本发明及其应用或使用的任何限制。基于本发明中的实施例,本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.
见图1,晶圆集成系统与顶部PCB板的互连结构,包括金属结构件1,所述金属结构件1内设置有凹槽11,所述凹槽11内设置有晶圆集成系统2,所述晶圆集成系统2的下表面与所述凹槽11的上表面还设置有导热材料3,所述金属结构件1的顶端连接有刚性板5,所述刚性板5上连接有PCB板7,所述PCB板7上连接有电源模块8和I/O模块9,所述刚性板5中设置有电气连接装置10,所述电气连接装置10的下表面连接所述晶圆集成系统2,所述电气连接装置10的上表面连接所述PCB板7。Referring to FIG. 1 , the interconnection structure of the wafer integrated system and the top PCB board includes a metal
所述晶圆集成系统2包括晶圆21、芯粒22、金属凸点23和填充物24,所述晶圆21上连接若干所述芯粒22,相邻所述芯粒22之间连接有所述金属凸点23,相邻所述芯粒22、晶圆21及金属凸点23之间设置有所述填充物24。The
所述金属凸点23的结构为球形、半球形、立方体或者圆柱体。The structure of the metal bumps 23 is spherical, hemispherical, cubic or cylindrical.
所述填充物24为绝缘有机物、二氧化硅或氮化硅。The
所述电气连接装置10包括绝缘介质101、弹性金属连接器102和PCB焊盘103,所述刚性板5中设置有若干绝缘通孔51,所述绝缘通孔51的侧壁设置有所述绝缘介质101,所述绝缘介质101内侧设置有所述弹性金属连接器102,所述弹性金属连接器102的底端与所述金属凸点23连接,所述弹性金属连接器102的顶端连接所述PCB焊盘103,所述PCB焊盘103与所述PCB板7的下表面连接。The
所述绝缘介质101为绝缘油漆、金属氧化物、树脂或有机胶。The insulating
所述弹性金属连接器102为毛纽扣、弹性针或微弹簧。The
所述金属结构件1内部设置有液体冷却通道12,所述液体冷却通道12呈蛇形。A
所述导热材料3为导热硅脂、导热硅胶或导热油脂。The thermally
所述刚性板5为铜板、钢板、陶瓷板、玻璃板或树脂板。The
所述PCB板7为两层或者两层以上的印制电路板。The
所述电源模块8包含DC-DC模组、LDO、隔离变压器和电源滤波网络,所述DC-DC模组、LDO、隔离变压器和电源滤波网络相互电连接。The
所述I/O模块9包含接插件、接口驱动器件和串并转换器件,所述接插件、接口驱动器件和串并转换器件相互电连接。The I/
一种晶圆集成系统与顶部PCB板的互连结构的制造方法,包括以下步骤:A manufacturing method of an interconnection structure of a wafer integrated system and a top PCB board, comprising the following steps:
步骤S1:在晶圆21上焊接若干芯粒22,并在相邻芯粒22之间连接金属凸点23,金属凸点23高度不低于芯粒22高度,在芯粒22、晶圆21及金属凸点23之间填充填充物24形成晶圆集成系统2,并通过CMP工艺磨平,露出金属凸点23;Step S1: Weld several cores 22 on the
步骤S2:在金属结构件1内部制作密封性良好的蛇形的液体冷却通道12,并制作液体冷却通道12的输入和输出口,在金属结构件1内部制作与晶圆集成系统2相互契合的凹槽11;Step S2 : making a serpentine
步骤S3:凹槽11内底部均匀涂覆导热材料3,将步骤S1处理后的晶圆集成系统2装入凹槽11中并贴合导热材料3,压实排出界面空气,使晶圆集成系统2高度不超出凹槽11外围,形成底部预制件;Step S3: the inner bottom of the
步骤S4:刚性板5上制作绝缘通孔51,并在绝缘通孔51的内壁焊接绝缘介质101,将弹性金属连接器102的顶端穿过绝缘通孔51并与PCB焊盘103接触,弹性金属连接器102的底端与金属凸点23贴合,PCB焊盘103的顶端与PCB板7连接,PCB板7的上表面贴合电源模块8和I/O模块9,并将刚性板5与PCB板7连接形成顶部预制件;Step S4: An insulating through
步骤S5:将底部预制件和顶部预制件连接,完成装配。Step S5: Connect the bottom prefab and the top prefab to complete the assembly.
实施例1Example 1
参见图2,采用机械加工工艺制造紫铜结构件,紫铜结构件外形尺寸为400 mm×400 mm×20mm。Referring to Fig. 2, the red copper structural parts are manufactured by a machining process, and the external dimensions of the red copper structural parts are 400 mm × 400 mm × 20 mm.
参见图3,紫铜结构件内部加工液体冷却通道12,流道截面为边长4mm的正方形,成蛇形走向,壁厚为4mm。紫铜结构件加工足量M3螺纹孔,相邻螺纹孔间距35-40mm,孔深9-10mm,四个角上加工高度1.5mm,直径1.5mm定位销,尺寸误差±10um以内,并在离定位销5mm处加工8个M4的螺纹通孔,紫铜结构件内部铣出与12英寸晶圆尺寸匹配的凹槽11,凹槽11深度为1.2mm-1.22mm,内部直径为304.81mm,且内壁加工与晶圆定位标记匹配的凸点,以固定晶圆无法转动,参见图4。Referring to FIG. 3 , the
采用顶部PCB板7与晶圆集成系统2连接时,晶圆集成系统2中的芯粒22间距须大于350um,在此基础上使用金属沉积和电镀工艺在晶圆集成系统2上制备直径100-150um、高度150um铜柱,并使用有机材料molding固定,厚度为160-200um,再使用CMP工艺磨平,露出铜柱。When the
在经过处理后的晶圆集成系统2背面均匀涂覆导热硅脂,涂覆厚度为250um左右,并将该晶圆集成系统2贴于紫铜结构件凹槽中,压实整平,以晶圆集成系统2高度不高出凹槽边界为准。The back of the processed
机械加工高强度航空铝合金板,外形为400mm×400mm×1.7mm,再根据晶圆集成系统2上的铜柱的分布,精准加工数量、位置与铜柱完全匹配的直径0.3mm的绝缘通孔;加工数量、位置与紫铜结构件M3螺纹孔完全匹配的通孔和与直径1.5mm定位销匹配的定位孔,孔精度优于±10um;加工与待固定的PCB板7孔位置、数量匹配的M2.5沉头螺丝通孔。最后将机械加工完毕的高强度航空铝合金板采用热氧化等工艺对表面及过孔进行绝缘处理。Machined high-strength aviation aluminum alloy plate with a shape of 400mm×400mm×1.7mm, and then according to the distribution of copper pillars on the
将正面装配有电源模块8、I/O模块9、驱动电路,背面只露焊盘的PCB板7与加工完成的高强度航空铝合金板,用若干M2.5螺钉及配套的弹片、垫片、螺母固定,以消除PCB板7的翘曲。其中PCB板7主要技术参数为350mm×350mm×1.5mm,板材为松下M6,层数为12层,表层镀金。Assemble the
将若干直径10mil(0.254mm),长度70mil(1.778mm)的毛纽扣塞入直径0.3mm的绝缘通孔51中,使毛纽扣一端与PCB焊盘103接触,另一端略高出高强度航空铝合金板平面,并注意检查是否有遗漏,是否有毛纽扣高度低于高强度航空铝合金板平面,如有,则需要更换毛纽扣。Insert a number of wool buttons with a diameter of 10 mil (0.254 mm) and a length of 70 mil (1.778 mm) into the insulating through
将紫铜结构件与PCB板7以及合金板组合件贴合在一起,贴合时根据紫铜结构件上定位销和合金板上的定位孔进行对准,贴合完成后使用M3×8的组合螺钉加以固定,从而完成装配。Laminate the copper structure with the
更详细的实施前后效果对比参见表1,表1从PCB板7的翘曲率,晶圆集成系统2翘曲率,PCB板7与晶圆集成系统2贴合形成的高度差变化情况,使用液冷散热前后晶圆集成系统2工作温度和电气连接可靠性等方面加以对比分析。从表1可以发现,由于PCB板7与刚性板贴合固定后,其翘曲率由0.5%降为0.03%,翘曲高度差仅有0.105mm。而晶圆集成系统2设置有芯粒22,因使用热压键合工艺时应力的释放,也存在一定程度的翘曲,其翘曲率约0.05%,高度差为0.1525mm。从表1还可以看到,与刚性贴合固定后的PCB板7翘曲程度略优于晶圆集成系统2,这为PCB板7与晶圆集成系统2的互连提供了可能。另外,表中考虑的是PCB板7与晶圆21翘曲方向正好相反的情况,实际上,PCB板7的翘曲并不完全与晶圆21翘曲方向相反,因此,毛纽扣的压缩量可能更小,连接的可靠性更高。For a more detailed comparison of the effects before and after implementation, see Table 1. In Table 1, the warpage rate of
表1本实施例前后对比Table 1 Comparison before and after the present embodiment
综上所述,本发明实施例提供了可解决大尺寸晶圆集成系统2与翘曲PCB板7印制电路系统互连互通问题,从而为信息交换提供技术支撑,为晶圆集成系统2与传统印制电路集成系统混合集成提供可靠的技术保障。To sum up, the embodiment of the present invention provides a solution to the interconnection problem between the large-size wafer integrated
以上所述仅为本发明的优选实施例而已,并不用于限制本发明,对于本领域的技术人员来说,本发明可以有各种更改和变化。凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.
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Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200511531A (en) * | 2003-09-08 | 2005-03-16 | Advanced Semiconductor Eng | Package stack module |
TW200822830A (en) * | 2006-11-13 | 2008-05-16 | Phoenix Prec Technology Corp | Circuit board structure and fabrication method thereof |
JP2008135584A (en) * | 2006-11-29 | 2008-06-12 | Hitachi Ltd | Multilayer printed wiring board manufacturing method and printed wiring board |
CN102280430A (en) * | 2010-06-10 | 2011-12-14 | 富士通株式会社 | Mounting structure, electronic component, circuit board, board assembly, electronic device, and stress relaxation member |
CN102339929A (en) * | 2010-07-29 | 2012-02-01 | 富士迈半导体精密工业(上海)有限公司 | Manufacturing method of LED lighting components |
CN107734227A (en) * | 2017-10-27 | 2018-02-23 | 昆山丘钛微电子科技有限公司 | Image sensor package structure, camera module and preparation method thereof |
CN208655611U (en) * | 2018-06-26 | 2019-03-26 | 华天科技(昆山)电子有限公司 | Improve the fan-out-type wafer stage chip encapsulating structure of warpage |
CN209418538U (en) * | 2018-12-21 | 2019-09-20 | 深圳市穗晶光电股份有限公司 | A kind of packaging structure of light source of high power LED |
CN110572954A (en) * | 2019-09-11 | 2019-12-13 | 苏州汇川技术有限公司 | pin assembly guide and circuit board assembly |
CN209914218U (en) * | 2019-04-27 | 2020-01-07 | 宏俐(汕头)电子科技有限公司 | Frock is rectified to circuit board perk |
CN111755409A (en) * | 2019-03-27 | 2020-10-09 | 恒劲科技股份有限公司 | Semiconductor packaging substrate and its manufacturing method and electronic package and its manufacturing method |
CN112997305A (en) * | 2019-01-17 | 2021-06-18 | 华为技术有限公司 | Chip packaging structure and electronic equipment |
CN216435891U (en) * | 2021-10-19 | 2022-05-03 | 悦城科技股份有限公司 | Three-dimensional chip packaging structure, interposer and carrier plate thereof |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7105918B2 (en) * | 2004-07-29 | 2006-09-12 | Micron Technology, Inc. | Interposer with flexible solder pad elements and methods of manufacturing the same |
CN113540066A (en) * | 2021-07-16 | 2021-10-22 | 芯知微(上海)电子科技有限公司 | System-level packaging structure and packaging method |
US20220117080A1 (en) * | 2021-12-17 | 2022-04-14 | Intel Corporation | Ball grid array chip (bga) package cooling assembly with bolster plate |
-
2022
- 2022-05-12 CN CN202210511528.XA patent/CN114630494B/en active Active
Patent Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200511531A (en) * | 2003-09-08 | 2005-03-16 | Advanced Semiconductor Eng | Package stack module |
TW200822830A (en) * | 2006-11-13 | 2008-05-16 | Phoenix Prec Technology Corp | Circuit board structure and fabrication method thereof |
JP2008135584A (en) * | 2006-11-29 | 2008-06-12 | Hitachi Ltd | Multilayer printed wiring board manufacturing method and printed wiring board |
CN102280430A (en) * | 2010-06-10 | 2011-12-14 | 富士通株式会社 | Mounting structure, electronic component, circuit board, board assembly, electronic device, and stress relaxation member |
CN102339929A (en) * | 2010-07-29 | 2012-02-01 | 富士迈半导体精密工业(上海)有限公司 | Manufacturing method of LED lighting components |
CN107734227A (en) * | 2017-10-27 | 2018-02-23 | 昆山丘钛微电子科技有限公司 | Image sensor package structure, camera module and preparation method thereof |
CN208655611U (en) * | 2018-06-26 | 2019-03-26 | 华天科技(昆山)电子有限公司 | Improve the fan-out-type wafer stage chip encapsulating structure of warpage |
CN209418538U (en) * | 2018-12-21 | 2019-09-20 | 深圳市穗晶光电股份有限公司 | A kind of packaging structure of light source of high power LED |
CN112997305A (en) * | 2019-01-17 | 2021-06-18 | 华为技术有限公司 | Chip packaging structure and electronic equipment |
CN111755409A (en) * | 2019-03-27 | 2020-10-09 | 恒劲科技股份有限公司 | Semiconductor packaging substrate and its manufacturing method and electronic package and its manufacturing method |
CN209914218U (en) * | 2019-04-27 | 2020-01-07 | 宏俐(汕头)电子科技有限公司 | Frock is rectified to circuit board perk |
CN110572954A (en) * | 2019-09-11 | 2019-12-13 | 苏州汇川技术有限公司 | pin assembly guide and circuit board assembly |
CN216435891U (en) * | 2021-10-19 | 2022-05-03 | 悦城科技股份有限公司 | Three-dimensional chip packaging structure, interposer and carrier plate thereof |
Non-Patent Citations (1)
Title |
---|
大面积印制电路板翘曲的改善;黄林峰等;《印制电路信息》;20170210(第02期);第64-67页 * |
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