TW571372B - Substrate with plated metal layer over pads thereon, and method for fabricating the same - Google Patents

Abstract

A substrate with a plated metal layer over pads thereon, and a method for fabricating the substrate are proposed. The substrate is formed with a plurality of pads on at least a surface thereof, and a conductive film is formed on the surface of the substrate. A photoresist is applied over the conductive film and formed with a plurality of through holes for exposing portions of the conductive film corresponding in position to the pads on the substrate. Then, the exposed portions of the conductive film are removed to expose the pads on the substrate. After a metal layer such as Ni/Au is deposited on the pads by a plating method, the photoresist and the conductive film underneath the photoresist are removed. Finally, a solder mask is applied on the surface of the substrate and formed with a plurality of openings for exposing the pads with the plated metal layer thereon; this can eliminate drawbacks induced by conventional chemical Ni/Au deposition, and effectively increase routing area of the substrate without having to form plating traces on the substrate.

Description

571372, V. Description of the invention (l) Field of invention]

-The present invention relates to a semiconductor package substrate electrical g metal layer and a manufacturing method thereof, and in particular, a nickel / gold metal layer is plated on a gold packaging substrate < 1 塾 electroplated gold surface and a manufacturing method thereof, so as to expose surface electrical properties Electrical connection pad of connection quality. Good supply [Previous technology] Due to the trend of electronic production, semiconductors are used for conductive materials composed of semiconductor materials to provide the electrical coupling of the remaining conductive elements as the exposed surface of the transmission electrical connection, and also the pad body Of oxidation. -Substrate (Flip-chip bump solder pad (Bump The electrical connection pad can also be a ball pad (Ball pad), 4-nickel / gold metal layer, said pad (usually gold to improve the quality of bumps, pre-soldering. 0 package) The industry is also facing many key points on the substrate surface of the package made by Xu Xi during the manufacturing process. The wiring is extended from it = if it is a copper signal or power supply, it is usually connected to 23 like nickel / gold. (Ni / Au) The metal connection is as effective as a gold wire, bump or solder ball, and the chip or the electric can effectively prevent the electric due to the influence of the external environment. '= The electrical connection can be, for example, a semiconductor flip chip package The package substrate is electrically coupled to the wafer, or the pad is a pre-solder pad. For example, the package substrate and the circuit board are electrically coupled to each other. The electrical type π 1 which is not covered with copper / in the recording / gold metal layer is susceptible to oxidation due to external environmental influences, and the electrical connection with a # ball or the like placed on the electrical pad is lightly familiar In the art, there is a nickel / gold metal layer formed on the surface of the main electrical connection pad of the electric remote post.

571372 V. Description of the invention (2) The methods include chemical nickel / gold process and electroplated nickel / gold process, etc. However, the chemical nickel / gold process often suffers from poor solderability such as jump plating and black pad. Or insufficient solder joint strength. This jump plating problem occurs when the nickel bath is cooled and rested for a period of time during the production process. Even if all the operating conditions are prepared, there will still be insufficient plating capacity and full plating, which will prevent subsequent gold plating. Therefore, the phenomenon of exposed copper appears; and the formation of the black pad problem is due to the excessive oxidation reaction of the nickel surface of the nickel surface during the immersion gold replacement, and the irregular deposition of very large gold atoms and the sparseness of its coarse grains Porous, causing the bottom nickel to continue to be motivated by the chemical battery effect, and continue to produce oxidation and aging, so that nickel rust that can not be removed under the gold surface continues to accumulate; the jump plating and black of the above chemical nickel / gold process The problems of the pads are likely to cause the phenomenon that the gold wires, solder bumps, pre-solders, or solder balls, etc., will not be able to be electrically coupled to the electrical connection pads in the future, resulting in reliability issues. In order to avoid the above-mentioned problems of the chemical nickel / gold process, another method for forming a nickel / gold metal layer on the surface of the electrical connection pad is to use an electroplated nickel / gold process. As shown in FIG. 1, the conventional nickel / gold plating process is known. A plurality of plated conductive wires 1 1 are additionally arranged on the packaging substrate 1 on which the multi-gluten electrical connection pads 10 are formed, so that a nickel / gold metal layer 1 2 is plated on the electrical connection pads 1 through the plated conductive wires 1 1. 0, but this process must pre-arrange a large number of plated wires 11 for plating, which not only occupies the circuit wiring area of the package substrate 1, reduces the area available for wiring, but also uses extra plated wires in high-frequency use. The antenna effect of 1 1 causes noise. In order to solve the above problems of electroplating nickel / gold process, the other adopts electroplating

571372, V. Description of the invention (3) The method of the process GPP (Goll pattern ρ1 ating), as shown in Figures 2A to 2D, has been familiar to the general industry. In this process, a conductive layer 21 (as shown in FIG. 2A) is formed on each of the upper and lower surfaces of a substrate 2 for carrying a semiconductor wafer. A plurality of via holes (PTH) or blind holes ( Blind via) (not shown); then, a photoresist layer 22 is covered on the conductive layer 21 of the substrate outside the area where the circuit is to be formed, and the conductive layer 21 is used as a current conduction path, and the conductive layer 2 1 electroplating a nickel / gold metal layer 2 3 (as shown in FIG. 2B) where it is not covered by the photoresist layer 2 2; thereafter, remove the photoresist layer 2 2 and leave only the recording / gold The metal layer 23 (as shown in FIG. 2C); and then the recording / gold metal layer 23 is used as a masking barrier layer, and the conductive layer 21 is patterned by etching to define a circuit layer 2 4 to An exposed / gold metal layer 23 is electroplated on the exposed surface of the circuit layer 24 (as shown in FIG. 2D). Although this conventional technique does not require the provision of additional electrical forged wires, only the surface of the entire circuit layer of the substrate (including the electrical connection pads and all conductive lines) is covered with a metal / gold metal layer, and the metal / gold metal layer raw material Very expensive, resulting in a significant increase in production costs; furthermore, because the top surface of the conductive layer of the circuit layer is covered with a nickel / gold metal layer, when a solder resist layer is subsequently covered on the substrate, it is easy to cause both The material characteristics are different, and the combination of stability cannot be achieved, resulting in the lack of reliability. ® Therefore, how to use a simple process and cost less, while avoiding the reliability issues such as jump plating and black pads caused by the chemical nickel / gold process, or the additional plating leads and cost waste derived from the conventional nickel / gold process? The problem has become a problem that is urgently needed to be solved.

Page 10 V. Description of the Invention (4) [Summary of the Invention]

In view of providing a semi-method, it is helpful to use a metal layer, which is conducive to electrically jumping the bell generated by the electroplating gold of the pad of the present invention. The cost of forming gold on the entire layer of wire plating pads of the electroplated gold plate. The above-mentioned conventional conductive package-based electrical connection pads are on gold wires and soldered metal layers to make the electrical board electrical connection pads electrically = the main purpose is to expose the exposed surface of the plating; f layer and its production of tin bumps or solder balls and wafers. The gold / gold connection pad is not easy to be oxidized by the electrical pad body of the circuit board. 1 The production of another purpose-oriented layer and the black pad, etc., which are guided by the influence of the environment, and the production line of the other-purpose layer. By using the large-plated wire, the production layer of the other purpose-layer is covered with the required layer. Nickel = t, -Semiconductor package substrate electrical method: can avoid the conventional chemical recording / gold process 2: to effectively improve the reliability of the sealing structure.糸 θt, a method for electrically connecting semiconductor packaging substrates, does not need to increase the effective wiring area of the packaging substrates on the surface of the packaging substrates, and the problems of noise interference. Provides a method for electrically connecting semiconductor package substrates. 'It can be avoided that the conventional manufacturing process must cover a nickel / gold metal layer on the packaging substrate, and only the electrical / gold metal layer can be used to effectively reduce electroplating / and its purpose.' The electrical metal layer of the semiconductor package substrate of the present invention is mainly formed on at least one surface of the package substrate. The electrical connection pads are plated with a metal layer, and a solder resist layer is provided on the surface. Layer has a plurality of electrical connection pads with open metal layers, at least one of which is electrically connected to a lift-off connection. The electrical plating of the package substrate has a plurality of electrical properties.

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571372, V. Description of the invention (5) The pad is not in communication with any plated wire. The method for manufacturing the electroplated metal layer of the electrical connection pad of the semiconductor package substrate of the present invention includes the following steps: First, a semiconductor package substrate with at least one surface having a plurality of electrical connection pads is provided, and the surface of the substrate is covered with a conductive film. (Electrically conductive film). Next, a photoresist layer is formed on the conductive film, and the photoresist layer is formed with a plurality of openings to expose the conductive film on the surface of the electrical connection pad. Then, the conductive film not covered by the photoresist layer is removed, so that the electrical connection pad can be exposed in the opening of the photoresist layer. β, and electroplating the package substrate so that the exposed surface of the electrical connection pad is electroplated with a metal layer to be formed such as metal / gold. After that, the photoresist layer and the conductive film covered by the photoresist layer are removed. A solder resist layer is formed on the surface of the package substrate, and the solder resist layer has a plurality of openings to expose the electrical connection pads of the electroplated metal layer. By the method for manufacturing the electroplated metal layer of the electrical connection pad of the semiconductor package substrate of the present invention, not only can the exposed surface of the electrical connection pad be completely covered with a nickel / gold-containing metal layer, which can effectively help gold wires and solder joints. The bumps, solder balls, etc. are electrically coupled to the chip or the circuit board, and at the same time, it is not easy to cause the electrical connection pad body to be oxidized due to the influence of the external ring; and to avoid the jump plating caused by the conventional chemical / gold process And black pads to effectively improve the reliability of the package structure. At the same time, when electroplating nickel / gold, there is no need to arrange electrical and mineral wires on the surface of the packaging substrate, so as to greatly increase the effective wiring area of the packaging substrate ’and reduce the problem of noise interference caused by the laying of plated wiring;

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To avoid the conventional electric money I, when a nickel-containing 0 / gold process is covered, the metal layer of / gold must be on the entire circuit layer of the package substrate to effectively reduce the plating nickel / gold composition. The following examples are used to further The present invention is described in detail, but is not limited by these examples. < What's more, the electroplated metal layer of the electrical connection pad of the present invention can be widely used in general packaging substrates, and the drawings and explanation boards clearly explain its implementation, but this should not be used as a target range, and described first . ^ [Embodiment] Figure 3 is a schematic cross-sectional view of a plating metal layer of a connection pad of a semiconductor package substrate to which the present invention is applied. The package substrate 3 is a flip-chip grid array (F 丨 丨 ρ 丨 ρ grid array) package substrate, which includes a plurality of circuit layers 32 in which the insulating layer 3i and the disk p-edge layer are staggered, and runs through these The insulation layer is electrically connected to the via layer 3 3 of the circuit layer and covers and protects the substrate 3 and the top solder layer 38. < The insulating layer 3 1 of the substrate 3 may be composed of organic materials, fiber-reinf0rced organic materials, or particle reinforced (Part 1 cl e-re enforced) organic materials, such as epoxy resin (£ ? = ^ 1 ^ 3 11〇 Polyethylenimine (1 ^ 〇1: ^ 111] [(16), Bismaleimide / Diazine (Bismaieimide triazine —based) resin, cyanate ( Cyanate ester), etc. The circuit layer 32 can be produced by forming a metal conductive layer, such as a copper layer, on the insulating layer 3 1, and then forming a circuit patterned circuit layer 3 2 by using the etching and etching technology. ... wherein the package substrate ^

Page 13 571372, V. Description of the invention (7)-Bumps _ pre-bright tin to the second == 40 can be formed in the second table by forming most solder connections on it; 3 let the electrical properties _ Is used to plant a semiconductor wafer 4 that provides the completed flip-chip process for a fresh ball pad. Electrical connection: such as soldering to the circuit board. The cloth layer is provided by the circuit layer 32 and the electrical connection pad 35, and provides the first surface 3a and the second surface of the substrate. The second connection pad 35 prevents the electrical connection from being caused by the external environment. The bonding ability of the bump 39a or the solder ball 39b is effective for the effective connection to the solder exposed surface with a metal layer 35c as a metal barrier layer. The pad 35 outer barrier layer includes a nickel adhesive layer and is formed on the electrical property. 3 ^ Mon resistance layer. However, the barrier layer can also be protected by electroplating (gold on e 35).

VaP0r deP0Slt10n) and other methods, deposit gold, nickel? : (, Cal nickel / saturated, chromium / titanium, Ky / gold or nickel / bar / gold ^ ba silver, tin, ^ to form a solder resist layer 38 to cover the base formation. Then there are several openings 38a, so that the electrical connection surface, and the solder-repellent layer-shaped opening 38a, at least one of which is electrically connected to the line exposed on the fresh-reflective layer. 3 5 Ya is not connected with any electroplating, please refer to sections 4A to 4 Figure 4H, A is too large for the semiconductor package substrate of the present invention.

Page 14 571372 V. Description of the invention (8) Schematic diagram of the manufacturing method of the electroplated metal layer of the connection pad. As shown in FIG. 4A, a package substrate 3 is first provided. The package substrate may be a flip-chip package substrate as shown in FIG. 3 or a wire-type (W i r e b ο n d i n g) package substrate. The package substrate 3 has completed the required previous processes. For example, most of the via holes (PTH) or blind holes (B1 ind Via), etc. (not shown) are formed therein. The surface of the package substrate 3 has been formed with a The circuit patterned circuit layer 3 2 includes a plurality of electrical connections 塾 3 5 ^ Of course, it may also include a plurality of circuits formed on the surface of the package substrate 3. There are many circuit patterning technologies, but they are well-known process technologies in the industry, and they are not the technical features of this case, so I will not repeat them here. As shown in FIG. 4B, a conductive film 3 6 is coated on the surface of the package substrate 3; the conductive film 36 is mainly used as a current conduction path required for the electroplated metal layer 3 5 c described later, and can be made of metal, alloy, or stacked layers. The metal layer may be formed of a metal selected from the group consisting of copper, tin, copper, copper, copper, copper-copper alloy, or tin-copper alloy. However, according to practical experience, the conductive film 3 6 is preferably composed of copper or palladium particles (especially electroless plating), and can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), or electroless plating. Or chemical, study Shen Dian, for example: reduction (spu 11 ering), evaporation (evapoorati ο η), arc vapor deposition (ion vapor deposition), ion beam sputtering (ion beam sputtering), laser smelting deposition (Laser ablation deposition), plasma-assisted chemical vapor deposition, or organic metal chemical vapor deposition are formed on the surface of the package substrate. As shown in FIG. 4C, a photoresist layer is formed on the surface of the package substrate 3 covered with the conductive film 36 by printing, spin coating, or bonding.

Page 15 571372, V. Description of the invention (9) 乂 Ph〇t〇resist) 37, such as a dry film or liquid photoresist, etc., and the photoresist layer 37 is formed into a plurality of openings 3 7a, whereby The conductive film 36a on the surface of the electrical connection pad 35 is exposed. As shown in FIG. 4D, the conductive film 3 6a not covered by the photoresist layer 37 is removed by etching or laser technology, that is, the photoresist layer openings 37a are removed and covered with The conductive film 3 6 a of the electrical connection pad 3 5 reveals the electrical connection pad 35 α as shown in FIG. 4E, and then the packaging substrate 3 is plated with a metal layer step by electroplating. 4 The electroplated metal can be gold, lu, le, silver, tin, town / Iε, chromium / chin, Lu / gold, Iε / gold, or lu / g, etc. Due to the conductive properties of the conductive film 36, rhenium can be used as a current conduction path when electroplating, preferably the electroplating / gold metal layer, which is first plated with nickel and then plated with gold. Nickel / gold metal can be electroplated on the exposed surface of each electrical connection pad 35 through the conductive film 36, so that the exposed surface of the electrical connection pad 3 5 is covered with a plated metal layer 3 5c. Of course, the plated metal of the present invention The choice of material can also be only one of the foregoing, gold, or other metals, such as plating directly on the exposed surface of the electrical connection pads 35 with gold, which is a simple replacement, which should be implemented by the present invention. category. As shown in FIG. 4F, after the plating / gold layer 35c is finished on the exposed surface of the electrical connection pad 35, the photoresist layer 37 is removed first, and then the photoresist layer 3 is previously threatened. The conductive film 3 6 covered by 7 is removed, and as shown in FIG. 4G, the electroplated metal layer 3 5 c is to be formed to cover the exposed surface of the electrical connection pad 3 5. As shown in FIG. 4 (a), the surface of the package substrate 3 can be covered with a

Page 16 571372 V. Description of the invention (10) ~ 1 _______Solder mask 38, such as green paint, ^ Board 3 is protected from external environmental pollution, the rejection 9 is to protect the packaging base Opening holes 3 8 a, make the finished electroplated metal dry out $ 3 8 and form a plurality of openings 38 a of chromium in the solder resist layer. Among them, the company ’s 4 △ raw connection pad 35 can be significantly larger or smaller than the electrical connection pad. The size, Fei said that the hole 38a < aperture-type connection pad can be used to interface with the chip or circuit board with an electroplated metal layer for electrical connection through the semiconductor package substrate of the present invention. And its manufacturing method, it can not only provide "base: J pad electroplated metal layer is covered with a nickel / gold electroplated metal layer, which is connected to the electrical conductivity of the _Lin meter electrical components, the same day temple can also avoid The electrical connection is oxidized by the main body; it can avoid the problems such as jump plating and black cricket that are caused by the influence of the conventional I environment. When the surface shovel of the conductive connection pad = the letter of the packaging structure, the conductive film is used as a current conduction path ^ to the various electrical connection pads made of metal, and there is no need to separate the line on the surface of the packaging substrate = the packaging substrate. In order to greatly increase the effective wiring area of the package substrate, the noise interference problem caused by the conductive conductive plated wires can be arranged; in addition, the nickel / gold metal layer can be fixed and arranged on the electrical connection pad, which must be avoided in the package. The conventional electroplating layer is covered with a nickel / gold-containing metal layer, so that the entire layer of the circuit board has two I. Baizheng reduces the cost of the semiconductor package substrate of the invention by electrically connecting the electrical connection pads described in the Thai method , For example, packaging metal substrates When the pad, the solder pre-pad or a solder ball pad, the first wire ^ winter, the convex pads that, in fact several to electrically connect the electrical pads of interest is electrically connected as a current

571372, V. Description of the invention (11) The conductive path and the photoresist layer for the mask are designed and distributed on the surface of the substrate according to the actual manufacturing process, and the process can be implemented on one or both sides of the substrate. The specific embodiments described above are only used to illustrate the features and effects of the present invention, rather than to limit the implementable scope of the present invention. Any application of the present invention without departing from the spirit and technical scope of the invention disclosed above Equivalent changes and modifications that are disclosed within the invention and are completed should still be covered by the scope of patent application described below.

Page 571372 Simple description of the drawings [Simplified illustration of the drawings] Figure 1 is a schematic cross-sectional view of the conventional electrical connection pad of the package substrate plated with a nickel / gold metal layer; Figures 2 A to 2 D are another Conventional cross-sectional schematic diagram of the electroplating nickel / gold process of the electrical connection pads of the package substrate; FIG. 3 is a schematic cross-sectional schematic view of the electroplated metal layer of the electrical connection pads of the semiconductor package substrate of the present invention; and FIGS. 4A to 4H are the present invention. A schematic cross-sectional view of a method for manufacturing an electrical ore metal layer of a semiconductor package substrate electrical connection pad. [Description of component symbols] 1 package substrate 10 electrical connection pad 11 electroforged wire 12 recording / gold metal layer 2 substrate 21 conductive layer 22 photoresist layer 23 recording / gold metal layer 24 circuit layer 3 packaging substrate 3 a first surface 3b Second surface 31 Insulating layer 32 Circuit layer 33 Through hole 35 Electrical connection pad 35c Plating metal layer 36 Conductive film 3 6a Conductive film to be removed 37 Photoresist layer 37a Opening hole 38 Solder resist layer 38a Opening hole 39a Fresh tin bump 39b fresh ball 40 semiconductor wafer

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Claims (1)

571372, VI. Application for Patent Scope 1. A method for manufacturing a plating metal layer of an electrical connection pad of a semiconductor packaging substrate. The method includes the steps of: providing a packaging substrate having at least one surface with a plurality of electrical connection pads' on the substrate. The surface is covered with a conductive film, a photoresist layer is formed on the conductive film, and the photoresist layer is formed. • A plurality of openings to expose the conductive film on the surface of the electrical connection pad; A covered conductive film, so that the electrical connection pad can be exposed in the opening of the photoresist layer; electroplating the package substrate so that the exposed surface of the electrical connection pad is plated with a metal layer; and ♦ removing the photoresist layer And the conductive film it covers. 2. For example, the method for manufacturing an electroplated metal layer of an electrical connection pad of a semiconductor package substrate according to item 1 of the application, wherein the package substrate is a flip-chip package substrate. 3. The method for manufacturing the electrical connection pad of the semiconductor package substrate according to item 1 of the patent application. A method for manufacturing a metal plating layer, wherein the package substrate is a wire-bonded package substrate. The manufacturing method of the electroplated metal layer of the electrical connection pad of the semiconductor package substrate according to item 1 of the scope of patent application, wherein the electrical connection pad may be a bump in a dry finish *. The method for manufacturing an electroplated metal layer of an electrical connection pad of a semiconductor package substrate as claimed in item 1 of the patent application scope, wherein the electrical connection pad may be a solder ball pad. -6. If the semiconductor package substrate is electrically connected to the pad as described in item 1 of the scope of patent application Page 20 571372 VI. Method for manufacturing a metal-plated layer with a patent scope, wherein the electroplated metal layer can be gold, metal, metal, silver, tin, metal / chrome, chromium / titanium, metal / gold, metal / gold and metal Formed by a group consisting of metal / palladium / gold. 7. The manufacturing method of the electroplated metal layer of the electrical connection pad of the semiconductor package substrate according to item 1 of the application, wherein the conductive film may be selected from the group consisting of copper, tin, copper, chromium, titanium, copper-chromium alloy, and tin-fault. A group of metals formed by an alloy. 8. For example, a method for manufacturing a plating metal layer of an electrical connection pad of a semiconductor package substrate according to item 1 of the scope of patent application, wherein the conductive film can be sputtered, electrolessly plated, or physically and chemically deposited. Either way. 9. The method for manufacturing an electroplated metal layer of an electrical connection pad of a semiconductor package substrate according to item 1 of the scope of patent application, wherein the photoresist layer may be a dry film. 10. The method for manufacturing an electroplated metal layer of an electrical connection pad of a semiconductor package substrate according to item 1 of the scope of patent application, wherein the photoresist layer may be a liquid photoresist. 1 1. A method for fabricating an electroplated metal layer of an electrical connection pad of a semiconductor packaging substrate, the steps include: providing a packaging substrate having at least one surface having a plurality of electrical connection pads, and covering the surface of the substrate with a conductive film; A photoresist layer is formed on the conductive film, and the photoresist layer is formed with a plurality of openings to expose the conductive film on the surface of the electrical connection pad; the conductive film not covered by the photoresist layer is removed to make the electrical connection The pad can be exposed in the opening of the photoresist layer; 16975.ptd Page 21 571372, VI. Patent application scope • Plating the package substrate so that the electrical connection pads are exposed. The surface is plated with a metal layer; remove the photoresist layer and the conductive film covered by it ' And forming a solder resist layer on the surface of the package substrate, and making the solder resist layer have a plurality of openings to expose the electrical connection pads of the electroplated metal layer. • 1 2. For the method for manufacturing a semiconductor package substrate electrical connection pad _ electroplated metal layer according to item 11 of the scope of patent application, wherein the solder resist layer can be a green paint 0 1 3. As for the scope of patent application 1 1 The manufacturing method of the electrical connection pad and electroplated metal layer of the semiconductor package substrate according to the item, wherein the hole diameter of the solder resist layer can be larger than the size of the electrical connection pad. 14. The manufacturing method of the electroplated metal layer of the electrical connection pad of the semiconductor package substrate according to item 11 of the scope of patent application, wherein the hole diameter of the solder resist layer can be smaller than the size of the electrical connection pad. .1 5. An electroplated metal layer of an electrical connection pad of a semiconductor package substrate. Mainly, a plurality of electrical connection pads are formed on at least one surface of the package substrate. The plurality of electrical connection pads are plated with a metal layer and the package substrate. The surface is covered with a layer of anti-frying layer. The anti-frying layer has a plurality of openings to expose the electrical connection pads with a metal layer. At least one of the electrical connection pads is not in communication with any electroplated wire. 16. The electroplated metal layer of the electrical connection pad of the semiconductor package substrate according to item 15 of the scope of the patent application, wherein the hole diameter of the solder resist layer may be larger than the size of the electrical connection pad. 16975.ptd Page 22 571372 VI. Application for patent scope 17. For example, if the semiconductor package substrate electrical connection pad electroplating metal layer of the patent application No. 15 is applied, the hole diameter of the solder resist layer can be smaller than the electrical connection. The size of the pad. 18. The electroplated metal layer of the electrical connection pad of the semiconductor package substrate according to item 15 of the scope of patent application, wherein the electrical connection pad may be a bump pad. 19. The electroplated metal layer of the electrical connection pad of the semiconductor package substrate according to item 15 of the scope of patent application, wherein the electrical connection pad may be a solder ball pad. 20. Electrical connection pads for semiconductor package substrates such as the 15th in the scope of patent application Electroplated metal layer, wherein the electroplated metal layer may be a metal of the group consisting of gold, metal, metal, silver, tin, nickel / Ιε, chromium / titanium, metal / gold, 4ε / gold, or metal / Is / gold Formed. Page 23