CN111755393A - Substrate-less semiconductor package structure and method for fabricating the same - Google Patents

Substrate-less semiconductor package structure and method for fabricating the same Download PDF

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Publication number
CN111755393A
CN111755393A CN201910266106.9A CN201910266106A CN111755393A CN 111755393 A CN111755393 A CN 111755393A CN 201910266106 A CN201910266106 A CN 201910266106A CN 111755393 A CN111755393 A CN 111755393A
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China
Prior art keywords
metal
insulating
pads
insulating sealing
semiconductor package
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CN201910266106.9A
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Chinese (zh)
Inventor
陈裕纬
徐宏欣
蓝源富
柯志明
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Powertech Technology Inc
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Powertech Technology Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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    • H01L2224/023—Redistribution layers [RDL] for bonding areas
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/214—Connecting portions
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Abstract

The invention is a non-base plate semiconductor package structure and its preparation method, mainly wrap a chip with an insulating sealing colloid containing metal salt, when using laser to irradiate the top surface of the insulating sealing colloid and aim at the metal joint position of the chip, namely every metal joint can be a laser barrier layer, form multiple openings on the insulating sealing colloid, make every metal joint expose, and the laser irradiates on the top surface of the insulating sealing colloid, form a circuit pattern; then, in the chemical plating step, forming metal columns in the openings, forming circuits on the circuit patterns, and forming a plurality of external pads electrically connected with the metal columns and the circuits; therefore, the semiconductor packaging structure of the invention can be electrically connected with other electronic elements or circuit boards through the external pads without using a substrate.

Description

Substrate-less semiconductor package structure and method for fabricating the same
Technical Field
The present invention relates to a substrate-less semiconductor package and a method for fabricating the same, and more particularly, to a substrate-less semiconductor package and a method for fabricating the same that reduce delamination of an encapsulant.
Background
In a general semiconductor package structure, a chip is usually disposed and electrically connected to a substrate, and finally an encapsulant is formed on the substrate to encapsulate the chip to complete a semiconductor package structure.
In view of the overall cost of the semiconductor package structure, the cost of the substrate accounts for a large proportion of the cost of the semiconductor package structure, so that a large part of the development of the semiconductor package technology is advancing the substrate technology, and considerable package cost and technology development cost can be saved if the substrate can be saved.
Disclosure of Invention
In view of the high cost of the substrate used or developed in the semiconductor package structure, the main object of the present invention is to provide a substrate-less semiconductor package structure and a method for fabricating the same.
The main technical means to achieve the above object is to make the substrate-less semiconductor package structure include:
a chip, including an active surface and a bottom surface opposite to the active surface; wherein the active surface has a plurality of metal contacts;
an insulating encapsulant containing metal salts and covering the chip; the bottom surface of the insulating sealing colloid is flush with the bottom surface of the chip, and a plurality of openings and a first circuit pattern are formed on the top surface of the insulating sealing colloid corresponding to a plurality of metal contacts of the chip;
a plurality of first metal columns which are respectively formed in the corresponding openings and are connected with the corresponding metal contacts;
a plurality of first lines formed on the first line patterns and connected to the corresponding first metal posts; and
the first external pads are electrically connected to the first metal posts and the first circuits.
In one embodiment, the insulating sealing compound includes a plurality of through holes, each through hole penetrates through the top surface and the bottom surface of the insulating sealing compound, and a second metal pillar is formed in each through hole.
In one embodiment, the substrate-less semiconductor package structure further comprises:
a protective layer covering the top surface of the insulating sealing colloid and comprising a plurality of metal pads, wherein the plurality of metal pads are correspondingly connected with the first circuit and the first metal column, and the parts of the plurality of metal pads are respectively connected with the corresponding first external pads; and
and the plurality of second external connecting pads are respectively connected to the second metal columns on the bottom surface of the insulating sealing colloid.
In one embodiment, a second circuit pattern is formed on the bottom surface of the insulating encapsulant, and a plurality of second circuits are formed on the second circuit pattern;
the parts of the second metal columns and the parts of the second circuits which are positioned on the bottom surface of the insulating sealing colloid are further respectively connected with a second external connecting pad; and the top surface of the insulating sealing colloid is further covered with a protective layer, the protective layer comprises a plurality of metal pads, the metal pads are correspondingly connected with the first circuit and the first metal column, and each metal pad is connected with the corresponding first external pad.
As can be seen from the above description, the active surface of the chip is mainly covered by the insulating encapsulant containing metal salts, when the top surface of the insulating encapsulant corresponding to the metal contacts of the chip is irradiated with laser, each metal contact can be used as a laser blocking layer, a plurality of openings are formed on the insulating encapsulant to expose each metal contact, and the laser is irradiated on the top surface of the insulating encapsulant to form a first circuit pattern; forming first lines on the first line patterns, wherein the first lines are electrically connected with the first metal posts in the corresponding openings and are provided with first external connection pads; therefore, the semiconductor packaging structure of the invention can be electrically connected with other electronic elements or circuit boards through the external pads on the circuits without using a substrate.
The main technical means for achieving the above purpose is to make the manufacturing method of the semiconductor packaging structure include the following steps:
(a) preparing a temporary carrier plate;
(b) adhering a back surface of a chip to the temporary carrier plate;
(c) forming an insulating sealing colloid on the temporary carrier plate and coating the chip; wherein the insulating sealing colloid contains metal salt;
(d) removing the temporary carrier plate, and irradiating a top surface of the insulating sealing colloid by laser to form a plurality of openings and a first circuit pattern; wherein each opening is aligned with a corresponding metal contact on an active surface of the chip, the metal contact is exposed, and a bottom surface of the insulating sealing colloid is flush with the back surface of the chip;
(e) chemically plating a plurality of the openings and the first circuit patterns, forming a first metal column on each opening, and forming a plurality of first circuits on the first circuit patterns; and
(f) and electrically connecting a plurality of first external pads to the plurality of first metal posts and the plurality of first circuits on the top surface of the insulating sealing colloid.
In one embodiment:
further irradiating the top surface of the insulating sealant with laser in the step (d) to form a through hole penetrating the top surface and the bottom surface of the insulating sealant; and
in step (e), a second metal pillar is formed in each of the through holes.
In one embodiment, the method for fabricating a substrate-less semiconductor package further comprises:
(g) and forming a plurality of second external connecting pads on a plurality of second metal columns on the bottom surface of the insulating sealing colloid.
In one embodiment:
further irradiating the bottom surface of the insulating encapsulant with laser in step (d) to form a second circuit pattern; and
in the step (e), a plurality of second lines are formed on the second line pattern.
In one embodiment, the method for fabricating a substrate-less semiconductor package further comprises:
(g) and forming a plurality of second external connecting pads on a plurality of second metal columns and a plurality of second circuits on the bottom surface of the insulating sealing colloid.
In one embodiment:
after the step (e), further forming a protective layer on the top surface of the insulating sealing colloid, forming a plurality of pad openings on the protective layer to expose parts of the metal posts and parts of the circuits, and forming metal pads in the pad openings; and
in step (f), a plurality of first external pads are formed on the plurality of metal pads.
As can be seen from the above description, the active surface of the chip is mainly covered by the insulating encapsulant containing metal salts, when the top surface of the insulating encapsulant corresponding to the metal contacts of the chip is irradiated with laser, each metal contact can be used as a laser blocking layer, a plurality of openings are formed on the insulating encapsulant to expose each metal contact, and the laser is irradiated on the top surface of the insulating encapsulant to form a first circuit pattern; forming first lines on the first line patterns, wherein the first lines are electrically connected with the first metal posts in the corresponding openings and are provided with first external connection pads; therefore, the semiconductor packaging structure of the invention can be electrically connected with other electronic elements or circuit boards through the external pads on the circuits without using a substrate.
Drawings
Fig. 1 is a cross-sectional view of a semiconductor package according to a first embodiment of the present invention.
Fig. 2 is a cross-sectional view of a semiconductor package structure according to a second embodiment of the present invention.
Fig. 3 is a cross-sectional view of a semiconductor package according to a third embodiment of the present invention.
Fig. 4A to 4J are cross-sectional views of different steps in a first semiconductor package fabrication method according to the present invention.
Fig. 5A to 5G are cross-sectional views illustrating different steps in a second method for fabricating a semiconductor package structure according to the present invention.
Wherein, the reference numbers:
1. 1a, 1b semiconductor package structure
10 chip
11 active surface
111 metal contact
12 bottom surface
20. 20a, 20b insulating sealing colloid
200 metal particles
21 bottom surface
211 second line pattern
22 top surface
221 opening
222 line pattern
223 through hole
23 protective layer
230 pad opening
231 metal pad
30 metal column
31 second metal column
40 line
41 second line
50 external connection pad
51 second external pad
60 external chip
61 external chip
70 temporary carrier plate
71 adhesive layer
Detailed Description
The present invention provides a substrate-less semiconductor package and a method for fabricating the same, and a plurality of embodiments are provided below to explain the technical contents of the present invention in detail with reference to the drawings.
Referring to fig. 1, a semiconductor package structure 1 according to a first embodiment of the present invention includes a chip 10, an insulating encapsulant 20, a plurality of metal pillars 30, a plurality of wires 40, and a plurality of external pads 50.
The chip 10 includes an active surface 11 and a bottom surface 12 opposite to the active surface 11; wherein the active surface 11 has a plurality of metal contacts 111.
The insulating encapsulant 20 includes metal salts and encapsulates the chip 10, and the bottom surface 21 of the insulating encapsulant 20 is flush with the bottom surface 12 of the chip 10, and the top surface 22 thereof forms a plurality of openings 221 and a circuit pattern 222 corresponding to the plurality of metal contacts 111 of the chip 10; in the embodiment, the insulating encapsulant 20 is a resin containing insulating metal salts and insulating metal oxides, and after laser sintering activation, reduced metal particles can be exposed, and the metal seed layer can be used for subsequent plating to form a conductive wire plating layer, so that the insulating encapsulant layer used in the present invention is a Laser Direct Structuring (LDS) encapsulant. In the present embodiment, the top surface 22 of the insulating encapsulant 20 is irradiated with laser and aligned with the position of each metal contact 111, after laser sintering activation, a corresponding opening 221 is formed on each metal contact 111, and the top surface 22 of the insulating encapsulant 20 is also irradiated with laser (with different power adjustment), and the circuit pattern 222 is formed on the top surface 22 of the insulating encapsulant 20, that is, after laser sintering activation, reduced metal particles are exposed in each opening 221 and the circuit pattern 222.
The metal pillars 30 are formed in the corresponding openings 221 of the insulating molding compound 20, and the plurality of lines 40 are formed on the line pattern 222 and connected to the corresponding metal pillars 30. In the present embodiment, since the metal particles are exposed in each of the openings 221 and the circuit pattern 222, the metal pillars 30 can be formed in the openings 221 and the circuit 40 can be formed on the circuit pattern 222 in an electroless plating process. In the present embodiment, the metal pillars 30 and the circuit lines 40 are further covered with a passivation layer 23, i.e., the metal pads 231 are formed on the metal pillars 30 and the circuit lines 40 that are not covered by the passivation layer 23.
The external pads 50 are electrically connected to the wires 40 and/or the metal posts 30 for electrically connecting with external electronic components or circuit boards. In the embodiment, the external pads 50 are solder balls or metal contacts, and the external pads 50 are formed on the corresponding metal pads 231 to electrically connect with the circuits 40 and/or the metal posts 30.
As can be seen from the above description, the semiconductor package 1 of the present invention does not use a substrate, and the insulating encapsulant 20 is directly used in combination with laser irradiation and chemical plating to directly form the circuit 40 and the external pad 50 electrically connected to the metal contact 111 of the encapsulated chip 10 on the insulating encapsulant 20, so as to form a complete semiconductor package 1.
Referring to fig. 2, a semiconductor package structure 1a according to a second embodiment of the present invention includes a chip 10, an insulating encapsulant 20a, a plurality of first metal pillars 30, a plurality of second metal pillars 31, a plurality of first wires 40, a plurality of first external pads 50, and a plurality of second external pads 51.
The chip 10 includes an active surface 11 and a bottom surface 12 opposite to the active surface 11; wherein the active surface 11 has a plurality of metal contacts 111.
The insulating sealant 20a is substantially the same as the insulating sealant 20 of the first embodiment shown in fig. 1, but the embodiment further includes a plurality of through holes 223, and each of the through holes 223 penetrates through the top surface 22 and the bottom surface 21 of the insulating sealant 20 a. In this embodiment, the insulating encapsulant 20a is irradiated with laser (with different power adjusted) to form the through holes 223 in the insulating encapsulant 20a, and exposed metal particles are formed in each through hole 223.
The first metal pillars 30, the second metal pillars 31, and the circuit patterns 40 are formed in the openings 221, the through holes 223, and the circuit patterns 222, respectively, by an electroless plating process. In the present embodiment, the portions of the first and second metal pillars 30 and 31 and the portions of the circuits 40 on the top surface 22 of the insulating encapsulant 20a are further covered with a passivation layer 23, and the metal pads 231 are formed on the first and second metal pillars 30 and 31 and the circuits 40, which are not covered by the passivation layer 23.
The first external pads 50 are electrically connected to the wires 40 and/or the first and second metal posts 30, 31 for electrically connecting with external electronic components or circuit boards. In the present embodiment, the first external pads 50 are solder balls or metal contacts, and the external pads 50 are formed on the corresponding metal pads 231, as shown in fig. 2, the first external pads 50 can be soldered to an external chip 60, and the other metal pads 231 can be soldered to an external chip 61 of a different package structure.
The second external pads 51 are formed on the corresponding second metal posts 31 on the bottom surface 21 of the insulating encapsulant 20 a. In the present embodiment, the second external pads 50 are solder balls, and can also be metal contacts for electrically connecting with external electronic devices or circuit boards.
Referring to fig. 3, a third embodiment of a semiconductor package structure 1b according to the present invention is shown, and the structure thereof is substantially the same as the structure of the semiconductor package structure 1a shown in fig. 2, but the bottom surface 21 of the insulating encapsulant 20b is further formed with a second circuit pattern 211 by laser, and a plurality of second circuits 41 are formed on the second circuit pattern 211 by chemical plating, and a plurality of second external pads 51 are formed on a portion of the second circuits 41 and the second metal posts 31 on the bottom surface 21 of the insulating encapsulant 20b for soldering an external chip 60, and another external chip 61 is also directly soldered on the second circuits 41 and the second metal posts 31 on the bottom surface 21 of the insulating encapsulant 20 b. The first external pads 50 are electrically connected to the wires 40 and/or the first and second metal posts 30, 31 formed on the top surface 22 of the insulating encapsulant 20b for electrically connecting to external electronic components or circuit boards; specifically, the first external connection pad 50 is formed on the metal pad 231.
Referring to fig. 4A to 4J, a method for packaging the semiconductor package structure 1 of fig. 1 is shown, first referring to fig. 4A, a temporary carrier 70 is prepared, and an adhesive layer 71 is formed on the carrier 70.
As shown in fig. 4B, a chip 10 is disposed on the adhesive layer 70 to be adhered to the temporary carrier 70; in the present embodiment, the chip 10 is disposed on the adhesive layer 70 with the back surface 12, and the active surface 11 and the plurality of metal contacts 111 on the active surface 11 face the opposite direction (face up) to the adhesive layer 71.
As shown in fig. 4C, an insulating encapsulant 20 is formed on the adhesive layer 71 of the temporary carrier 70 and covers the chip 10; wherein the insulating encapsulant 20 contains metal salts. In the embodiment, the insulating encapsulant 20 is a resin containing insulating metal salts and insulating metal oxides, and after laser sintering activation, reduced metal particles can be exposed, and the metal seed layer can be used for subsequent plating to form a conductive wire plating layer.
As shown in fig. 4D, the temporary carrier 70 and the adhesive layer 71 thereon are removed, such that the bottom surface 12 of the chip and the bottom surface 21 of the insulating encapsulant 20 are exposed, and the bottom surface 12 of the chip 10 is flush with the bottom surface 21 of the insulating encapsulant 20.
As shown in fig. 4E, the top surface 22 of the insulating encapsulant 20 is irradiated with laser and aligned with the metal contacts 111 to form a plurality of openings 221, exposing the metal contacts 111; as shown in fig. 4F, a circuit pattern 222 is formed on the top surface of the insulating molding compound 20 by adjusting the laser power. Since each of the openings 221 and the line pattern 222 is activated by laser sintering, the metal particles 200 are exposed.
As shown in fig. 4G, the openings 221 and the circuit patterns 222 are chemically plated, a metal pillar 30 is formed in each opening 221, and a plurality of circuits 40 are formed on the circuit patterns 222; wherein the lines 40 are connected to the metal posts 30.
As shown in fig. 4H, a passivation layer 23 is formed on the top surface 22 of the insulating molding compound 20 to cover the metal pillars 30 and the circuits 40 exposed on the top surface 22 of the insulating molding compound 20.
As shown in fig. 4I, a pad opening 230 is formed on the passivation layer 23, so that portions of the metal pillars 30 and portions of the circuits 40 are exposed; as shown in fig. 4J, a metal pad 231 is formed in each pad opening 230, and an external pad 50 is formed on part or all of the metal pads 321; thus, the semiconductor package 1 shown in fig. 1 is constructed.
Referring to fig. 5A to 5G, which are illustrations of a packaging method of the semiconductor package structure 1a of fig. 2, the first steps of the packaging method of the present embodiment are the same as those of fig. 4A to 4C, and thus are not repeated herein. Referring to fig. 5A, the chip 10 is covered by the insulating encapsulant 20 a.
As shown in fig. 5B, laser is irradiated onto the top surface 22 of the insulating encapsulant 20a and aligned with the metal contacts 111 to form a plurality of openings 221, so as to expose the metal contacts 111, and the top surface 22 of the insulating encapsulant 20a is irradiated to form through holes 223 penetrating through the top surface 22 and the bottom surface 21 of the insulating encapsulant 20 a; wherein the metal particles 200 are exposed on the sidewall of each opening 221 and the sidewall of each through hole 223. In the present embodiment, since the laser irradiates the top surface 22 of the insulating encapsulant 20a, the apertures of the openings 221 and the through holes 223 are wider at the top and narrower at the bottom.
As shown in fig. 5C, adjusting the laser power to form a circuit pattern 222 on the top surface 22 of the insulating encapsulant 20a, wherein the metal particles 200 are exposed due to the activation of the circuit pattern 222 by laser sintering; in addition, as shown in fig. 3, another circuit pattern (the second circuit pattern 211) may be further formed on the bottom surface 21 of the insulating molding compound 20b in this step.
As shown in fig. 5D, the openings 221, the through holes 223 and the circuit patterns 222 are chemically plated, a first metal pillar 30 is formed in each opening 221, a second metal pillar 31 is formed in each through hole 223, and a plurality of circuits 40 are formed on the circuit patterns 222; wherein the lines 40 are connected to the first and second metal pillars 30, 31. Similarly, as shown in fig. 3, a plurality of second lines 41 may be formed in the second line pattern 211 in this step.
As shown in fig. 5E, a passivation layer 23 is formed on the top surface 22 of the insulating molding compound 20a to cover the first and second metal pillars 30, 31 and the circuits 40 exposed on the top surface 22 of the insulating molding compound 20 a.
As shown in fig. 5F, a pad opening 230 is formed on the passivation layer 23 to expose a portion of the first and second metal pillars 30 and 31 and the circuit 40; as shown in fig. 5G, a metal pad 231 is formed in each pad opening 230, a first external pad 50 (e.g., a solder ball) is formed on a portion of the metal pad 231, and a second external pad 51 (e.g., a solder ball) is formed on the second metal pillar 31 exposed on the bottom surface 21 of the insulating encapsulant 20 a; thus, the semiconductor package 1a shown in fig. 2 is configured to be soldered to external chips 60 and 61 of different package types through the metal pads 231 and the first external pads 50. Alternatively, as shown in fig. 3, the second metal pillar 31, the second circuit 41 and the second external pad 51 exposed on the bottom surface 21 of the insulating encapsulant 20a are soldered to external chips 60 and 61 of different packaging types.
In summary, the active surface of the chip is mainly coated with the insulating encapsulant containing metal salts, and when the top surface of the insulating encapsulant corresponding to the metal contact position of the chip is irradiated with laser, each metal contact can be a laser blocking layer, a plurality of openings are formed on the insulating encapsulant to expose each metal contact, and the laser is irradiated on the top surface of the insulating encapsulant layer to form a circuit pattern; forming circuits on the circuit pattern, wherein the circuits are electrically connected with the metal posts in the corresponding openings and are provided with external pads; therefore, the semiconductor packaging structure of the invention can be electrically connected with other electronic elements or circuit boards through the external pads on the circuits without using a substrate.
The present invention is capable of other embodiments, and various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (10)

1. A substrate-less semiconductor package structure, comprising:
a chip, including an active surface and a bottom surface opposite to the active surface; wherein the active surface has a plurality of metal contacts;
an insulating encapsulant containing metal salts and covering the chip; the bottom surface of the insulating sealing colloid is flush with the bottom surface of the chip, and a plurality of openings and a first circuit pattern are formed on the top surface of the insulating sealing colloid corresponding to a plurality of metal contacts of the chip;
a plurality of first metal columns which are respectively formed in the corresponding openings and are connected with the corresponding metal contacts;
a plurality of first lines formed on the first line patterns and connected to the corresponding first metal posts; and
the first external pads are electrically connected to the first metal posts and the first circuits.
2. The substrate-less semiconductor package according to claim 1, wherein the insulating encapsulant comprises a plurality of through holes, each through hole penetrating through a top surface and a bottom surface of the insulating encapsulant, and a second metal pillar is formed in each through hole.
3. The substrate-less semiconductor package structure of claim 2, further comprising:
a protective layer covering the top surface of the insulating sealing colloid and comprising a plurality of metal pads, wherein the plurality of metal pads are correspondingly connected with the first circuit and the first metal column, and the parts of the plurality of metal pads are respectively connected with the corresponding first external pads; and
and the plurality of second external connecting pads are respectively connected to the second metal columns on the bottom surface of the insulating sealing colloid.
4. The substrate-less semiconductor package structure of claim 2, wherein:
a second circuit pattern is formed on the bottom surface of the insulating sealing colloid, and a plurality of second circuits are formed on the second circuit pattern;
the parts of the second metal columns and the parts of the second circuits which are positioned on the bottom surface of the insulating sealing colloid are further respectively connected with a second external connecting pad; and the top surface of the insulating sealing colloid is further covered with a protective layer, the protective layer comprises a plurality of metal pads, the metal pads are correspondingly connected with the first circuit and the first metal column, and each metal pad is connected with the corresponding first external pad.
5. A method for manufacturing a substrate-free semiconductor packaging structure is characterized by comprising the following steps:
(a) preparing a temporary carrier plate;
(b) adhering a back surface of a chip to the temporary carrier plate;
(c) forming an insulating sealing colloid on the temporary carrier plate and coating the chip; wherein the insulating sealing colloid contains metal salt;
(d) removing the temporary carrier plate, and irradiating a top surface of the insulating sealing colloid by laser to form a plurality of openings and a first circuit pattern; wherein each opening is aligned with a corresponding metal contact on an active surface of the chip, the metal contact is exposed, and a bottom surface of the insulating sealing colloid is flush with the back surface of the chip;
(e) chemically plating a plurality of the openings and the first circuit patterns, forming a first metal column on each opening, and forming a plurality of first circuits on the first circuit patterns; and
(f) and electrically connecting a plurality of first external pads to the plurality of first metal posts and the plurality of first circuits on the top surface of the insulating sealant.
6. The method of manufacturing a substrate-less semiconductor package according to claim 5, wherein:
further irradiating the top surface of the insulating sealant with laser in the step (d) to form a through hole penetrating the top surface and the bottom surface of the insulating sealant; and
in step (e), a second metal pillar is formed in each of the through holes.
7. The method of fabricating the substrate-less semiconductor package structure of claim 6, further comprising:
(g) and forming a plurality of second external connecting pads on a plurality of second metal columns on the bottom surface of the insulating sealing colloid.
8. The method of manufacturing a substrate-less semiconductor package according to claim 6, wherein:
further irradiating the bottom surface of the insulating encapsulant with laser in step (d) to form a second circuit pattern; and
in the step (e), a plurality of second lines are formed on the second line pattern.
9. The method of fabricating the substrate-less semiconductor package according to claim 8, further comprising:
(g) and forming a plurality of second external connecting pads on a plurality of second metal columns and a plurality of second circuits on the bottom surface of the insulating sealing colloid.
10. The method of fabricating the substrate-less semiconductor package structure of any one of claims 5 to 9, wherein:
after the step (e), further forming a protective layer on the top surface of the insulating sealing colloid, forming a plurality of pad openings on the protective layer to expose parts of the metal posts and parts of the circuits, and forming metal pads in the pad openings; and
in step (f), a plurality of first external pads are formed on the plurality of metal pads.
CN201910266106.9A 2019-03-26 2019-04-03 Substrate-less semiconductor package structure and method for fabricating the same Pending CN111755393A (en)

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