TWI473189B - Method for wafer-level testing diced multi-dice stacked packages - Google Patents

Description

Wafer-level test method for single-chip stacked packages

The present invention relates to the fabrication of semiconductor devices, and more particularly to a wafer level testing method for a single-die stacked package.

Multi-wafer stacked package is a new high-density packaging technology in which a plurality of stacked chips are packaged in a package member. The current practice is to stack the wafers one by one on a substrate and then package and test them. However, the presence of the substrate increases the surface bonding area and thickness of the package structure.

In order to reduce the size of the multi-wafer stack package structure, some people try to omit the substrate, and perform multiple wafer bonding at the wafer level, and after wafer dicing, a substrate-free die stack (or a crystal grain cube) is formed. Dice cube), such as those disclosed in U.S. Patent Application Publication No. 2011/0074017. However, in a wafer, defective wafers are generated and the position is not fixed, and the wafer alignment of the wafers causes the defect rate of the substrate-free die stack to be greatly improved. In addition, when the substrate is omitted, the distance between the external conductive electrode and the test electrode of the multi-wafer stacked package structure will be significantly reduced, and the original package tester will not be used if the original distance of several hundred micrometers is reduced to less than one hundred micrometers. The test pin (pogo pin) in the station was tested. At present, there are two methods. First, after testing the board to be tested, the module test is performed. Therefore, it is impossible to determine in advance whether the joint between the stacked wafers is good. Second, the substrate stack without the substrate is separated. Combined with a transfer substrate (usually made of 矽) with a fan-out circuit and a fan-out terminal, and then loaded into the package test machine for testing, not only The process is complicated and the test cost is increased.

In order to solve the above problems, the main object of the present invention is a wafer level test method for a single-die stack package, which can achieve a micro-gap probe test for a single-die stack package, especially Integrated in the TSV packaging process.

The second object of the present invention is a wafer level test method for a single-die stack package, which can perform the wafer level test before the upper board, and the advantages and disadvantages of the single-die stack package can be achieved in a low cost manner. Prevent misuse of the single-die stack package.

The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The present invention discloses a wafer level test method for a single-die stack package. First, a plurality of die-stack packages are provided, each die-stack package comprising a plurality of upper and lower stacked dies, and having a front surface, a back surface, and a plurality of test electrodes on the front surface; The die array arrays and fixes the die stack packages on a light transmissive wafer carrier having a plurality of component set regions defined by a specific positioning pattern (eg, by an X axis) An array or a central, corner or peripheral positioning mark planned by the marking line and the Y-axis marking line) and a photosensitive adhesive layer adhered to the back surface of the die-stacked package and The die stacking package is located in the component setting regions, and may not cover the X-axis marking lines and the Y-axis marking lines, or may not cover the corners or the peripheral positioning marks; afterwards, the loading has carried the die stacks The light transmissive wafer carrier of the package is in a In the wafer testing machine; then, using the plurality of wafer testing probes of the wafer testing machine to probe the test electrodes to electrically test the die-stack packages; finally, transmitting the transmissive crystal The circular carrier light illuminates the photosensitive adhesive layer for picking up the die-stack packages from the light-transmissive wafer carrier.

The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.

In the aforementioned wafer level test method, the light transmissive wafer carrier can be a glass disk.

In the foregoing wafer level testing method, the step of providing the die stack packages may include the steps of: setting a plurality of substrateless die stacks on an adhesive tape, and each substrateless die stacking The system is composed of the plurality of die stacks, and a die stacking gap is formed between each of the upper and lower adjacent crystal grains, wherein the test electrodes are relatively far away from the adhesive tape; and a filling colloid is formed thereon. Adhesive tape is applied to fill the die stack gaps.

In the foregoing wafer level testing method, the step of providing the die-stack packages may further include: removing a glue step after forming the filling gel to remove the filling gel beyond the non-substrate The overflow portion of the crystal grain stack.

In the wafer level test method described above, after the step of removing the glue, the filling gel can still cover a plurality of sides of the grains.

In the foregoing wafer level test method, the glue filling system may be a positive photoresist type, and the de-glue step is to enter the glue-filled portion of the filling gel. Line exposure development.

In the foregoing wafer level testing method, before the step of disposing the substrateless die stack on the adhesive tape, the adhesive tape may be preset in one of the openings of the long strip adhesive carrier. The simulation is a substrate strip.

In the foregoing wafer level test method, a plurality of germanium vias may be disposed in each of the die, and the die stack packages may be provided with a plurality of interconnect bumps in the die stack gaps. It electrically conducts the perforations of the crucible.

In the wafer level testing method described above, each of the die stack packages may have a plurality of locations on the front side of the bumps.

In the foregoing wafer level testing method, the positioning patterns may include a plurality of X-axis marking lines and a plurality of Y-axis marking lines, and are not covered by the die-stack packages.

In the foregoing wafer level testing method, the X-axis marking lines and the Y-axis marking lines may extend to the periphery of the light-transmitting pseudo-wafer carrier.

In the wafer level test method described above, the transmissive wafer carrier may have a wafer identification code formed on one of the surface edges outside the component placement regions.

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not actual The number, shape, and size of the implementation are scaled, and some ratios of dimensions to other related dimensions are either exaggerated or simplified to provide a clearer description. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated.

In accordance with a preferred embodiment of the present invention, a wafer level test method for a single-die stack package is illustrated in cross-section of the components of steps 1A through 1D. According to the wafer level test method, a plurality of die-stack packages 100 are first provided, and FIGS. 2A to 2E are schematic cross-sectional views of elements in a sub-step of providing a plurality of die-stack packages 100.

As shown in FIG. 1A, a plurality of die-stack packages 100 are provided which have been diced to be singulated, preferably in a substrateless form. Each of the die-stacked packages 100 includes a plurality of die 110 stacked on top of each other. The die 110 can be formed by singulating the same wafer. Generally, the system of the die 110 is a semiconductor material. The active surface of the die 110 has been fabricated with the required integrated circuit components, and its function can be, for example, a body, a logic circuit, or a microprocessor circuit, and is generally a non-volatile document. Moreover, each of the die-stack packages 100 has a front surface 102, a back surface 103, and a plurality of test electrodes 130 on the front surface 102. The front surface 102 is an external surface joint surface. The opposite surface of the front side 102. In this embodiment, the front surface 102 can be formed by an active surface of one of the crystal grains, and the back surface 103 can be formed by an inactive surface of one of the crystal grains. The test electrodes 130 are connected to the integrated circuit components of the die 110. Use an electrode. In this embodiment, the test electrodes 130 are wafer pads or may be bumps. More specifically, each of the die 110 may be provided with a plurality of through silicon vias 111 (TSV), and the die stack gaps 120 between the upper and lower stacked die 110 may be provided with plural numbers. The interconnecting bumps 140 electrically conduct the turns of the turns 111. In this embodiment, each of the die-stack packages 100 can have a plurality of locations on the front surface 102, such as copper pillars, solder balls or metal bumps, and the interconnect bumps. The block 140 is substantially identical in position, material and size on the die, and is electrically connected to the test electrodes 130 by using a reconfiguration circuit layer (not shown). In addition, the distance between the test electrodes 130 is between 60 and 100 micrometers. The wafer level test method of the present invention is particularly applied to the case where the distance between the test electrodes 130 is less than 100 micrometers, and the external bumps 141 are The spacing system may be equal to or greater than the distance between the test electrodes 130. In a variant embodiment, the external bumps 141 can be omitted, and the test electrodes 130130 are directly used as the external electrodes of the die stack package 100. The fabrication of the die-stack packages 100 can utilize existing semiconductor packaging devices.

As shown in FIGS. 1A and 4, the die-stack packages 100 are arranged and fixed on a transmissive wafer carrier 210 according to the die array. As used herein, "die array" refers to the arrangement of the grains in a wafer such that the die-stack packages 100 are arranged as if they were in the same wafer. The light transmissive wafer carrier 210 is molded into a wafer, such as an 8-inch, 12-inch or 16-inch wafer, in size and can be loaded. Loaded in a wafer tester. In this embodiment, the translucent wafer carrier 210 can be a glass disk, so the transmissive wafer carrier 210 has good light transmittance, is sufficiently rigid, and has a coefficient of expansion close to that of the semiconductor material. . In addition, the surface of the light-transmissive wafer carrier 210 has a photosensitive adhesive layer 214. The photosensitive adhesive layer 214 is used to adhere the back surface 103 of the die-stack package 100. The photosensitive adhesive layer 214 The characteristic is that there is adhesive force before the light is irradiated, and the photosensitive adhesive layer 214 loses the adhesive force after irradiating the light of a specific wavelength, and removes the photosensitive photosensitive adhesive layer, and repeatedly applies the photosensitive adhesive layer before the unilluminated, In the repeated operation of adhering the workpiece and illuminating, it is indicated that the main system of the translucent pseudo-wafer carrier 210 can be recycled. Further, as shown in FIG. 3C, the translucent wafer carrier 210 has a plurality of component setting regions 213 defined by a specific positioning pattern. In this embodiment, the positioning pattern includes a plurality of X-axis marking lines 211 and a plurality of Y-axis marking lines 212, which are perpendicular to each other to plan a maximum area of the component setting regions 213. The adhesion of the photosensitive adhesive layer 214 should be such that the die-stacked packages 100 are located in the component mounting regions 213, and the X-axis markings 211 and the Y-axis markings 212 are not covered. Good positioning identification (as shown in Figure 4). Preferably, the X-axis markings 211 and the Y-axis markings 212 extend to the periphery of the transparent wafer carrier 210 to simulate a wafer cutting line, and the light transmittance is easy to locate. Wafer carrier 210. The X-axis reticle 211 and the Y-axis reticle 212 are preferably semi-etched linear grooves for illuminating light; or the X-axis reticle 211 and the Y-axis reticle 212 can also It is a linear ink line.

Thereafter, as shown in FIG. 1B, the translucent pseudo-wafer carrier 210 on which the die-stack packages 100 are mounted is loaded in a wafer testing machine 220. The translucent wafer carrier 210 can also be adhered to a wafer dicing tape (not shown) supported by a conventional wafer support ring, and the translucent wafer carrier 210 is placed on a conventional wafer support ring. In the central opening, the die-stacked package 100 can completely simulate the die cut by a wafer and fixed on the wafer cutting tape, so that the existing wafer testing machine can be used without barriers. The loading mechanism loads into the wafer testing machine 220 and performs accurate positioning.

Then, as shown in FIG. 1C, the plurality of wafer test probes 221 of the wafer testing machine 220 are used to probe the test electrodes 130 to electrically test the die-stack packages 100. The wafer test probes 221 are mounted in a probe card 225 (probe card). As shown in FIG. 5, the wafer testing machine 220 includes a loading area 222, a transfer area 223, and a test area 224. The conventional wafer and the transparent wafer carrier 210 are available in the loading area 222. The loading and unloading can be transmitted to the test area 224 after the alignment inspection by the transfer area 223. The test area 224 is provided with the probe card 225 including the wafer test probe 221 for the wafer. The stage detects the electrodes on the surface of the wafer. Since the wafer test mimetic trays conform to the wafer size, they can be directly loaded into the loading area 222, and the wafer test probes 221 are used to probe the die stack packages in the test area 224. 100 test electrode 130, so the test cost of multi-wafer wafer level packaging is reduced, and test efficiency is improved The die-stacked package 100 does not need to be mounted on the adapter substrate provided with the fan-out circuit and the fan-out terminal to be tested to confirm the between the die 110 Whether the electrical conduction (ie, the bonding of the interconnecting bumps 140) is good. In addition, the wafer level testing method of the single-die stacking package of the present invention may also allow the classification of the die-stack packages 100 directly after being detected by the wafer testing machine 220, and pre-pick or A poor die-stack package is shaved.

Then, as shown in FIG. 1D, after the test, the translucent wafer carrier 210 is unloaded from the wafer testing machine 220 and moved into an exposure machine, and a light irradiation device 230 is disposed under the lens. The main body of the optical wafer carrier 210 is irradiated with light to the photosensitive adhesive layer 214, and the light irradiation device 230 emits light of a specific wavelength, such as UV light (ultraviolet light), which can react to the photosensitive adhesive layer 214. The photosensitive adhesive layer 214 is rendered viscous.

Finally, as shown in FIG. 1E, the die-stacked packages 100 are picked up by the light-transmissive wafer carrier 210 for sorting and packaging. Therefore, the wafer level test method of the single-die stack package of the present invention can achieve micro-gap probe test for the single-die stack package, and can be easily integrated into the TSV package process.

The wafer level test method of the present invention is further described with reference to FIGS. 2A through 2E for the detailed steps of the steps of providing the die stack packages 100 described above.

As shown in FIG. 2A, after cutting and cutting, a plurality of dies 110 are adhered to a wafer dicing tape 240, and the wafer is diced. The tape 240 is adhered to a wafer support ring (not shown). The dies 110 can be formed on the same wafer, and the dicing streets of the wafer are cut by a wafer cutting tool 241 during the dicing process to form the dies 110. After wafer level testing, good grains 110 are sorted and collected.

As shown in FIG. 2B, a plurality of substrate-free die stacks 101 are disposed on an adhesive tape 250, and each of the substrate-free die stacks 101 is composed of the plurality of die 110 stacks. Each of the adjacent die 110 is formed with a die stacking gap 120, wherein the test electrodes 130 are relatively far from the adhesive tape 250, and the interconnecting bumps 140 are located in the die stacking gaps 120. The turns 111 are electrically conductive.

As shown in FIG. 2C, a filling gel 150 is formed on the adhesive tape 250 to fill the die stack gaps 120, thereby sealing the interconnect bumps 140. The filling gel 150 may be provided by a glue applying needle 270 formed on the adhesive tape 250 and filled with the filling gel 150 under the condition that the temperature and time can produce capillary action. The granules are stacked with a gap 120, and then the filled colloid 150 is slightly solidified in a heated pre-curing manner. In addition, the filling gel 150 may be a die-fill material, a non-conductive glue (NCP) or an anisotropic conductive paste (ACP), in addition to the underfill. For the specific implementation technique of the above-mentioned sub-step die stacking and gluing, reference may be made to the descriptions of Figures 8A and 8B of U.S. Patent Publication No. 2011/0057327; or, in this embodiment, as shown in FIG. 3, in the above Set these none Before the step of the substrate die stack 101 on the adhesive tape 250, the adhesive tape 250 can be preliminarily disposed in one of the openings 261 of the elongated tape carrier 260, and is simulated as a substrate strip, so that both can be utilized. Some flip chip bonding machines and dispensers (or molding machines) of semiconductor packaging equipment are implemented. In addition, the tape carrier 260 can also serve as a mounting fixture for transporting the substrate-free die stack 101 into the baking furnace.

In addition, as shown in FIGS. 2D and 2E, the steps of providing the die-stack packages 100 may further include: removing the glue step 150 after forming the filling gel 150 to remove the filling gel 150. The overflow portions 151 of the substrate-free die stack 101 are not provided. Preferably, the filling colloid 150 can still cover the plurality of sides 112 of the plurality of crystal grains 110 after the step of removing the glue. One of the specific technical means for achieving this structure is that the filling colloid 150 can be a positive photoresist type, and the de-glue step is to expose and develop the overflow portion 151 of the filling colloid 150. As shown in FIG. 2D, the overflow portion 151 of the filling gel 150 can be exposed and developed by using an exposure mask 280. The mask pattern of the exposure mask 280 is slightly larger than the size of the crystal grains 110. The filling gel 150 is filled. The overflow portion 151 will be irradiated with light to cause a reaction. As shown in FIG. 2E, the developer can dissolve and remove the overflow portion 151 of the filling gel 150, and at the same time, the side faces 112 of the crystal grains 110 are still covered by the filling gel 150. After the filling paste 150 is post-cured in a heat-baking manner, the above-described die-stack packages 100 can be formed. Alternatively, another specific technical means for achieving the structure in which the side faces 112 of the die 110 are covered by the filling colloid 150 is that a laser can be utilized. The cutting tool cuts the overflow portion 151.

In addition, the fabrication of the translucent wafer carrier 210 can be referred to the figures 6A to 6C. First, as shown in FIG. 6A, the main system of the translucent pseudo-wafer carrier 210 is a blank glass disk of a size such as 12-inch wafer, and the upper and lower surfaces are clean and smooth; as shown in FIG. 6B, The positioning mask 290 is aligned on the translucent wafer carrier 210, and the X-axis markings 211 and the Y are formed on the upper surface of the translucent wafer carrier 210 by etching or deposition. Axis marking line 212 (as shown in Figure 6C). More specifically, the transmissive wafer carrier 210 may have a wafer identification code 215 for the bar code system at the edge of the upper surface or the lower surface outside the component placement regions 213. Identification, through this bar code system can track the test yield as it does for general wafer testing. In addition, the present invention is not limited to the use of the X-axis reticle 211 and the Y-axis reticle 212 to form the aforementioned alignment pattern. 7A to 7C are diagrams showing a light transmissive wafer carrier having different positioning patterns in different variant embodiments. In FIG. 7A, the positioning pattern of the light-transmitting wafer carrier 210 for identifying the component setting regions 213 includes a plurality of central positioning marks 216 located at a central point of the component setting regions 213, which may be Circular or cross-shaped; in FIG. 7B, the positioning pattern of the transmissive wafer carrier 210 for identifying the component mounting regions 213 includes a plurality of corner locating marks 217 located in the components. The angle 隅 of the setting area 213 may be a triangle or an L shape. In the 7C, the positioning pattern of the light-transmitting wafer carrier 210 for identifying the component setting areas 213 includes a plurality of peripheral positioning marks 218. ,its It is located at the periphery of the component setting areas 213 and has a window shape. When the die-stack packages are fixed in the component mounting regions, it is preferable not to cover the corner-pointing marks 217 or the peripheral positioning marks 218. The formation of the positioning patterns may also be formed by inlaying or recessing a substance different from the bulk material of the light transmissive wafer carrier 210.

Therefore, the wafer level test method of the single-die-stacked package of the present invention is compatible with the current wafer tester, and can achieve micro-gap for the single-die stack package without substrate or wafer size. The probe test does not require an electrical transfer substrate to provide a well-tested, single-die stack package that prevents misuse of the defective single-die stack package in a low cost manner.

The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made without departing from the technical scope of the present invention are still within the technical scope of the present invention.

100‧‧‧ die stack package

101‧‧‧No substrate die stack

102‧‧‧ positive

103‧‧‧Back

110‧‧‧ grain

111‧‧‧矽 piercing

112‧‧‧ side

120‧‧‧ die stacking gap

130‧‧‧Test electrode

140‧‧‧Interconnect bumps

141‧‧‧External bumps

150‧‧‧filled colloid

151‧‧‧Over the glue

210‧‧‧Transmissive wafer carrier

211‧‧‧X-axis marking

212‧‧‧Y-axis marking

213‧‧‧Component setting area

214‧‧‧Photosensitive adhesive layer

215‧‧‧ wafer identification code

216‧‧‧Central Mark

217‧‧‧ corner mark

218‧‧‧ surrounding marking

220‧‧‧Watt Testing Machine

221‧‧‧ wafer test probe

222‧‧‧ Loading area

223‧‧‧Transfer area

224‧‧‧Test area

225‧‧‧ probe card

230‧‧‧Lighting device

240‧‧‧ Wafer Cutting Tape

241‧‧‧ Wafer Cutting Tools

250‧‧‧Adhesive tape

260‧‧‧ Tape Carrier

261‧‧‧ openings

270‧‧‧Glue needle

280‧‧‧Exposure mask

290‧‧‧ Positioning mask

1A-1E FIG. 1 is a cross-sectional view showing the components of each of the main steps in a wafer level test method for a single-die stack package according to a preferred embodiment of the present invention.

2A to 2E are diagrams showing a wafer level test method for a single-die stack package according to a preferred embodiment of the present invention A schematic cross-sectional view of an element for providing a sub-step of a plurality of die-stack packages.

Figure 3 is a front elevational view showing a plurality of substrate-free die stacks mounted on a long strip of tape carrier in the wafer level test method.

Figure 4 is a front elevational view showing a plurality of die-stack packages mounted on a light-transmissive wafer carrier in the wafer level test method.

Figure 5 is a perspective view of a wafer testing machine used in the wafer level testing method in accordance with a preferred embodiment of the present invention.

6A to 6C are views showing a front view of a translucent pseudo-wafer carrier used in the wafer level test method in a manufacturing process according to a preferred embodiment of the present invention.

7A-7C are front elevational views of a light transmissive wafer carrier having different positioning patterns in accordance with a preferred embodiment of the present invention.

100‧‧‧ die stack package

102‧‧‧ positive

103‧‧‧Back

110‧‧‧ grain

111‧‧‧矽 piercing

112‧‧‧ side

120‧‧‧ die stacking gap

130‧‧‧Test electrode

140‧‧‧Interconnect bumps

141‧‧‧External bumps

150‧‧‧filled colloid

210‧‧‧Transmissive wafer carrier

212‧‧‧Y-axis marking

214‧‧‧Photosensitive adhesive layer

220‧‧‧Watt Testing Machine

221‧‧‧ wafer test probe

225‧‧‧ probe card

Claims (14)

A wafer level testing method for a single-die stack package includes: providing a plurality of die-stack packages, each die-stack package comprising a plurality of upper and lower stacked dies, and having a front side and a front side a back surface and a plurality of test electrodes on the front surface; arranging and fixing the die stack packages on a light transmissive wafer carrier according to the die array, the light transmissive wafer carrier having a plurality of a component setting region defined by a specific positioning pattern and a photosensitive adhesive layer, the photosensitive adhesive layer is adhered to the back surface of the die-stacked package, and the die-stack packages are located in the component setting regions; Loading the translucent pseudo-wafer carrier on which the die-stacked packages are mounted in a wafer testing machine; and using the plurality of wafer test probes of the wafer testing machine to probe the test electrodes to be electrically Testing the die-stack packages; and illuminating the photosensitive adhesive layer through the light-transmissive wafer carrier for picking up the die-stack packages from the light-transmissive wafer carrier; Provided above These steps of die-based stack package comprising the steps of: setting a plurality of substrate-die on a stack of adhesive tape, each of the substrate-die stacked system composed of the plurality of stacked die, And forming a die stack gap between the two adjacent upper and lower dies, wherein the test electrodes are relatively far away from the adhesive tape; and forming a filling gel on the adhesive tape to fill the dies Stack gaps. A wafer level test method for a single-die-stacked package according to the first aspect of the patent application, wherein the light-transmissive wafer carrier is a glass disk. The wafer level testing method for the single-die-stacked package according to the first aspect of the patent application, wherein the step of providing the die-stacked package further comprises: removing the glue after forming the filling gel a step of removing the filling gel beyond the overflow portion of the substrate-free substrate stack. A wafer level test method for a single-die stack package according to claim 3, wherein the fill colloid still covers a plurality of sides of the die after the step of removing the glue. A wafer level test method for a single-die stack package according to claim 3, wherein the fill system is a positive photoresist type, and the step of removing the glue is to perform the overflow portion of the filled colloid. Exposure development. A wafer level test method for a single-die-stacked package according to claim 3, wherein the adhesive tape is pre-set before the step of disposing the substrate-free die stack on the adhesive tape In a long strip of tape carrier in one of the openings, and the mold It is intended to be a substrate strip. A wafer level test method for a single-die-stacked package according to claim 1, wherein each of the crystal grains is provided with a plurality of germanium perforations, and the die-stacked packages are on the crystal grains A plurality of interconnecting bumps are disposed in the stacking gap, and the plurality of interconnecting bumps are electrically connected. A wafer level test method for a single-die-stacked package according to claim 7 of the patent application, wherein each of the die-stack packages further has a plurality of external bumps on the front surface. A wafer level test method for a single-die-stacked package according to the first aspect of the patent application, wherein the positioning patterns comprise a plurality of X-axis marks and a plurality of Y-axis marks, and are not subjected to the crystals Covered by a grain stack package. A wafer level test method for a single-die-stacked package according to claim 9 of the patent application, wherein the X-axis marks and the Y-axis marks extend to the periphery of the light-transmissive wafer carrier . A wafer level testing method for a single-die-stacked package according to the first aspect of the patent application, wherein the positioning patterns are selected from the group consisting of a central positioning mark, a corner positioning mark, and a peripheral positioning mark. one. A wafer level test method for a single-die-stacked package according to the first aspect of the patent application, wherein the light-transmissive wafer carrier has a wafer on a surface edge of the component mounting region Identification code. A wafer level testing method for a single-die stack package includes: providing a plurality of die-stack packages, each die-stack package comprising a plurality of upper and lower stacked dies, and having a front side and a front side a back surface and a plurality of test electrodes on the front surface; arranging and fixing the die stack packages on a light transmissive wafer carrier according to the die array, the light transmissive wafer carrier having a plurality of a component setting area defined by a specific positioning pattern, and a photosensitive adhesive layer, the photosensitive adhesive layer is adhered to the back surface of the die-stacked package, and the die-stacked packages are located in the component setting regions, Wherein the positioning patterns comprise a plurality of X-axis marking lines and a plurality of Y-axis marking lines, and are not covered by the die-stack packages; loading the light-transmitting properties of the chip-stack packages Wafer is carried in a wafer testing machine; a plurality of wafer testing probes of the wafer testing machine are used to probe the test electrodes to electrically test the die-stack packages; and through the light transmission Pseudo wafer carrier Irradiation of the photosensitive adhesive layer, the pickup for the plurality of stacked die package of the light-transmissive plate intended wafer. A wafer level test method for a single-die-stacked package according to claim 13 wherein the X-axis marks and the Y-axis marks extend to the periphery of the light-transmissive wafer carrier .