CN114050111A - Fan-out type packaging method and fan-out type packaging structure - Google Patents

Fan-out type packaging method and fan-out type packaging structure Download PDF

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Publication number
CN114050111A
CN114050111A CN202111358610.5A CN202111358610A CN114050111A CN 114050111 A CN114050111 A CN 114050111A CN 202111358610 A CN202111358610 A CN 202111358610A CN 114050111 A CN114050111 A CN 114050111A
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layer
metal
packaging
wafer
substrate
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陈文军
潘明东
张中
梅万元
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Jiangsu Silicon Integrity Semiconductor Technology Co Ltd
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Jiangsu Silicon Integrity Semiconductor Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying

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  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

The invention discloses a fan-out type packaging method and a fan-out type packaging structure.A plastic packaging wafer is prepared by adopting a wafer level packaging process, and is cut into countless independent packaging bodies after being pasted with a film; welding the packaging body and the passive element on a prepared substrate; coating sealant on the vacant position of the substrate, coating heat dissipation glue on the back of the packaging body, and installing the metal heat dissipation plate on the substrate in a pressing mode; and turning over the substrate on which the heat dissipation plate is mounted, and obtaining metal balls on the back of the substrate through ball planting and reflow processes. The invention fully utilizes the characteristics of the fan-out type packaging process, solves the problems that the passive element structure is not compatible with the high-temperature process and the chip dissipates heat, and has more stable packaging structure; the space in the vertical direction is effectively utilized in a three-dimensional stacking mode; the three-dimensional fan-out type interconnection among the functional chips is realized, the high-density interconnection is formed by using smaller size, the integration level is higher, and the realization is more facilitated.

Description

Fan-out type packaging method and fan-out type packaging structure
Technical Field
The invention belongs to the technical field of semiconductor packaging, and particularly relates to a fan-out packaging method and a fan-out packaging structure.
Background
The Fan-Out type is called as (Fan-Out Packaging) in English and called as (FOP) in Chinese, and adopts a mode of pulling Out pins in the chip to embed various different bare chips, and the bare chips are connected through high-density rewiring, so that the interconnection density is improved, the distance between the chips is shortened, the Packaging thickness is reduced, the space is saved, and the interconnection performance is improved.
However, the heat dissipation problem of the chips under the condition of high packaging density cannot be timely and effectively solved, especially in the packaging body for stacking multiple chips in order to realize high density. In addition, after the passive component is plastic-encapsulated in the package body, a plurality of high-temperature processes are required, and these high-temperature processes may affect the structure of the passive component, further causing the package structure to be damaged, and the subsequent package process cannot be performed.
Disclosure of Invention
The purpose of the invention is as follows: in order to solve the problems of heat dissipation of a chip and packaging of a passive element in a fan-out packaging process in the prior art, the invention provides a fan-out packaging method.
The invention also provides a fan-out type packaging structure.
The technical scheme is as follows: a fan-out packaging method comprising the steps of:
the method comprises the following steps: preparing a plastic package wafer by adopting a wafer level packaging process, and cutting the plastic package wafer into countless independent packages after film pasting;
step two: welding a first passive element on a substrate prepared in advance, and welding the cut independent packaging body on the substrate through a flip chip and reflow process;
step three: filling a gap between the packaging body and the substrate with a filling material;
step four: coating sealant on the vacant position of the substrate, coating heat dissipation glue on the back of the packaging body, and installing the metal heat dissipation plate on the substrate in a pressing mode;
step five: and turning over the substrate on which the heat dissipation plate is mounted, and obtaining metal balls on the back of the substrate through ball planting and reflow processes.
Further, in the first step, the preparation of the plastic package wafer by using the wafer level packaging process comprises the following steps:
(1) taking a carrier plate made of a light-transmitting material, and coating a composite separation layer on the carrier plate;
(2) sputtering a metal layer on the composite separation layer;
(3) forming a passivation layer and a first metal column above the sputtered metal layer through photoetching, sputtering and electroplating processes, wherein a chip reserved area is arranged on the surface of the passivation layer of the carrier plate;
(4) manufacturing a second metal column on the first layer of chip by using a wafer-level metal micro-bump technology, wherein the second metal column is in telecommunication connection with the first layer of chip;
(5) the first layer of chip is integrally thinned to the target thickness through a thinning process, and is cut into countless independent chip embedded bodies after film pasting;
(6) welding the chip embedding body in a chip reserved area on the surface of the passivation layer of the carrier plate by adopting a flip chip and welding process;
(7) carrying out primary plastic package on the carrier plate, the chip embedding body and the first metal column by using a plastic package material to form a first plastic package layer, wherein the height of the first plastic package layer is not lower than that of the first metal column, and the size of the first plastic package layer is smaller than that of the wafer;
(8) exposing the first metal column and the second metal column through lapping and polishing processes, and forming an insulating layer, a rewiring metal circuit layer and a rewiring metal circuit layer bonding pad on the upper part through photoetching, sputtering and electroplating processes;
(9) the second layer chip with the independent upper layer metal bonding pad is aligned and welded with the bonding pad of the rewiring metal circuit layer through the upper layer metal bonding pad by adopting the flip chip and welding process;
(10) filling a gap between the second layer of chip and the rewiring metal circuit layer with a filling material;
(11) carrying out secondary plastic package on the first plastic package layer, the second layer of chips and the rewiring metal circuit layer by using a plastic package material to form a second plastic package layer, wherein the size of the second plastic package layer is larger than that of the first plastic package layer and smaller than that of the wafer;
(12) performing debonding on the plastic package wafer, and removing the carrier plate;
(13) sticking a hot glass film on one surface of the original carrier plate of the plastic package wafer without the carrier plate;
(14) turning over the plastic package wafer on which the hot glass film is attached, and carrying out third plastic package to form a third plastic package layer, wherein the size of the third plastic package layer is equal to that of the wafer;
(15) turning over the plastic package wafer again, removing the hot glass film by adopting a pyrolytic bonding technology, and polishing the back plastic package material by a thinning process to expose the back of the second layer of chips;
(16) corroding the metal layer sputtered in the step two to expose the lead in the passivation layer;
(17) and sequentially forming a metal bump by adopting sputtering, photoetching and electroplating processes, wherein the metal bump is communicated with the lead in the passivation layer to prepare the plastic package wafer for later use.
Further, in the step (1), the carrier plate is one or more of glass and sapphire; in the step (2), the sputtered metal layer is one or more of aluminum, titanium and copper.
Further, in the step (12), the debonding includes: firstly, adhering an ultraviolet film on the upper surface of a first plastic packaging layer, fixing the ultraviolet film on a metal ring, irradiating the plastic packaging wafer by using laser with a specific wavelength to perform laser debonding, removing the carrier plate by using external force, irradiating the ultraviolet film adhered to the plastic packaging wafer by using ultraviolet light, tearing off the ultraviolet film to obtain the plastic packaging wafer without the carrier plate, and performing degumming and cleaning.
Further, in the step (8), the rewiring metal circuit layer is manufactured by adopting multiple photoetching, sputtering and electroplating processes; the rewiring metal circuit layer bonding pad is manufactured on the upper surface of the rewiring metal circuit layer through a wafer-level metal micro-bump technology.
Further, in the step (9), the upper layer metal pad is formed by scribing on the chip by using a wafer level metal micro bump technology.
Furthermore, in the first step, membrane removing treatment is not carried out after membrane pasting.
Further, step five includes soldering a second passive element on the back side of the substrate.
A fan-out type packaging structure comprises a packaging body, a first passive element, a substrate, a second filling layer, metal balls and a metal radiating plate, wherein the packaging body comprises a plurality of chips; the packaging body and the first passive element are welded with the substrate, and the second filling layer is positioned between the packaging body and the substrate; the metal heat dissipation plate is arranged on the back surface of the packaging body and the spare position of the substrate; the metal balls are positioned on the other surface of the substrate, and the metal balls, the packaging body and the first passive element form an interconnection structure through the substrate.
Furthermore, the packaging body is a multi-chip stacked three-dimensional packaging body and comprises a first layer of chip, a second layer of chip, a rewiring metal circuit layer, a metal bump, a passivation layer, a first metal column, a second metal column, a first filling layer, a first plastic packaging layer, a second plastic packaging layer and a third plastic packaging layer, wherein the first layer of chip is connected with the front side of the rewiring metal circuit layer through the second metal column; the first filling layer is filled between the second layer of chip and the rewiring metal circuit layer; the first plastic packaging layer is filled between the passivation layer and the rewiring metal circuit layer and wraps the first layer of chip, the first metal column and the second metal column; the second plastic packaging layer is positioned outside the first filling layer and wraps the first filling layer; the third plastic packaging layer is located outside the second plastic packaging layer and wraps the second plastic packaging layer.
Has the advantages that: compared with the prior art, the fan-out packaging method and the fan-out packaging structure provided by the invention have the advantages that the packaging characteristic that a high-density pin chip is fanned out into low-density pins in the fan-out packaging process is fully utilized, the metal cooling plate is extended to the spare position on the substrate, the area of the cooling plate is increased, and the cooling effect is better; the passive element is not plastically packaged in the packaging body, but is welded on the substrate, so that the negative influence of a high-temperature process on the passive element is reduced; the advantages of high fan-out type packaging wiring density and small interconnection distance are considered, and the space in the vertical direction is effectively utilized in a three-dimensional stacking mode; the three-dimensional fan-out type interconnection among the functional chips is realized, the high-density interconnection is formed by using smaller size, and compared with the traditional fan-out type packaging structure or the three-dimensional stacking process, the scheme has higher integration level and is more favorable for realization.
Drawings
FIG. 1 is a schematic cross-sectional view of an embodiment of a fan-out package structure;
FIGS. 2A-2U are schematic diagrams illustrating a manufacturing process of the high density fan out packaging method of the embodiment of FIG. 1;
the package comprises a package body 1, a first passive element 2, a substrate 3, a second filling layer 4, metal balls 5, a metal heat dissipation plate 6, a chip 7, a first layer chip 71, a second layer chip 72, a rewiring metal circuit layer 8, metal bumps 9, a passivation layer 10, first metal columns 11, second metal columns 12, a first filling layer 13, a first plastic package layer 14, a second plastic package layer 15, a third plastic package layer 16, a second passive element 17, a carrier plate 18, a composite separation layer 19, a metal layer 20, an ultraviolet film 21 and a hot glass film 22.
Detailed Description
The invention is further illustrated by the following figures and examples.
The embodiment of the application provides a fan-out package structure, as shown in fig. 1, including a package body 1, a first passive element 2, a substrate 3, a second filling layer 4, metal balls 5 and a metal heat dissipation plate 6, where the package body 1 includes a plurality of chips 7; the packaging body 1 and the first passive element 2 are welded with the substrate 3, and the second filling layer 4 is positioned between the packaging body 1 and the substrate 3; the metal heat dissipation plate 6 is arranged on the back surface of the packaging body 1 and the spare position of the substrate 3; the metal balls 5 are located on the other surface of the substrate 3, and the metal balls 5, the package body 1 and the first passive element 2 form an interconnection structure through the substrate 3. The metal heat dissipation plate 6 is tightly attached to the back face of the chip, the packaging characteristic that the high-density pin chip is fanned out into low-density pins is fully utilized, the metal heat dissipation plate 6 extends to the spare position on the substrate, the area of the metal heat dissipation plate 6 is large enough, and the heat dissipation effect is good. The first passive element 2 is not plastically packaged in the packaging body, but is welded on the substrate 3, the influence of a high-temperature process is small, and the stability of a fan-out packaging structure is ensured.
The package 1 is a multi-chip package, and in this embodiment, the package is a three-dimensional package with multiple chips stacked, so as to fully utilize the space in the vertical direction. The packaging body 1 comprises a first layer of chip 71, a second layer of chip 72, a rewiring metal line layer 8, a metal bump 9, a passivation layer 10, a first metal column 11, a second metal column 12, a first filling layer 13, a first plastic packaging layer 14, a second plastic packaging layer 15 and a third plastic packaging layer 16, wherein the first layer of chip 71 is connected with the front surface of the rewiring metal line layer 8 through the second metal column 12, the second layer of chip 72 is connected with the back surface of the rewiring metal line layer 8 through a rewiring metal line layer bonding pad, the metal bump 9 is arranged on the passivation layer 10, and the metal bump 9 is in telecommunication connection with the rewiring metal line layer 8 through the first metal column 11; the first filling layer 13 is filled between the second layer chip 72 and the rewiring metal circuit layer 8; the first plastic packaging layer 14 is filled between the passivation layer 10 and the rewiring metal circuit layer 8 and wraps the first layer chip 71, the first metal column 11 and the second metal column 12; the second plastic package layer 14 is positioned outside the first filling layer 13 and wraps the first filling layer 13; the third molding compound layer 16 is located outside the second molding compound layer 15 and wraps the second molding compound layer 15.
The package 1 may further include a second passive element 17, and the second passive element 17 is soldered to the surface of the substrate 3 having the metal balls 5.
Another embodiment of the present application provides a fan-out package method, which includes preparing an independent package 1, then soldering the package 1 and a passive component 2 on a substrate 3 prepared in advance, and mounting a metal heat dissipation plate 6, where the embodiment takes a three-dimensional package with stacked multiple chips as an example, as shown in fig. 2A to 2U, and specifically includes the following steps:
(1) referring to fig. 2A, a carrier 18 made of a transparent material, such as glass, sapphire, etc., is coated with a composite separation layer 19 on the carrier 18, and the carrier made of the transparent material is used to smoothly realize laser debonding and make the composite separation layer generate a photochemical reaction by laser irradiation.
(2) As shown in fig. 2B, a metal layer 20, such as aluminum, titanium, copper, etc., is sputtered on the composite separation layer 19 to shield the laser beam during laser debonding so as not to damage the wiring layer by direct laser irradiation.
(3) As shown in fig. 2C, a passivation layer 10 and a first metal pillar 11 are formed above the sputtered metal layer 20 through photolithography, sputtering, and electroplating processes, a chip reserved area is disposed on the surface of the passivation layer of the carrier, the chip reserved area may be disposed in the middle of the carrier, and the first metal pillar 11 is disposed at the periphery of the chip reserved area.
(4) As shown in fig. 2D, a second metal pillar 12 is fabricated on the first layer of chip 71 by using wafer-level metal micro-bump technology, and the second metal pillar 12 is in telecommunication connection with the first layer of chip 71;
(5) the first layer of chips 71 are integrally thinned to the target thickness through a thinning process, and are cut into countless independent chip embedded bodies after film pasting;
(6) as shown in fig. 2E, the chip embedding body is soldered to the chip reserved area on the surface of the passivation layer of the carrier board by using a flip chip and soldering process;
(7) as shown in fig. 2F, performing a first plastic package on the carrier plate 18, the chip embedded body, and the first metal pillar 11 with a plastic package material to form a first plastic package layer 14, where the height of the first plastic package layer 14 is not lower than the height of the first metal pillar 11, the size of the first plastic package layer 14 is smaller than the size of the wafer, and the size of the first plastic package layer 14 in this embodiment is 293mm, because a sufficient distance is left in a subsequent lamination plastic package process, performing two plastic packages again;
(8) through lapping and polishing processes, the first metal column 11 and the second metal column 12 are exposed, an insulating layer, a rewiring metal circuit layer 8 and a rewiring metal circuit layer bonding pad are formed on the upper part through photoetching, sputtering and electroplating processes, and the rewiring metal circuit layer 8 is manufactured through multiple photoetching, sputtering and electroplating processes; the rewiring metal line layer pads are fabricated on the upper surface of the rewiring metal line layer 8 by wafer level metal micro-bump technology, as shown in fig. 2G.
(9) As shown in fig. 2H, a second layer of chip 72 having an independent upper layer of metal pads formed by dicing on the chip using wafer-level metal micro-bump technology is aligned and bonded to the re-wiring metal circuit layer pads through the upper layer of metal pads by using a flip-chip, bonding process.
(10) The gap between the second chip 72 and the redistribution layer 8 is filled with a filler by capillary action to form a first filling layer 13, as shown in fig. 2I.
(11) Carrying out secondary plastic package on the first plastic package layer 14, the second layer of chips 72 and the rewiring metal circuit layer 8 by using a plastic package material to form a second plastic package layer 15, wherein the size of the second plastic package layer 15 is larger than that of the first plastic package layer 14 and smaller than that of a wafer, as shown in fig. 2J, the size of the second plastic package layer 15 is 296mm in the embodiment, and a certain distance is reserved in the plastic package process for edge pressing;
(12) performing debonding on the plastic package wafer, and removing the carrier plate;
the bonding-releasing method comprises the following steps: as shown in fig. 2K, an ultraviolet film 21 is adhered to the upper surface of the second plastic packaging layer 15 and fixed on the metal ring; irradiating the plastic package wafer by using laser with a specific wavelength to perform laser debonding, wherein a composite separation layer 19 material coated on the carrier plate 18 undergoes a photochemical reaction under the excitation of the laser to decompose the composite separation layer, the carrier plate 18 is separated from the metal layer 20, and the carrier plate is removed by using an external force; and irradiating the ultraviolet film 21 adhered to the plastic package wafer by ultraviolet light, wherein the ultraviolet film 21 loses viscosity after being irradiated by the ultraviolet light, pulling down the ultraviolet film as shown in figure 2L to obtain the plastic package wafer without the carrier plate, removing the glue, cleaning, and removing substances generated by photochemical reaction of the composite separation layer.
In fact, the existing process can also realize that the plastic package wafer is directly sent to a laser de-bonding machine table without an iron ring and ultraviolet film process, so that de-bonding is carried out, and the transparent carrier plate and the plastic package wafer are separated, and the result is the same.
(13) Referring to fig. 2M, a hot glass film 22 is attached to one surface of the plastic wafer without a carrier, which is used to protect the bottom of the circuit layer and prevent the bottom from being damaged.
(14) Turning over the plastic package wafer with the hot glass film 22 attached, and carrying out third plastic package to form a third plastic package layer 16, wherein the size of the third plastic package layer 16 is equal to 300mm, and the size of the third plastic package layer is ensured to be consistent with that of a normal wafer.
(15) As shown in fig. 2O, the plastic package wafer is turned over again, the thermal glass film 22 is removed by using the thermal decomposition bonding technology, so as to obtain a plastic package wafer with the circuit layer and the chips welded together, and the back surface plastic package material is ground by using the thinning process to expose the back surface of the second layer of chips 72.
(16) And as shown in fig. 2P, the metal layer 20 sputtered in the second step is etched away to expose the conductive lines in the bottom passivation layer.
(17) And (3) sequentially adopting sputtering, photoetching and electroplating processes to form a metal bump 9, as shown in figure 2Q, wherein the metal bump 9 is communicated with a lead in a passivation layer 10, and a multi-chip packaged plastic package wafer is prepared for standby.
(18) Cutting the plastic-packaged wafer into a plurality of independent packages 1 after film pasting, wherein film removing treatment is not carried out after film pasting;
(19) as shown in fig. 2R, a first passive component (SMT device) 2 is soldered on a substrate 3 prepared in advance, and individual packages 1 (not stripped) are diced and soldered on the substrate 3 by a flip-chip, reflow process.
(20) The gap between the package body 1 and the substrate 3 is filled with the filler by capillary phenomenon to form the second filling layer 4, as shown in fig. 2S.
(21) A sealant is applied to the vacant position of the substrate 3, a heat dissipation adhesive is applied to the back surface of the package 1, and the metal heat dissipation plate 6 is mounted on the substrate 3 and the package 1 by pressing, as shown in fig. 2T.
(22) The substrate 3 with the heat dissipation plate mounted thereon is turned over, and metal balls 5 are obtained on the back surface of the substrate through ball-mounting and reflow processes, as shown in fig. 2U, and a second passive component (SMT device) 17 can be soldered at a specific position on the back surface of the substrate by a soldering method as required.
The method fully utilizes the packaging characteristic that a high-density pin chip is fanned out into low-density pins in a fanout type packaging process, and extends the metal heat dissipation plate to the spare position on the substrate, so that the area of the heat dissipation plate is increased, and the heat dissipation effect is better; the passive element is not plastically packaged in the packaging body, but is welded on the substrate, so that the negative influence of a high-temperature process on the passive element is reduced; the advantages of high fan-out type packaging wiring density and small interconnection distance are considered, and the space in the vertical direction is effectively utilized in a three-dimensional stacking mode; the three-dimensional fan-out type interconnection among the functional chips is realized, the high-density interconnection is formed by using smaller size, the integration level is higher, and the realization is more facilitated.

Claims (10)

1. A fan-out packaging method, comprising the steps of:
the method comprises the following steps: preparing a plastic package wafer by adopting a wafer level packaging process, and cutting the plastic package wafer into countless independent packages after film pasting;
step two: welding a first passive element on a substrate prepared in advance, and welding the cut independent packaging body on the substrate through a flip chip and reflow process;
step three: filling a gap between the packaging body and the substrate with a filling material;
step four: coating sealant on the vacant position of the substrate, coating heat dissipation glue on the back of the packaging body, and installing the metal heat dissipation plate on the substrate in a pressing mode;
step five: and turning over the substrate on which the heat dissipation plate is mounted, and obtaining metal balls on the back of the substrate through ball planting and reflow processes.
2. The fan-out packaging method of claim 1, wherein in the first step, the step of preparing the plastic package wafer by using a wafer level packaging process comprises the steps of:
(1) taking a carrier plate made of a light-transmitting material, and coating a composite separation layer on the carrier plate;
(2) sputtering a metal layer on the composite separation layer;
(3) forming a passivation layer and a first metal column above the sputtered metal layer through photoetching, sputtering and electroplating processes, wherein a chip reserved area is arranged on the surface of the passivation layer of the carrier plate;
(4) manufacturing a second metal column on the first layer of chip by using a wafer-level metal micro-bump technology, wherein the second metal column is in telecommunication connection with the first layer of chip;
(5) the first layer of chip is integrally thinned to the target thickness through a thinning process, and is cut into countless independent chip embedded bodies after film pasting;
(6) welding the chip embedding body in a chip reserved area on the surface of the passivation layer of the carrier plate by adopting a flip chip and welding process;
(7) carrying out primary plastic package on the carrier plate, the chip embedding body and the first metal column by using a plastic package material to form a first plastic package layer, wherein the height of the first plastic package layer is not lower than that of the first metal column, and the size of the first plastic package layer is smaller than that of the wafer;
(8) exposing the first metal column and the second metal column through lapping and polishing processes, and forming an insulating layer, a rewiring metal circuit layer and a rewiring metal circuit layer bonding pad on the upper part through photoetching, sputtering and electroplating processes;
(9) the second layer chip with the independent upper layer metal bonding pad is aligned and welded with the bonding pad of the rewiring metal circuit layer through the upper layer metal bonding pad by adopting the flip chip and welding process;
(10) filling a gap between the second layer of chip and the rewiring metal circuit layer with a filling material;
(11) carrying out secondary plastic package on the first plastic package layer, the second layer of chips and the rewiring metal circuit layer by using a plastic package material to form a second plastic package layer, wherein the size of the second plastic package layer is larger than that of the first plastic package layer and smaller than that of the wafer;
(12) performing debonding on the plastic package wafer, and removing the carrier plate;
(13) sticking a hot glass film on one surface of the original carrier plate of the plastic package wafer without the carrier plate;
(14) turning over the plastic package wafer on which the hot glass film is attached, and carrying out third plastic package to form a third plastic package layer, wherein the size of the third plastic package layer is equal to that of the wafer;
(15) turning over the plastic package wafer again, removing the hot glass film by adopting a pyrolytic bonding technology, and polishing the back plastic package material by a thinning process to expose the back of the second layer of chips;
(16) corroding the metal layer sputtered in the step two to expose the lead in the passivation layer;
(17) and sequentially forming a metal bump by adopting sputtering, photoetching and electroplating processes, wherein the metal bump is communicated with the lead in the passivation layer to prepare the plastic package wafer for later use.
3. The fan-out packaging method of claim 2, wherein in step (1), the carrier is one or more of glass and sapphire; in the step (2), the sputtered metal layer is one or more of aluminum, titanium and copper.
4. The fan-out packaging method of claim 2, wherein in step (12), the de-bonding comprises: firstly, adhering an ultraviolet film on the upper surface of a first plastic packaging layer, fixing the ultraviolet film on a metal ring, irradiating the plastic packaging wafer by using laser with a specific wavelength to perform laser debonding, removing the carrier plate by using external force, irradiating the ultraviolet film adhered to the plastic packaging wafer by using ultraviolet light, tearing off the ultraviolet film to obtain the plastic packaging wafer without the carrier plate, and performing degumming and cleaning.
5. The fan-out packaging method of claim 2, wherein in the step (8), the rewiring metal circuit layer is manufactured by multiple photoetching, sputtering and electroplating processes; the rewiring metal circuit layer bonding pad is manufactured on the upper surface of the rewiring metal circuit layer through a wafer-level metal micro-bump technology.
6. The fan-out packaging method of claim 2, wherein in step (9), the upper metal pads are formed by dicing on the chip using wafer-level metal micro-bump technology.
7. The fan-out packaging method of any one of claims 1 to 6, wherein in the first step, no stripping treatment is performed after the film is attached.
8. The fan-out packaging method of any one of claims 1 to 6, wherein step five further comprises soldering a second passive component on the back side of the substrate.
9. A fan-out type packaging structure is characterized by comprising a packaging body, a first passive element, a substrate, a second filling layer, metal balls and a metal radiating plate, wherein the packaging body comprises a plurality of chips; the packaging body and the first passive element are welded with the substrate, and the second filling layer is positioned between the packaging body and the substrate; the metal heat dissipation plate is arranged on the back surface of the packaging body and the spare position of the substrate; the metal balls are positioned on the other surface of the substrate, and the metal balls, the packaging body and the first passive element form an interconnection structure through the substrate.
10. The fan-out package structure of claim 9, wherein the package is a multi-chip stacked three-dimensional package, the package comprises a first layer of chips, a second layer of chips, a rewiring metal line layer, a metal bump, a passivation layer, a first metal pillar, a second metal pillar, a first filling layer, a first molding layer, a second molding layer and a third molding layer, the first layer of chips is connected to the front surface of the rewiring metal line layer through the second metal pillar, the second layer of chips is connected to the back surface of the rewiring metal line layer through a pad of the rewiring metal line layer, the metal bump is disposed on the passivation layer, and the metal bump is in telecommunication connection with the rewiring metal line layer through the first metal pillar; the first filling layer is filled between the second layer of chip and the rewiring metal circuit layer; the first plastic packaging layer is filled between the passivation layer and the rewiring metal circuit layer and wraps the first layer of chip, the first metal column and the second metal column; the second plastic packaging layer is positioned outside the first filling layer and wraps the first filling layer; the third plastic packaging layer is located outside the second plastic packaging layer and wraps the second plastic packaging layer.
CN202111358610.5A 2021-11-16 2021-11-16 Fan-out type packaging method and fan-out type packaging structure Pending CN114050111A (en)

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