JP2011154627A - Semiconductor device, test method thereof, and system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the time of an I/O compression test at low cost. <P>SOLUTION: A semiconductor device includes a plurality of chips to which a plurality of I/O terminals DQ0 to DQ31 are commonly connected via TSV. Each of the chips includes an I/O compression circuit which outputs one compression result (at least either one of nodes 01 to 04, 10) obtained by compression of data from each of a plurality of internal data buses to one first I/O terminal of the plurality of I/O terminals, and a control circuit including a register group setting the number of the one first I/O terminal. Setting information that makes the one first I/O terminal different for each chip is registered in the group of registers, so that each chip memory inputs or outputs data by using a different I/O terminal number for each chip, so that I/O compression tests by the I/O compression circuits can be performed concurrently in parallel in the plurality of chips without a bus fight. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device, a test method thereof, and a system including the semiconductor device.

  A semiconductor device including a memory function, for example, a semiconductor memory device has been highly integrated and increased in capacity. As a technique for realizing high integration and large capacity, a plurality of chips (memory chips) are stacked on an I / O chip, and the plurality of chips stacked on the I / O chip are penetrated (respectively). A technology of connecting by a through electrode (TSV: Through Silicon Via) that penetrates the thickness direction of the chip (Patent Document 1) and two chips having the same structure in one package (that is, two memory dies) A stacked dual die package (DDP) technique (Patent Document 2) is known.

  By the way, a semiconductor memory device requires an operation test to test whether all memory cells operate normally before shipping after packaging (assembly process) for sealing the chip by molding or the like. The time required increases as the capacity increases. For this reason, a technique for shortening the operation test time (test time) is required.

  Here, not only shortening the operation test time but also reducing the number of drivers and comparators included in a tester device (or a controller mounted on a motherboard that controls the semiconductor device) that is a device for testing the semiconductor device. An I / O compression test function mounted on one chip is also known. The driver is a means for writing data from a tester device to a memory cell in the semiconductor device via, for example, a TSV included in the semiconductor device during an operation test, and the comparator is read from the memory cell during the operation test and transmitted through the TSV to the semiconductor device. It is means for determining whether or not the signal output (signal logic) sent to the outside matches the expected value of the tester device. The I / O compression test function refers to a specific I / O terminal among a plurality of I / O terminals included in a semiconductor device, and a plurality of I / O lines (internal data buses) included in each chip. ) At the same time (write), and outputs the AND logic result of the data on the plurality of I / O lines to the specific I / O terminal.

  Patent Document 3 discloses that this type of operation test shortening technique includes a chip having a data compression test mode for compressing and outputting read data.

JP 2004-327474 A JP 2006-172700 A JP-A-9-259600

  In a semiconductor device in which a plurality of chips are stacked and packaged by the above-described technology such as TSV or DDP, the I / O terminal of the semiconductor device and the I / O terminal (chip terminal) of each chip are connected to each other. For example, it is connected to an external terminal of the semiconductor device. Therefore, the I / O compression test cannot be performed on each chip at the same time. In other words, the tester device (or controller) is configured so that the I / O in the plurality of chips is connected to each of the plurality of chips connected in the same manner from one external terminal (I / O terminal) of the semiconductor device. The compression test cannot be performed at the same time. This is because the I / O compression test results of different chips are commonly connected in the package. Specifically, for example, when each of the plurality of chips outputs a test result to a corresponding chip terminal using the I / O compression test function, the chip terminals are electrically shared by the TSV. Multiple I / O compression test results bus fight at the same time. Therefore, the plurality of chips have only a means for performing I / O compression testing of each chip in time series, and the test time is increased by the number of the plurality of chips. Furthermore, as the number of I / O terminals increases, the number of drivers and comparators of the tester device (or controller) increases.

  According to the first aspect of the present invention, the plurality of I / O terminals included in the first chip and the plurality of I / O terminals included in the second chip include the first chip and the second chip. However, each of the first and second chips is connected in common to each of the plurality of internal data buses in the test mode. An I / O compression circuit for outputting to one of the I / O terminals, the number of the first I / O terminal of the first chip, and the first of the second chip A number setting register for setting the number of the first I / O terminal among the plurality of I / O terminals so that the number of the I / O terminal of the I / O terminal is different from each other. A test control circuit for controlling the / O compression circuit. In each of the chips, the I / O compression circuit activated by the test control circuit in the test mode transmits the corresponding data via the first I / O terminal which is different for each chip. Provided is a semiconductor device that inputs or outputs in parallel with the outside of the device.

  The I / O compression circuit includes a plurality of first I / O compression circuits respectively corresponding to a plurality of groups obtained by dividing the plurality of I / O terminals into a plurality of groups. In this case, each of the plurality of first I / O compression circuits receives a plurality of signals of the plurality of internal data buses respectively corresponding to the plurality of groups, and the plurality of first I / O compression circuits are in the test mode and the read mode. A first logic circuit that outputs the one compression result corresponding to each of the plurality of groups, a plurality of I / O terminals that respectively correspond to the plurality of groups, and one output node of the first logic circuit. And a first switch circuit electrically connected to any one of the plurality of I / O terminals respectively corresponding to the plurality of groups in the test mode. . The first I / O compression circuit electrically connects one output node of the first logic circuit and a plurality of input nodes of the first logic circuit in the test mode and the write mode, respectively. A second switch circuit to be connected may be included.

  The test control circuit further includes a compression rate setting register for changing the compression rate of the data. In this case, the I / O compression circuit includes a second I / O compression circuit that is the first compression rate for the plurality of I / O terminals, one of which is selected by the compression rate setting register. , Each having a second compression ratio lower than the first compression ratio, and including the plurality of first I / O compression circuits respectively corresponding to the plurality of groups. The second I / O compression circuit receives a plurality of signals from the plurality of internal data buses and outputs the one compression result in the test mode and the read mode, and the plurality of the plurality of internal data buses. An I / O terminal is connected between one output node of the second logic circuit and one output node of the second logic circuit is connected to any one of the plurality of I / O terminals in the test mode. A third switch circuit electrically connected to the first switch circuit.

  According to the second aspect of the present invention, the plurality of I / O terminals included in the first chip and the plurality of I / O terminals included in the second chip include the first chip and the second chip. Are I / O compression test methods for semiconductor devices connected to a plurality of external I / O terminals of the semiconductor devices communicating with the corresponding external devices, respectively, and after supplying power to the semiconductor devices, The first and second chips recognize or set different first and second information from each other, and are accessed by exclusive control with each other in the non-test mode. A first test result that is simultaneously accessed and output to one first I / O terminal selected by the first information by the first chip is selected from the corresponding plurality of external I / O terminals. One first external I / A first comparison with an expected value outside the semiconductor device via a terminal, and a second output from the second chip to one second I / O terminal selected by the second information The test results are output from the semiconductor device via one second external I / O terminal different from the one first external I / O terminal among the plurality of corresponding external I / O terminals. A semiconductor device I / O compression test method is provided in which the second comparison is performed with the expected value and the first and second comparisons are performed simultaneously and in parallel.

  According to the present invention, there is further provided a system including the above-described semiconductor device, and a controller connected to the semiconductor device via a command bus and an I / O bus and controlling the semiconductor device.

  1. Since the I / O compression test for a plurality of chips including the first and second chips can be performed in parallel, the time for the I / O compression test can be shortened.

  2. For example, when the I / O compression test is performed at the highest compression rate (only one terminal is used with 32 I / O terminals), the tester device driver and comparator need only be compressed, so the number of drivers and comparators in the tester device The cost can be reduced by reducing the cost.

It is the figure which showed typically the component required for an I / O compression test in one memory chip of the semiconductor devices by the Example of this invention. It is a figure for demonstrating the 32I / O compression test with respect to the semiconductor device by the Example of this invention. It is a figure for demonstrating the 8I / O compression test with respect to the semiconductor device by the Example of this invention. Relationship between the I / O terminal used in the write operation and the I / O terminal used in the read operation, the external terminal of the semiconductor device, and the terminal number of the tester device in the 32 I / O compression test for the semiconductor device according to the embodiment of the present invention. It is a figure for demonstrating. Relationship between the I / O terminal used in the write operation and the I / O terminal used in the read operation, the external terminal of the semiconductor device, and the terminal number of the tester device in the 8 I / O compression test for the semiconductor device according to the embodiment of the present invention It is a figure for demonstrating. It is a figure for demonstrating the relationship between the I / O terminal used at the time of write-in operation | movement, and the I / O terminal used at the time of read-out operation | movement in the 32 I / O compression test with respect to the semiconductor device by the Example of this invention. It is a figure for demonstrating the relationship between the I / O terminal used at the time of write-in operation | movement in the 8I / O compression test with respect to the semiconductor device by the Example of this invention, and the I / O terminal used at the time of read-out operation. It is a figure for demonstrating the I / O terminal used at the time of write-in operation | movement in the 32 I / O compression test with respect to the semiconductor device by the Example of this invention, and the I / O terminal used at the time of read-out operation. It is the block diagram which showed schematic structure of the Example of the system by this invention. FIG. 4 is a related diagram illustrating a schematic configuration of a planar array type semiconductor device as an example of a semiconductor device to which the present invention can be applied. FIG. 5 is a related diagram showing a schematic configuration of a stacked semiconductor device as another example of a semiconductor device to which the present invention can be applied. 1 is a related diagram illustrating a schematic configuration of a semiconductor device having eight memory chips stacked as an example of a stacked semiconductor device to which the present invention can be applied. FIG. It is the figure which showed schematic structure of the memory chip in the semiconductor device with which this invention can be applied.

  Typical examples of technical ideas for solving the problems of the present invention are shown below. However, it goes without saying that the claimed contents of the present application are not limited to this technical idea, but are the contents described in the claims of the present application.

  The present invention is a semiconductor device composed of a plurality of memory chips, and each memory chip is a semiconductor device to which a plurality of I / O terminals are connected in common, and each of the plurality of memory chips is a semiconductor device. An I / O compression circuit unit having an I / O compression test function after packaging, and a control circuit unit including a register group that allocates the I / O compression test function to one or more of a plurality of I / O terminals. By setting information for allocating one or more different I / O terminals for each memory chip in the register group of each memory chip, each memory chip is connected to the I / O via one or more different I / O terminals. The compression test function can be executed simultaneously in parallel.

  In short, the I / O compression technique is used so that the I / O terminals used for inputting / outputting compressed data in the I / O compression test are made different for each memory chip.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[Example]
Before explaining embodiments of the present invention, in order to facilitate understanding of the present invention, examples of semiconductor devices 1000 and 3000 to which the present invention can be applied will be described with reference to FIGS. . The examples shown in FIGS. 10, 11 and 12 are disclosed in Patent Document 1, and all examples are merely examples for facilitating understanding of the present invention, and limit the scope of rights of the present invention. It goes without saying that it is not.

  With reference to FIG. 10, a memory subsystem, that is, a memory module (semiconductor device) will be schematically described as a first example that can be a subject of the present invention. First, the memory module shown in FIG. 10 includes a module substrate 200, a plurality of DRAM (Dynamic Random Access Memory) chips (9 in the figure) 201 arranged in parallel on the module substrate 200 in a plan view, and a module substrate. 200 includes a register 202, a PLL (Phase Locked Loop) circuit 203, and an SPD (Serial Presence Detect) 204, which are arranged in the central portion of 200. Module board 200 is mounted on a mother board (not shown) by a connector (not shown). Here, in addition to the illustrated memory module, other memory modules are also mounted on the motherboard together with a chip set (memory controller), and a memory system is configured by the plurality of memory modules and the chip set.

  Module data wiring is provided from each DRAM 201 to the lower side of the figure, that is, in the short side direction of the module substrate 200, while module command / address wiring is provided from the register 202 to the lower side of the figure. Further, a module clock wiring extends downward from the PLL 203 in the drawing, and these module command / address wiring and module clock wiring are connected to connectors arranged in the long side direction of the module substrate 200. The SPD 204 is a memory that determines the operating conditions of the DRAM chip 201 mounted on the module substrate 200, and is usually composed of a ROM.

  Further, from the register 202, a module command / address distribution wiring is applied to each DRAM chip 201 in the long side direction of the module substrate 200, that is, in the horizontal direction, and the module clock distribution is similarly performed from the PLL circuit 203. Wiring is applied to each DRAM chip 201.

  In the memory module having this configuration, data of the number of bits corresponding to the bus width of the memory access data bus can be input / output as module data.

  A memory module (semiconductor device) as a second example of the semiconductor device 3000 will be described with reference to FIG. The memory module shown in FIG. 11 can input / output data signals corresponding to the data widths of a plurality of DRAM chips as the memory data bus width, similarly to the memory module shown in FIG. As described above, a memory system that includes a plurality of memory chips as a whole by including a plurality of, here, eight DRAM chips in a stacked structure, and that can include a plurality of memory subsystems to increase the memory capacity and reduce the mounting area. Can be configured.

  In FIG. 11, the memory module includes an interposer substrate 210, an I / O chip 211 mounted on the interposer substrate 210, and eight DRAM chips 201 stacked on the I / O chip 211. Hereinafter, layers 0 to 7 may be called upward from the lowermost DRAM chip adjacent to the I / O chip 211. Layer 0 is the first chip, and any one of layers 1 to 7 is the second chip.

  Next, each part constituting the memory module will be described. The I / O chip 211 and the DRAM chip 201 of each layer are connected by a through electrode, that is, a TSV 215, and a data signal is transmitted via the TSV 215. To and from. Here, TSV 215 is an inter-chip connection electrode penetrating from one surface of each DRAM chip 201 to the other surface. For convenience, only one is shown in FIG. 11, but 72 × formed of copper or aluminum, for example. Four (= 288) TSVs are provided.

  In addition, the interposer substrate 210 is made of silicon and supports all on-board mounting pitches of system data signals, system address signals, system control signals, and system clock signals necessary to configure the functions of a one-channel memory subsystem. BGA (Ball Grid Array) terminals, and each signal BGA terminal and a signal pad on an I / O chip formed of a silicon chip are provided with a function that enables wiring by a substrate wiring and a bump. Yes.

  The I / O chip 211 has a function of reconfiguring the signal input from the chip set to operate the DRAM chip 201, a function of transmitting the signal from the terminal by the TSV 215 to the DRAM chip 201, and a signal from the DRAM chip 201 as the TSV 215. And a function of reconfiguring a data signal received from the DRAM chip 201 and transmitting it as a system data signal.

  A plurality of BGA terminals of the interposer substrate 210 are connected to input / output pads and input pads of each input / output circuit (I / O circuit) on the I / O chip 211 and stacked on the I / O chip 211. The data signal terminal, the address signal terminal, and the control signal terminal of the DRAM chip 201 and the I / O chip 211 are joined by the TSV 215, and the data signal, the address signal, and the control signal between the chips are received and transmitted via the TSV 215. Further, power and GND are supplied from the BGA terminal of the interposer substrate 210 to the pads on the I / O chip 211 and supplied to the power and GND terminals of the DRAM chips 201 via the TSV 215.

  The data signal terminal of each DRAM chip 201 is connected to the data signal terminal of the I / O chip 211 via the TSV 215. In this case, the TSV 215 as a data signal line is shared by each DRAM chip 201. The address signal terminal of each DRAM chip 201 shares the TSV 215 as an address signal line and is connected to the address signal terminal of the I / O chip 211. Further, the control signal terminal of each DRAM chip 201 shares the TSV 215 as a control signal line and is connected to the control signal terminal of the I / O chip 211.

  Referring to FIG. 12 in which the semiconductor device 3000 is expressed from a different viewpoint (functional), eight DRAM chips 201 are stacked on the I / O chip 211, and the stacked DRAMs are indicated by hatching. One DRAM chip of the chips 201 is selected. Thus, since the memory module to which the present invention can be applied can change the number of DRAM chips 201 stacked on the I / O chip 211, the I / O chip 211 can determine the number of stacked DRAM chips 201. Composed.

  In the example shown in FIG. 12, each DRAM chip 201 constitutes a single bank, and each DRAM chip 201 has × 256 data terminals, while the I / O chip 211 has ××. 64 system data lines are provided.

  An example of a semiconductor device (DRAM chip 201) to which the technical idea of the present application is applied is disclosed in FIG. A schematic configuration of the DRAM chip will be described. Here, the configuration of the layer 0 DRAM chip is shown, and the DRAM chips of other layers also have the same configuration.

  The DRAM chip 201 includes a test circuit 300 that is a characteristic part of the present application. A detailed configuration of the test circuit 300 will be described later with reference to FIG. First, the entire DRAM chip 201 will be described. Address signals A0 to A13 from a controller (not shown) are applied to the address buffer 305. The address buffer 305 outputs address signals AX0-13 and AY0-9 to the X decoder 307 and the Y decoder 309, respectively. The DRAM array 301 shown in the drawing has 128 bits (ie, × 128) with the parallel-serial conversion circuit 313 when the address signals AX0 to 13 and AY0 to 9 are given to the X and Y decoders 307 and 309, respectively. Input and output data signals in parallel. The input / output operation of the 128-bit data signal is performed under the control of the command from the command decoder 303 that receives the chip selection signal CS and the clock signal CK0 and the clock from the DLL circuit 311. The command decoder 303 also receives a row address strobe signal / RAS, a column address strobe signal / CAS, a write enable signal / WE, etc. from the controller.

  The parallel-serial conversion circuit 313 sends / receives a x128-bit parallel data signal to / from the DRAM array 301 and sends / receives a 32-bit parallel data signal (x32) to / from the controller. That is, the parallel-serial conversion circuit 313 has a function of converting a x128-bit data signal into a x32-bit data signal and converting a x32-bit data signal into a x128-bit data signal.

  FIG. 1 schematically shows a configuration in one memory chip (one layer) among eight layers of semiconductor chips (memory chips) (layer 0 to layer 7) included in the semiconductor device 3000. It goes without saying that other memory chips have exactly the same configuration. FIG. 1 mainly shows components necessary for an I / O compression test, which will be described later. For example, a command decoder, an address buffer, an X decoder, a Y decoder, and a DLL circuit described in FIG. The parallel-serial conversion circuit and various signals transmitted and received in each of these components are not shown. Therefore, TSVs necessary for transmission / reception of various signals also indicate only 32 TSVs (here used as I / O terminals DQ0 to DQ31) necessary for an I / O compression test described later. .

  However, in the upper right of FIG. 1, a plurality of TSVs for receiving a clock signal Clocks from a controller (not shown) and circuit elements of the control system (test control circuit, particularly the first test control circuit) are passed through the plurality of TSVs. Based on the received clock signal, a write mode signal, a read mode signal, and a test mode signal are generated, and the first register Reg. 1 (compression ratio setting register) via the first control signal Reg. S1, the second register Reg. 2 (compression ratio setting register) via the second control signal Reg. S2, third register Reg. 3 (number setting register), the third control signal Reg. Control circuit Cntl. cir. Is shown. This control circuit Cntl. cir. Also outputs an array control signal Array cont signals to the memory cell array. The first register Reg. 1 and the second register Reg. 2 may be one, and the other may be an inverted signal obtained by inverting the output signal of one of the registers.

  On the other hand, in the lower right of FIG. 1, as other circuit elements of the control system (test control circuit, particularly the second test control circuit), a test mode signal, a write mode signal, a read mode signal, and a first control signal Reg. . S1, the second control signal Reg. Data input / output format (uncompressed or compressed) based on S2, Case 1-R (second test condition signal) that defines a test mode (32 I / O compression or 8 I / O compression), Case 1-W (first Test condition signal), Case2-R (fourth test condition signal), and Case2-W (third test condition signal). cir. Is shown.

  Test control circuit Test. cir. Includes an inverter circuit INV that receives a test mode signal and generates a normal mode signal, a test mode signal, and a first control signal Reg. A two-input AND circuit A1 having S1 as an input, a test mode signal and a second control signal Reg. A 2-input AND circuit A2 having S2 as an input, a 2-input AND circuit A3 having a read mode signal and an output of the AND circuit A1 as inputs, a write mode signal and an output of the AND circuit A1 A 2-input AND circuit A4 as an input, a 2-input AND circuit A5 that receives a read mode signal and the output of the AND circuit A2, and a write mode signal and an output of the AND circuit A2 as inputs. And a 2-input AND circuit A6. The AND circuits A3 to A6 respectively have Case1-R (second test condition signal), Case1-W (first test condition signal), Case2-R (fourth test condition signal), and Case2-W (third Test condition signal).

  First to third registers Reg. 1-Reg. 3 may be collectively referred to as a register group, and the register group and the control circuit Cntl. cir. , Test control circuit Test. cir. May be collectively referred to as a control circuit section.

  A plurality of I / O terminals DQ0 to DQ31 (a plurality of first nodes) respectively constituted by a plurality of TSVs with which the memory chip 201 communicates with the outside are connected to a well-known I / O circuit unit IOC. In FIG. 10, it is an external terminal of the chip 201. 1 and 10, it should be noted that the external terminals of the semiconductor devices 1000 and 3000 are different.

  Returning to the description of FIG. 1, the I / O circuit unit IOC is connected to various elements of the test circuit 300 described later. Here, the I / O circuit unit IOC is grouped into four I / O circuits IO group 0 to IO group 3. In this I / O compression test, which will be described later, this grouping constitutes 8 compression × 4 groups (hence 32 I / O / 1 chip), and one group is composed of 8 I / O terminals. This is because switching to different I / O circuits (I / O terminals) is performed in the chips (layer 0 to layer 7). The IO group 0 is a plurality of I / O circuits I / O0, I / O4, I / O8, and I / O12 connected to the I / O terminals DQ0, DQ4, DQ8, DQ12, DQ16, DQ20, DQ24, and DQ28, respectively. , I / O16, I / O20, I / O24, I / O28, and IO group 1 is connected to each of I / O terminals DQ1, DQ5, DQ9, DQ13, DQ17, DQ21, DQ25, and DQ29. The I / O circuit includes I / O1, I / O5, I / O9, I / O13, I / O17, I / O21, I / O25, and I / O29. Similarly, the IO group 2 includes a plurality of I / O circuits I / O2, I / O6, and I / O10 connected to the I / O terminals DQ2, DQ6, DQ10, DQ14, DQ18, DQ22, DQ26, and DQ30, respectively. , I / O14, I / O18, I / O22, I / O26, and I / O30, and IO group 3 is connected to each of I / O terminals DQ3, DQ7, DQ11, DQ15, DQ19, DQ23, DQ27, and DQ31 The plurality of I / O circuits I / O3, I / O7, I / O11, I / O15, I / O19, I / O23, I / O27, and I / O31.

  Here, as a component of the test circuit after packaging, one compression 32 circuit (32 I / O compression circuit) C32 (second I / O compression circuit) related to the 32 I / O compression test (first compression ratio) ) Four 8I / O compression test-related (second compression ratio) 8I / O compression circuits C8-0, C8-1, C8-2, C8-3 (four first I / O compression circuits) ). The 32 I / O compression circuit and the 8 I / O compression circuit may be collectively referred to as an I / O compression circuit unit. As a feature of the present embodiment, the compression 32 circuit C32 is a switch for connecting uncompressed write data to one or more specific I / O circuits (here, all I / O terminals DQ0 to DQ31) in the 32I / O compression test. A circuit TSW32-W and a switch circuit TSW32-R that connects the compression result to one or more specific I / O circuits (here, one I / O terminal) are included. The compression 32 means that 32 pieces of data are received and the calculation result is output as one calculation result signal. The later-described compression 8 means that eight data are received and the calculation result is output as one calculation result signal.

  On the other hand, in the 8I / O compression test, the compressed write data or the compression result is connected to one or more specific I / O circuits (here, four I / O terminals). For this purpose, the 8I / O compression circuit includes a combination of a compression 8 circuit C8-i (i is 0 to 3) connected in series and a corresponding switch circuit TSW8-i for each group. That is, the 8I / O compression circuit includes a combination of the compression 8 circuit C8-0 and the switch circuit TSW8-0, a combination of the compression 8 circuit C8-1 and the switch circuit TSW8-1, and a compression 8 circuit C8-2 and the switch circuit. A combination of TSW8-2 and a combination of compression 8 circuit C8-3 and switch circuit TSW8-3 are included.

  The memory chip is further connected in parallel to each of four series of compression 8 circuits C8-0 to C8-3 and switch circuits TSW8-0 to TSW8-3 for operation in the normal mode. There are two normal switch circuits NSW8-0 to NSW8-3.

  The first to third registers Reg. 1-Reg. 3 has the following functions.

  Register A (Reg. 1) for determining the type of test mode: It is possible to individually select data input to operate without compression and data output to operate with compression.

  Register B (Reg. 2) for determining the data compression rate: It is possible to individually select 32 I / O compression and 8 I / O compression.

  Register C (Reg. 3) for determining an I / O terminal: The I / O terminal can be individually set to be set to one I / O terminal or set to a plurality of I / O terminals.

  As will be described in detail later, the I / O compression test is performed in the following cases 1 and 2.

Case 1 (Case 1):
A. Data input (write) operates without compression, data output (read) operates with compression,
B. Compression rate works with 32 I / O compression,
C. The I / O terminal is set to one I / O terminal that is different for each memory chip.

Case 2 (Case 2):
A. Both data input (write) and output (read) are compressed.
B. Compression rate works with 8I / O compression,
C. I / O terminals are set to different I / O terminals for each memory chip.

  In the following, Case1-W and Case1-R are referred to as case 1 write and case 1 read, respectively. Case2-W and Case2-R may be referred to as case 2 write and case 2 read, respectively.

  Next, the compression 32 circuit C32 will be described.

  The switch circuit TSW32-R in the compression 32 circuit C32 is used in the read operation (Case1-R) in the 32I / O compression test, and is an AND circuit AND2 (logic circuit; second logic circuit) and its output (output) Node: a switch circuit TSW32 (first switch circuit: third switch circuit) connected to the test result). The AND circuit AND2 is activated by the second test condition signal Case1-R, and the 32 read data (internal data bus) from the memory cell array by the read operation in the 32 I / O compression test is transferred to each of the AND circuits AND2. If it is output to the input node and all the 32 read data are of the same logic, the output (node 10; one compression result) of the AND circuit AND2 is set to a high level. The switch circuit TSW32 is a circuit of the form of 1 input-8 outputs (outputs a to h), and the control circuit Cntl. cir. From the third control signal Reg. In S3, the output is switched to any one of outputs a to h, and the output of the AND circuit AND2 is transferred to the corresponding I / O circuit (I / O terminal).

  On the other hand, the switch circuit TSW32-W (second switch circuit) in the compression 32 circuit C32 is a 1-input-1-output type circuit used in the write operation (Case1-W) in the 32I / O compression test. Each write data from 32 I / O circuits (I / O terminals) is transferred in parallel to 32 internal data buses.

  Since the four sets of the compression 8 circuit C8, the switch circuit TSW8, and the normal switch circuit NSW8 all have the same configuration, the first compression 8 circuit C8-0, switch circuit TSW8-0, and normal switch circuit NSW8-0 are described below. explain.

  The compression 8 circuit C8-0 has an 8-input-1-output format AND circuit AND1 (logic circuit; first logic circuit) and a 1-input-8-output format connected to its output (output node: test result). Switch circuit TSW8-0 (first switch circuit). The AND circuit AND1 is used at the time of a read operation (Case2-R) in the 8I / O compression test, activated by the fourth test condition signal Case2-R, and eight read data (from the memory cell array ( (Internal data bus) is output to each input node of the AND circuit AND1, and if all eight read data have the same logic, the output (node 01; one compression result) is set to a high level.

On the other hand, the switch circuit TSW8 ₁ -0 (second switching circuit) in the compression 8 circuit C8-0 is intended to be used during the write operation in (Case2-W) 8I / O compression test, of eight its output Connected to the internal data bus, the signal of node 01 is transferred to the eight internal data buses.

Next, the switch circuit TSW8-0 (first switch circuit) is used in both the read operation and the write operation in the 8I / O compression test. During the read operation, 1 input (node 01 side) -8 output ( a-h side) circuit, and at the time of write operation, it operates as an 8-input (a-h side) -1 output (node 01 side) type circuit. That is, the switch circuit TSW8-0 receives the third control signal Reg. In S3, the output is switched to any one of the outputs a to h, and the output of the AND circuit AND1 is transferred to one corresponding I / O circuit (I / O terminal). The switch circuit TSW8-0 receives the third control signal Reg. The switch circuit TSW8 ₁ which is switched to any one of the inputs a to h by S3 and the input from the corresponding I / O circuit (I / O terminal) is controlled by the third test condition signal “Case2-W”. Transfer to -0.

As described above, the switch circuit TSW8-0, since it is used in both the read operation time and the write operation in the 8I / O compression test, the combination of the switch circuit TSW8-0 a switch circuit TSW8 ₁ -0 Part It is called a primary switch circuit, and the combination of the switch circuit TSW8-0 and the AND circuit AND1 may be called a secondary switch circuit.

  As described above, there are four normal switch circuits NSW8-0 to NSW8-3, which are circuit elements other than the test (circuit elements used during normal operation), between the I / O circuit and the internal data bus. These normal switch circuits are 1-input-1-output type circuits. For example, the normal switch circuit NSW8-0 connects the I / O circuit and the internal data bus during normal operation, and the corresponding data (write Data, read data).

  Next, the circuit elements of the control system will be described in detail.

  As described above, the memory chip includes a plurality of TSVs to which a plurality of clock signals for controlling the memory chip are input and a control circuit Cntl. cir. , First to third registers Reg. 1-Reg. 3, a test control circuit Test.Test.Test that generates a plurality of types of test condition signals Case1-R, Case1-W, Case2-R, Case2-W. cir. Have

  A plurality of TSVs to which a plurality of control signals for control are respectively input are also commonly connected among the eight layers of memory chips (similar to the common connection of TSVs related to the I / O compression test).

  Control circuit Cntl. cir. Generates a plurality of control signals below from a plurality of signals such as clocks received via a plurality of TSVs.

  The write mode signal is a basic signal that instructs the memory chip to perform a write operation.

  The read mode signal is a basic signal that instructs the memory chip to perform a read operation.

  The test mode signal is a basic signal that instructs the memory chip to perform a test mode operation.

  Control circuit Cntl. cir. Are registered in the first register Reg. 1, second register Reg. 2, the degree of I / O compression at the time of the test (here, 32 I / O compression, 8 I / O compression) is registered as setting information. When the 32 I / O compression test is performed, the first register Reg. Is registered from the outside (controller) of the memory chip via the control TSV. Register a high level to 1. On the other hand, when the 8I / O compression test is performed, the second register Reg. 2. Register a high level to 2. The first and second registers Reg. 1, Reg. When both 2 are at a high level, either one of the compression modes is selected by an arbiter (not shown).

  Control circuit Cntl. cir. Is the third register Reg. 3 is also registered. The third register Reg. 3 has a function of storing layer number information of a plurality of memory chips. From the outside of the memory chip via the control TSV, the third register Reg. Register the code to 3. This code may be set at the time of testing, may be set in a wafer state before this chip is diced, or may be set after the plurality of chips are assembled into one semiconductor device. . On the other hand, the third register Reg. 3 may also be used as a volatile layer recognition circuit that each memory chip automatically recognizes a layer number when power is supplied to the semiconductor device 1000 (afterwards). The code is represented by a 3-bit binary code in an example in which the stacked memory chips are 8 layers and are registered in binary. As will be described later, for example, layer number information of layer 0 is “000”, layer number information of layer 1 is “001”, and similarly, layer number information of layer 7 is represented by “111”. . The third register Reg. 3 may be non-volatile (for example, ROM).

  The third register Reg. 3 controls the above-described various switch circuits (TSW32, TSW8-0 to TSW8-3, etc.), and in the read mode at the time of testing, a plurality of test results respectively possessed by a plurality of chips are connected by a common TSV. The I / O circuit (I / O terminal) is different for each memory chip so that the bus fight is not performed by the plurality of I / O circuits (I / O terminals), in other words, the bus fight is not performed in the semiconductor device. Information for switching to a plurality of switch circuits is provided. The same applies to the write mode during the 8I / O compression test, and to different I / O circuits (I / O terminals) in each memory chip so as not to capture write data of different logic (data of different TSV lines). Switch.

  Examples of these memory chip layers and switching will be described later.

  Test control circuit Test. cir. Generates a Case 1 signal for instructing a 32 I / O compression test and a Case 2 signal for instructing an 8 I / O compression test. As described above, “-R” following Case 1 and Case 2 is a signal activated at the time of test and read operation, and “−W” following Case 1 and Case 2 is a signal activated at the time of test and during write operation. These are the first register Reg. 1, second register Reg. The activity is selected by 2. In addition, the test control circuit Test. cir. Also generates a normal mode signal indicating a state other than during the test.

  The memory cell array inputs and outputs 32 data corresponding to one command (read command, write command).

  FIG. 2 shows a plurality of drivers for a semiconductor device and a tester device having an eight-layer stacked structure in which 32 I / O terminals (data terminals) DQ0 to DQ31 are commonly connected (same connection) by a plurality of TSVs. FIG. 5 is a schematic diagram showing a DV (data driver) and a plurality of driver / comparators CP (comparators of outputs from corresponding I / O terminals and expected values) as a single unit. The IO chip 211 is omitted. The configuration in the memory chip (one layer) is as described above. In particular, FIG. 2 is a diagram for explaining the 32 I / O compression test of Case 1.

  Each of the eight memory chips is indicated by any one of layer numbers 0 to 7, and an example of a tester device, a driver DV and a driver / comparator CP therein are shown on the left side of FIG. On the right side of FIG. 2, one I / O terminal DQ in each layer memory chip is commonly connected by a plurality of (in this case, eight) TSVs corresponding to each layer, and is connected to the I / O circuit of each chip. Indicates that it is connected. Each TSV (I / O terminal) is commonly connected between the memory chips, and is connected to the driver DV or the driver / comparator CP on the tester device side.

  Note that the layer number is the third register Reg. This corresponds to the information of No. 3.

  A plurality of external terminals (PKG external terminal group; 32 I / O terminals; external I / O terminals) of the semiconductor device are composed of, for example, well-known solder balls or the like. The pin of the comparator CP contacts an external terminal (solder ball) of the semiconductor device via a test jig (socket or the like). Here, 32 TSVs corresponding to 32 I / O terminals DQ0 to DQ31 and 32 external terminals (solder balls) are respectively connected. Since 32 I / O circuits corresponding to 32 TSVs are grouped into 4 groups, in this embodiment, the tester device has 32 output pins, and these 32 pins are 4 Divided into groups, the card numbers (pin numbers) of the tester devices in each group are numbered so as to correspond to the numbers of 32 I / O terminals. In the present embodiment (case 1), the tester device is the first and second of each group, that is, a total of 8 functions as a driver / comparator CP, and the remaining 24 function as a driver DV.

  Referring to FIG. 2, case 1 (A: data input is uncompressed, data output is compressed, B: compression rate is 32 I / O compression, C: I / O terminal is one I / O terminal that is different for each chip. ).

  After the power supply to the semiconductor device, the third register Reg. Each of the first and second chips has. Different information is set in 3. The different information is recognized by a layer recognition circuit included in each of the first and second chips, or set from the outside of the semiconductor device. During the write operation during the test, the tester device writes data from 8 driver comparators CP and 24 drivers DV to the PKG external terminal of the semiconductor device as shown in [When writing] in the test table of case 1 according to FIG. Output each data. The semiconductor device has 32 I / O terminals DQ0 to DQ31 that are commonly connected by eight common TSVs (they are cascaded in the stacking direction) in each of the eight layers of memory chips. Therefore, 32 pieces of write data (parallel data) from the tester device are simultaneously written in the respective memory cell arrays of the eight-layer memory chip. That is, each memory chip has a switch circuit TSW32-W (see FIG. 1) from 32 I / O terminals DQ0 to DQ31 (32 TSVs) to the corresponding internal data bus (32 connected to the memory cell array). Data is written via

  At the time of the read operation at the time of test, as shown in [When reading] in the test table of case 1 according to FIG. 4, the semiconductor device has one test result that each memory chip has (generates) (total of eight in the semiconductor device). The test result information is output to eight PKG external terminals of the semiconductor device via different TSVs, that is, different one I / O terminals, respectively in eight memory chips. In the tester device, eight test results are received by the eight driver / comparator CPs of card numbers 0 to 7 connected to the eight PKG external terminals, respectively, and each test result is compared with the corresponding eight expected values. Perform verification. The tester device determines that the eight test results are normal if all of the eight test results have the same logic as the expected value.

  In this way, in the tester device, the number of comparators CP that are more expensive than the driver DV can be suppressed to only eight. That is, the number of channels of the driver DV and the comparator CP on the tester device side is only 8 channels corresponding to only DQ0 to DQ7 for I / O compression. On the other hand, the number of channels of the driver on the tester device side that does not perform I / O compression (sends only write data) is 24 channels (= 32-8).

  That is, the number of comparators used per semiconductor device (here, configured with 8 memory chips) can be reduced. On the other hand, since it can be allocated to other devices (semiconductor devices), the number of devices to be measured increases in simultaneous measurement in which a plurality of semiconductor devices are measured simultaneously (in parallel). Both of them can greatly reduce the test cost.

  In each internal data bus (32) of each memory chip, the read data is compressed (verified by the AND circuit AND2) through the above-mentioned 32 I / O compression, and the result is sent through one terminal of the switch circuit TSW32. To one I / O terminal (one PKG external terminal of the semiconductor device). The selection of any one of the I / O terminals is performed by the third register Reg. 3 is different for each memory chip. Specifically, as apparent from FIG. 4, the switch circuit TSW32 in the layer 0 memory chip selects the output a, the switch circuit TSW32 in the layer 1 memory chip selects the output b, and so on. The switch circuit TSW32 in the memory chips of layers 3, 4, 5, 6, and 7 selects outputs c, d, e, f, g, and h, respectively.

  In case 1, the eight memory chips are mutually exclusive during normal operation, which is a non-test time, whereas it is necessary to note that the eight memory chips are simultaneously accessed during this test. . The exclusive control is natural for bus fight suppression because a plurality of I / O terminals respectively included in the eight memory chips are commonly connected. For example, at the time of normal operation, it is recognized by three address signals (not shown) for selecting one from eight memory chips mapped to different address spaces in the system space (logic). The semiconductor device sets these three addresses as don't cares (Inhibit) by the test signal. Instead of the three addresses, three control signals (for example, three CS signals or three WE signals) may be used.

  Next, referring to FIG. 3, Case 2 (A: data input and output are both compressed, B: compression ratio is 8 I / O compression, and C: I / O terminals are different I / O terminals for each memory chip. ). Differences from the description of FIG. 2 are mainly described. The structure in the semiconductor device is the same as that described in FIG. In this embodiment (Case 2), all the groups of the tester device function as the driver / comparator CP.

At the time of the write operation during the test, the tester device outputs the write data from the 32 driver comparators CP to the PKG external terminal group of the semiconductor device, as shown in [When writing] in the test table of case 2 according to FIG. . The semiconductor devices are commonly connected by eight TSVs associated with one I / O terminal DQ. That is, the semiconductor device is composed of eight layers of semiconductor chips having 32 I / O terminals DQ, and 32 pieces of write data from the tester device are assigned as four pieces of write data per one layer of memory chip. However, as will be described later, the four write data are associated with different I / O terminals DQ for each memory chip. In one layer of memory chip, one write data is simultaneously written to eight internal data buses (eight connected to the memory cell array). More specifically, each memory chip switching circuit TSW8-i (i is 0-3 either) and compression 8 circuit _C8 1 -i (test conditions signals corresponding from each one of I / O pins for each group Data is written to the corresponding internal data bus (eight) via a switch controlled by Case2-W. This is simultaneously written into each memory cell array of the eight-layer memory chip by four systems (four switch circuits TSW8-i and four compression 8 circuits C8-i) corresponding to four write data.

  At the time of a read operation at the time of test, as shown in [When reading] in the test table of case 2 according to FIG. 5, information of four test results (total 32 test results) each memory chip has (generates) is provided. Each of the eight memory chips outputs data to 32 PKG external terminals of the semiconductor device via different TSVs, that is, different I / O terminals. In the tester device, the 32 driver / comparators CP perform verification by comparing the 32 test results with the corresponding 32 expected values. The tester apparatus determines that it is normal if all 32 test results have the same logic as the expected value.

  In this way, in the tester device, different data patterns can be combined for each memory chip in each layer and / or in each 8I / O compression group, so that advanced test screening can be performed. In particular, data interference between multiple TSVs can also be included in the test. A plurality of TSV columns that are each cascade-connected in the stacking direction have an interval 10 times or more smaller than the interval between signal lines outside the semiconductor device. It is possible to check for adverse effects caused by coupling interference between a plurality of TSV rows. Also, the gap between the stacked memory chips is very small. In these characteristic structures, for example, write data for each DQ set / layer is “High” data for I / O terminals DQ0 to DQ3 (for layer 0), and I / O terminals DQ4 to DQ7 (for layer 1). ) Is changed to “Low” data,..., The influence of the data difference between layers can be seen. For example, only the I / O terminals DQ16 to DQ19 of the layer 4 are different from the I / O terminals of the other layers. In this case, the layer 4 sandwiched between the memory chips of the layer 3 and the layer 5 is processed by the memory chip that processes the data of the layer 4 by the coupling capacity of the parallel plates of the memory chips of the layers 3 and 5. It can be seen whether or not the memory chips of the layers 3 and 5 are subjected to interference.

  In each internal data bus (eight) of each memory chip, data is compressed (verified by the AND circuit AND1) via the compression 8 circuit C8-i, and the result is one of the above-described ones via the switch circuit TSW8-i. It is output to one I / O terminal (one PKG external terminal of the semiconductor device). The selection of any one of the I / O terminals is performed by the third register Reg. 3 differs for each memory chip. Since the memory chip of one layer includes four systems of compression 8 circuits C8-0 to C8-3, four compression results are output. The selection of the four I / O terminals output from the four compression 8 circuits C8-0 to C8-3 is determined by the third register Reg. 3 is controlled uniformly.

  In case 2, as described above, the eight memory chips are mutually exclusive during normal operation, which is a non-test time, whereas the eight memory chips are simultaneously accessed during this test. is required.

  6 to 8 show the 32I / O compression test, the 8I / O compression test, and the input pins (I / O terminals used at the time of writing operation) and outputs in the normal mode, respectively. It is the figure which showed the relationship of a pin (I / O terminal used at the time of read-out operation).

  Referring to FIG. 6, the write operation in the 32 I / O compression test is a batch write of the same data in all layers, and memory chips in all layers of the 0th layer to the 7th layer are selected and 32 I / O terminals are selected. All layers are collectively written using all of DQ0 to DQ31. On the other hand, the read operation is also batch read for all layers, but one I / O terminal is provided for each layer, for example, the 0th layer memory chip is the I / O terminal DQ0, and the first layer memory chip is the I / O terminal DQ1. The second layer memory chip is an I / O terminal DQ2, the third layer memory chip is an I / O terminal DQ3, the fourth layer memory chip is an I / O terminal DQ4, and the fifth layer memory chip is an I / O terminal. The read operation using the terminal DQ5, the sixth layer memory chip using the I / O terminal DQ6, and the seventh layer memory chip using the I / O terminal DQ7.

  Referring to FIG. 7, the write operation in the 8 I / O compression test is batch write for all layers, but four I / O terminals are used per layer, for example, four for the 0th layer memory chip. Using I / O terminals DQ0 to DQ3 (I / O terminal DQ0 of IO group 0, I / O terminal DQ1 of IO group 1, I / O terminal DQ2 of IO group 2, I / O terminal DQ3 of IO group 3) The same data is written, and for the first layer memory chip, the same data is written using the four I / O terminals DQ4 to DQ7. Similarly, four I / O terminals DQ8 to DQ11 are used for the second layer, four I / O terminals DQ12 to DQ15 are used for the third layer, and four are used for the fourth layer. Using the I / O terminals DQ16 to DQ19 of the fifth layer, using the four I / O terminals DQ20 to DQ23 for the fifth layer, and using the four I / O terminals DQ24 to DQ27 for the sixth layer, For the seventh layer, the same data is written using four I / O terminals DQ28 to DQ31. The write data may be the same in each layer, and different data may be written for each layer.

  On the other hand, the reading operation is all-layer batch reading, and four I / O terminals are used for each layer. For example, for the 0th layer memory chip, reading is performed using four I / O terminals DQ0 to DQ3. The first layer memory chip is read using the four I / O terminals DQ4 to DQ7. Similarly, four I / O terminals DQ8 to DQ11 are used for the second layer, four I / O terminals DQ12 to DQ15 are used for the third layer, and four are used for the fourth layer. Using the I / O terminals DQ16 to DQ19 of the fifth layer, using the four I / O terminals DQ20 to DQ23 for the fifth layer, and using the four I / O terminals DQ24 to DQ27 for the sixth layer, The seventh layer is read using four I / O terminals DQ28 to DQ31.

  Referring to FIG. 8, it goes without saying that writing and reading in the normal mode are performed for each layer. That is, in any layer, when writing, a layer (memory chip) is selected and a write operation is performed using 32 I / O terminals DQ0 to DQ31. On the other hand, at the time of reading, after selecting a layer, a reading operation is performed using 32 I / O terminals DQ0 to DQ31.

[Effect of Example]
1. Since the I / O compression test for a plurality of memory chips can be performed in parallel, the time for the I / O compression test can be shortened.

  2. By performing the I / O compression test at the highest compression ratio (using only one terminal with 32 I / O terminals), the tester device driver and comparator need only be compressed, reducing the number of drivers and comparators in the tester device. Cost reduction can be realized.

  3. In the case of a plurality of stacked chips, by testing with different (compressed) data between layers in case 2 described above, interference between layers (noise varies depending on data for each chip (substrate). Parasitic between chips) It is possible to test with the assumption that the models are coupled with each other by capacity. In addition, it is possible to realize a test capable of screening including coupling noise of signals between a plurality of TSV columns in which each signal line pitch is 10 times or more smaller than the outside of the semiconductor device. .

  Next, a memory system according to the present invention will be described with reference to FIG.

  This memory system will be described with reference to the semiconductor device described with reference to FIGS. 1 and 2. The semiconductor device 1000 (or 3000) including eight (layer 0 to layer 7) stacked memory chips, and the semiconductor device 1000 The controller 2000 is connected to each memory chip via a command bus and an I / O bus.

  Four grouped I / O circuits (IO group 0 to IO group 3) in the block diagram in the memory chip (one layer) shown in FIG. 1 and test-related circuit elements (corresponding to each of the four groups) Switch circuit TSW8-0 to TSW8-3 and compression 8 circuit C8-0 to C8-3, compression 32 circuit C32 common to all groups, first register Reg.1 to third Reg.3, etc.) It is included in the front-end interface 1003 of each memory chip. The front end interface 1003 also includes circuit elements other than the test circuit for communicating with the controller 2000.

  A write circuit, a charge transfer control circuit, a sense amplifier, and the like that access the memory cell 1001 to be tested are included in the back-end interface 1002.

  The controller 2000 has an interface with the outside of the memory system, controls the entire system, and also controls the semiconductor device 1000. The control signal issuance circuit 2001 includes a first register Reg. In addition to the issuance of command commands and address signals to the known semiconductor device 1000. 1 to 3 Reg. 3 also has a function of setting information. The above-described tester device may be shared by the controller 2000 (that is, the controller 2000 includes the driver DV and the driver / comparator CP as described with reference to FIG. 2). In this case, the controller 2000 has a well-known BIST (built-in self test) circuit function, and can reduce costs (reducing the area of the BIST circuit) by reducing the number of comparators in the BIST circuit. On the other hand, the aforementioned tester device may be connected to the outside of the memory system. In this case, the I / O bus in the system passes through the data processing circuit 2002 in the controller 2000 as it is and is connected to an external tester device, or the I / O bus in the system is an external terminal (not shown) It is directly connected to a tester device outside the system via The same applies to the command bus in the system.

  This system is mounted on personal computers, communication electronic devices, mobile electronic devices such as automobiles, electronic devices used in other industries, and electronic devices used in consumer products.

  Although the present invention has been described with reference to the embodiments and the modifications thereof, the basic technical idea of the present application is not limited to the above examples. For example, in the embodiments, the semiconductor memory including the I / O compression test function has been described. The basic technical idea of the present application is not limited to this. For example, the present invention provides a semiconductor product such as a CPU (Central Processing Unit), MCU (Micro Control Unit), DSP (Digital Signal Processor), ASIC (Application Specific Integrated Circuit), and ASSP (Application Specific Standard Circuit) including a memory function. Applicable in general. For example, in FIG. 9, a CPU, MCU, DSP, ASSP, or the like can be replaced with a semiconductor device 1000 (or 3000). This is because these functional devices also have a storage function. Therefore, it can be easily understood that the technical idea of the present application is effective not only in a memory system as a single functional product but also in a general system of electronic equipment having many I / Os. That is, the memory chip described in the embodiment can be replaced with a CPU chip, an MCU chip, a DSP chip, and an ASSP chip. The device to which the present invention is applied can be applied to semiconductor devices such as SOC (system on chip), MCP (multichip package), and POP (package on package). The transistor may be a field effect transistor (FET) or a bipolar transistor. In addition to MOS (Metal Oxide Semiconductor), the present invention can be applied to various FETs such as MIS (Metal-Insulator Semiconductor) and TFT (Thin Film Transistor). Transistors other than FETs may be used. A part of the bipolar transistor may be included. A P-channel transistor or a PMOS transistor is a typical example of a first conductivity type transistor, and an N-channel transistor or an NMOS transistor is a typical example of a second conductivity type transistor. Furthermore, the semiconductor substrate is not limited to a P-type semiconductor substrate, and may be an N-type semiconductor substrate, a semiconductor substrate having an SOI (Silicon on Insulator) structure, or another semiconductor substrate.

  In addition, the semiconductor device may be a semiconductor device in which a plurality of memory chips are not stacked as shown in FIG. 11, but a plurality of memory chips are arranged in parallel in a plane as described in FIG.

  Further, the circuit formats of the switch circuits TSW8-0 to TSW8-3, the compression 8 circuits C8-0 to C8-3, the compression 32 circuit C32, and the like are not limited to the circuit formats according to the above-described embodiments.

  Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various modifications and changes that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

1000, 3000 semiconductor device 201 memory chip 300 test circuit IOC I / O circuits NSW8-0~NSW8-3 normal mode switch circuit TSW8-0~TSW8-3 switch circuit TSW8 ₁ -0 switch circuit C32 32I / O compression circuit ( 32 compression circuits)
TSW32 switch circuit TSW32-W switch circuit C8-0 to C8-3 compression 8 circuit Cntl. cir. Control circuit Test. cir. Test control circuit

Claims (11)

Including a first chip and a second chip;
The plurality of I / O terminals included in the first chip and the plurality of I / O terminals included in the second chip are connected in common,
The first and second chips are respectively
In the test mode, an I / O that outputs one compression result obtained by compressing each data of the plurality of internal data buses to one first I / O terminal among the plurality of I / O terminals. An O compression circuit;
Among the plurality of I / O terminals, the number of the first I / O terminal of the first chip and the number of the first I / O terminal of the second chip are different from each other. Including a number setting register for setting the number of the first I / O terminal, and a test control circuit for controlling the I / O compression circuit,
Each of the first and second chips passes through the first I / O terminal which is different for each chip by the I / O compression circuit activated by the test control circuit in the test mode. The semiconductor device is characterized in that corresponding data is input or output in parallel with the outside of the semiconductor device in parallel.   The first chip and the second chip have a stacked structure, and each of the plurality of I / O terminals of the first chip and the plurality of I / O terminals of the second chip has through electrodes. The semiconductor device according to claim 1, wherein the semiconductor devices are connected in common. The I / O compression circuit receives a plurality of signals from the plurality of internal data buses, and outputs a first compression result in the test mode and in the read mode, and a first electrically connected in the test mode. And a switch circuit of
The semiconductor device according to claim 1, wherein the first switch circuit is connected between the plurality of I / O terminals and one output node of the logic circuit.   The I / O compression circuit includes a second switch circuit that electrically connects one output node of the logic circuit and a plurality of input nodes of the logic circuit in the test mode and the write mode, respectively. The semiconductor device according to claim 3. The I / O compression circuit is a plurality of first I / O compression circuits respectively corresponding to a plurality of groups obtained by dividing the plurality of I / O terminals into a plurality of groups;
Each of the plurality of first I / O compression circuits receives a plurality of signals of the plurality of internal data buses respectively corresponding to the plurality of groups, and is assigned to the plurality of groups in the test mode and the read mode. A first logic circuit that outputs the corresponding one compression result, and a connection between the plurality of I / O terminals respectively corresponding to the plurality of groups and one output node of the first logic circuit. And a first switch circuit that electrically connects the one output node to any one of the plurality of I / O terminals respectively corresponding to the plurality of groups in the test mode. The semiconductor device according to claim 1, wherein the semiconductor device is characterized.   The first I / O compression circuit electrically connects one output node of the first logic circuit and a plurality of input nodes of the first logic circuit in the test mode and the write mode, respectively. The semiconductor device according to claim 5, further comprising a second switch circuit. The test control circuit further includes a compression rate setting register for changing the compression rate of the data,
The I / O compression circuit includes a second I / O compression circuit that is the first compression ratio for the plurality of I / O terminals, one of which is selected by the compression ratio setting register. A plurality of first I / O compression circuits each corresponding to the plurality of groups, the second compression ratio being lower than the first compression ratio;
The second I / O compression circuit receives a plurality of signals from the plurality of internal data buses and outputs the one compression result in the test mode and the read mode, and the plurality of the plurality of internal data buses. An I / O terminal is connected between one output node of the second logic circuit and one output node of the second logic circuit is connected to any one of the plurality of I / O terminals in the test mode. The semiconductor device according to claim 5, further comprising a third switch circuit electrically connected to the first switch circuit. A plurality of I / O terminals included in the first chip and a plurality of I / O terminals included in the second chip are connected in common and include a first chip and a second chip, respectively. An I / O compression test method for a semiconductor device connected to a plurality of external I / O terminals of a semiconductor device communicating with the outside,
After the power supply to the semiconductor device, the first and second chips recognize or set different first and second information,
Accessing the first and second chips, which are accessed by exclusive control in the non-test mode, simultaneously in the test mode;
The first test result output from the first chip to the first I / O terminal selected by the first information is the first test result of one of the corresponding external I / O terminals. A first comparison with an expected value outside the semiconductor device via the external I / O terminal of 1,
The second test result output to the second I / O terminal selected by the second information by the second chip is used as the one of the corresponding external I / O terminals. A second comparison is made with the expected value outside the semiconductor device via one second external I / O terminal different from the first external I / O terminal,
A method for I / O compression testing of a semiconductor device, wherein the first and second comparisons are performed simultaneously and in parallel.   The plurality of the first comparisons and the plurality of the second comparisons are made different from each other by the corresponding first and second information, respectively. The external I / O terminal, and the plurality of first external I / O terminals different from each other and the plurality of second external I / O terminals are different from each other. Semiconductor device I / O compression test method.   A system comprising: the semiconductor device according to claim 1; and a controller connected to the semiconductor device via a command bus and an I / O bus and controlling the semiconductor device. The system according to claim 10, wherein the controller has a function of setting a number setting register of the semiconductor device.

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