JPH09259600A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device having a data compression function and capable of preventing a decline in integration caused by the data compression function. SOLUTION: Cell information of a large number of storage cells, to which identical data is written, is read to a large number of bit lines BL, the cell information which is read to the bit lines BL is read to a large number of data buses DB, and a large amount of cell information which is read to the data buses DB is logically processed to compress into one signal; therefore, a data compression performance test, which collectively decides operations of a large number of storage cells, is carried out. The bit lines BL are simultaneously connected to each of the data buses DB. The storage device is provided with a multiple selection circuit 21, which outputs cell information which is read to the bit lines BL, to a common data bus DB, and a decision circuit 22 which collectively decides operations of a large number of storage cells by comparing an output voltage of each data bus DB with a reference voltage Vr which is set beforehand.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a data compression test mode function.

In recent years, semiconductor memory devices are becoming more highly integrated and larger in capacity. Further, in the semiconductor memory device, an operation test for testing whether or not all memory cells normally operate is performed before shipment. A semiconductor memory device having a large capacity has a data compression test mode for compressing and outputting read data because the time required for the operation test becomes long. Then, while shortening the test time in the operation test in the data compression test mode, it is necessary to reduce the scale of the circuit used only in the operation test in the data compression test mode to achieve higher integration.

[0003]

2. Description of the Related Art FIG. 5 shows a conventional DRAM data read circuit having a data compression test mode function. This data read circuit has 4-bit output data DQ0-
An example of a × 4 product that outputs DQ3 is shown.

A sense amplifier 1 is connected to each pair of bit lines BL0, BL0 to BL7, and BL7. The bit lines BL0, BL0 to BL7, and BL7 are connected to the data buses DB0, DB0 to DB7, and DB7 via transfer gates Tg, respectively.

The bit lines BL0 and BL0 to BL
3, the transfer gate Tg connected to the bar BL3 is opened / closed by a signal obtained by inverting the NOR logic signal of the column selection signal CL0 and the test mode signal TEST that becomes H level in the test mode by the inverter circuit. The bit line BL
4, the transfer gates Tg connected to the BL4 to BL7 and the bar BL7 are opened and closed by a signal obtained by inverting a NOR logic signal of the column selection signal CL1 and the test mode signal TEST by an inverter circuit.

Therefore, in the test mode, the transfer gates Tg are turned on at the same time, and in the normal mode, the column selection signal C is set.
Based on L0 and CL1, bit line BL0 and bar BL0
~ BL3, transfer gate Tg connected to bar BL3,
Any one of the transfer gate Tg connected to the bit line BL4, the bars BL4 to BL7, and the bar BL7 becomes conductive.

The bit lines BL0 and BL0 to BL
A large number of memory cells (not shown) are connected to each of 7 and bar BL7, and cell information is read from the memory cells selected based on the selection of the word line.
Amplified by

The bit lines BL0 and BL0 to BL
7, the cell information read to the bar BL7 is transferred to the data bus DB0 and the bar DB via the transfer gate Tg, respectively.
0 to DB7, output to the bar DB7.

Data bus DB0, bars DB0-DB
7 and bar DB7, a larger number of bit line pairs are connected, and each of these bit line pairs is 4 by a column selection signal.
Selected column by column.

Data bus DB0, bars DB0-DB
7, the cell information read to the bar DB7 is input to the sense buffers SB0 to SB7, respectively. The sense buffers SB0 to SB7 amplify the input cell information and output signals CM0, CM0 to CM7, CM.
7, and outputs to the selector 2 and the data compression circuit 3.

The selector 2 is activated during a normal read operation based on the test mode signal TEST, and outputs the output signal CM of the sense buffers SB0 to SB3.
0, bar CM0 to CM3, bar CM3, and output signals CM4, CM4 to CM4 of the sense buffers SB4 to SB7.
Either the CM7 or the bar CM7 is used as an address signal AD
It is selected based on D and output to the output circuits 4a to 4d.

A concrete structure of the selector circuit 2 is shown in FIG. Output signal C of the sense buffers SB0 to SB3
M0, CM0 to CM3 and CM3 are output to the output circuits 4a to 4d via transfer gates Tgs1 and output signals C from the sense buffers SB4 to SB7.
M4, CM4 to CM7, and CM7 are output to the output circuits 4a to 4d via transfer gates Tgs2, respectively.

The transfer gate Tgs1 is opened and closed based on the NOR logic signal of the test mode signal TEST and the address signal ADD, and the transfer gate Tgs2 is opened and closed with the test mode signal TEST and an inverted signal of the address signal ADD. It is opened / closed based on the NOR logic signal.

Therefore, when the test mode signal TEST becomes H level in the test mode, the transfer gates Tgs1,
Tgs2 becomes non-conductive, and the output signal of the selector 2 becomes high impedance.

When the test mode signal TEST goes low, one of the transfer gates Tgs1 and Tgs2 becomes conductive based on the address signal ADD, and the input signal C
M0, bar CM0-CM3, bar CM3, and CM4,
Either one of the bars CM4 to CM7 and the bar CM7 is output from the selector 2.

The output circuits 4a to 4d amplify the signal input from the selector 2 and output it as 4-bit output data DQ0 to DQ3. The data compression circuit 3 is activated based on the test mode signal TEST, and outputs the output signal C of the sense buffers SB0 to SB7.
M0, CM0 to CM7, and CM7 are compressed into 1-bit signals and output to the output circuit 4a.

An example of the data compression circuit 3 is shown in FIG. Output signal CM of the sense buffers SB0 to SB7
0 to CM7 are input to the NAND circuit 5a, and the output signals / CM0 to CM7 of the sense buffers SB0 to SB7 are input to the NAND circuit 5b.

The output signals of the NAND circuits 5a and 5b are input to the NAND circuits 5c and 5d, respectively. The output signal of the NAND circuit 5c is output to the output circuit 4a as an output signal CMT via the transfer gate Tg.

The output signal of the NAND circuit 5d is output through the inverter circuit 6a and the transfer gate Tg.
The bar CMT is output to the output circuit 4a. The test mode signal TEST is input to the transfer gate Tg. Then, the test mode signal TEST becomes H
When it becomes the level, the transfer gate Tg becomes conductive, and the output signals CMT and CMT of the data compression circuit 3 are output to the output circuit 4a.
Is output to

In the output circuit 4a, the output signal CMT of the data compression circuit 3 is input to the gate of the output transistor Tr1 formed of an N-channel MOS transistor via the two-stage inverter circuit 6b, and the output signal The output transistor T, which is composed of an N-channel MOS transistor via the inverter circuit 6c having a two-stage CMT
Input to the gate of r2.

The output transistors Tr1 and Tr2 are connected in series between the power supply Vcc and the ground GND, and the output data DQ0 is output from the connection point. In the data compression circuit 3 thus configured, the sense buffer SB0
~ SB7 output signal CM0, bar CM0 to CM7, bar CM7 match, that is, output signal CM0 to CM
When 7 and the output signals CM0 to CM7 match, one of the output signals of the NAND circuits 5a and 5b becomes H level and the other becomes L level.

Then, since the output signals of the NAND circuits 5c and 5d become H level, the output transistor Tr1 is turned on and the output transistor Tr2 is turned off,
The output data DQ0 becomes H level.

On the other hand, when the output signals CM0, CM0-CM7, CM7 of the sense buffers SB0-SB7 do not match, the output signals of the NAND circuits 5a, 5b both become H level.

Then, since the output signals of the NAND circuits 5c and 5d become L level, the output transistor Tr1 is turned off and the output transistor Tr2 is turned on,
The output data DQ0 becomes L level.

Therefore, if the output data DQ0 is at the H level, the output signals CM of the sense buffers SB0 to SB7.
0, the bar CM0 to CM7, and the bar CM7 are determined to match, and if the output data DQ0 is at the L level, the output signals CM0 and the bar CM of the sense buffers SB0 to SB7
It is determined that 0 to CM7 and bar CM7 do not match.

In the data read circuit configured as described above, in the normal read mode, one of the column selection signals CL0 and CL1 becomes H level, and the same as the bit lines BL0, BL0 to BL3, and bar BL3. BL
4, data bus DB0, bar DB0-DB3, and bar DB3 from any one of bars BL4 to BL7 and bar BL7,
The cell information is read out to any of the DB 4, bar DB 4 to DB 7, and bar DB 7.

Data bus DB0, bars DB0-DB7,
The cell information read to the bar DB7 is amplified by the sense buffers SB0 to SB7, and the output signals CM0 and C are amplified.
M0 to CM7 and bar CM7 are output.

For example, data bus DB0 and bars DB0-D
When cell information is read out in B3, bar DB3,
The selector 2 outputs the output signals CM0, CM0 to CM3 and CM3 from the sense buffers SB0 to SB3 to the output circuit 4
a to 4d.

The output circuits 4a-4d are sense buffers SB.
Output data DQ0 to DQ3 based on the output signals CM0 to CM0, CM0 to CM3 and CM3 of CM0 to SB3 are output. Further, when the cell information is read out to the data bus DB4, the bars DB4 to DB7, and the bar DB7, the selector 2 outputs the output signals CM4 to the sense buffers SB4 to SB7.
Output circuits 4a to 4d for bar CM4 to CM7 and bar CM7
Output to

The output circuits 4a-4d are sense buffers SB.
4 to SB7 output signal CM4, bars CM4 to CM7, and output data DQ0 to DQ3 based on bar CM7. On the other hand, in the test mode, prior to the operation test,
The same data is written in all the memory cells, and then the data is read to determine whether or not each memory cell is operating normally.

The column selection signals CL0 and CL1 are both H
It becomes the level, and the bit line BL0, the bars BL0 to BL7,
The cell information read to bar BL7 is the data bus DB
0, DB0 to DB7, and output to DB7.

Data bus DB0, bars DB0-DB7,
The cell information read to the bar DB7 is amplified by the sense buffers SB0 to SB7, and the output signals CM0 and C are amplified.
M0 to CM7 and bar CM7 are output to the data compression circuit 3.

In the data compression circuit 3, the sense buffer S
B0 to SB7 output signals CM0, bars CM0 to CM7,
Output signal CM based on whether or not the bars CM7 match
The T, bar CMT is output to the output circuit 4a.

If the output signal DQ0 of the output circuit 4a is at the H level, the bit lines BL0 and BL0 to BL0 to BL
7, it is determined that the cell information read from the bar BL7 matches, and if the output signal DQ0 is at L level, the bit line B
It is determined that the cell information read from L0, bar BL0 to BL7, and bar BL7 does not match.

By such a test operation by data compression, although normally only 4 bits of cell information can be obtained in the × 4 product, it is necessary to perform an operation test because the 8 bits of cell information can be collectively judged. Time is reduced.

[0036]

Since the data read circuit as described above is a × 4 product which outputs the 4-bit output signals DQ0 to DQ3 in the normal read operation,
Although only four pairs of data buses and four sense buffers are required, eight pairs of data buses DB0 and DB0 to DB0 are required to perform an operation test for compressing 8-bit data.
DB7, DB7, and eight sense buffers SB0 to SB0
It is equipped with SB7.

Therefore, the data bus DB0 and the bar DB0 to DB0
DB7, bar DB7 and sense buffers SB0 to SB7
The layout area for forming the semiconductor device increases, and the integration degree decreases.

Further, the memory cell array has a large capacity,
In addition, in a DRAM in which output data has multiple bits, if 16-bit or 32-bit read data is compressed to 1 bit in order to shorten the operation test time, the data bus and the data bus required only in the data compression test mode are set. The number of sense buffers further increases.

Therefore, as the data compression degree is increased, the number of unnecessary data buses and sense buffers is increased in the normal state, and the integration degree is lowered.

An object of the present invention is to provide a semiconductor memory device which has a data compression function and can prevent a decrease in the degree of integration due to the data compression function.

[0041]

FIG. 1 is a diagram for explaining the principle of claim 1. That is, the cell information of a large number of memory cells in which the same data is written is read to a large number of bit lines BL, the cell information read to the bit lines BL is read to a large number of data buses DB, and the data A data compression operation test is performed in which the operations of a large number of memory cells are collectively determined by logically processing a large number of cell information read out on the bus DB and compressing them into a single signal. Multiple selection circuit 21 that simultaneously connects a plurality of bit lines BL to each of the data buses DB and outputs the cell information read out to the plurality of bit lines BL to a common data bus DB.
By comparing the output voltage of each data bus DB with a preset reference voltage Vr, the operation of a large number of memory cells whose cell information has been read out to the data bus DB is collectively determined. The determination circuit 22 is provided.

According to a second aspect of the present invention, the determination circuit determines whether or not the output signals of the plurality of comparators for comparing the output voltage of each data bus with the reference voltage match. And a logic circuit for judging.

According to another aspect of the present invention, the reference voltage is at least one of an output voltage of the data bus when a plurality of cell information read out to the data bus coincides with a plurality of cell information read out to the data bus. It is set to an intermediate level with the output voltage of the data bus when the two do not match.

(Operation) In claim 1, the multiplex selection circuit 21
As a result, a plurality of bit lines BL are simultaneously connected to a large number of data buses DB, and a plurality of cell information are output to a common data bus DB. The determination circuit 22 outputs the output voltage of each data bus DB and the reference voltage Vr. By comparing with, it is determined whether the plurality of read cell information is the same data, and it is collectively determined whether the memory cell in which the cell information is written is operating normally. It

According to a second aspect of the present invention, the output voltages of the plurality of data buses and the reference voltage are compared by the plurality of comparators, it is determined whether the output signals of the plurality of comparators match, and the signals are read out. It is determined whether multiple pieces of cell information are the same data,
It is collectively determined whether or not the memory cell in which the cell information is written is operating normally.

In the third aspect, when at least one of the plurality of cell information read out to the data bus does not match, the output signal of the comparator to which the output signal of the data bus is input is inverted. If it is determined whether the output signals of the comparators match, it is determined whether the read cell information is the same data, and the memory cell in which the cell information is written operates normally. It is collectively determined whether or not there is.

[0047]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 shows a D embodying the present invention.
The data read circuit of RAM is shown. This data read circuit has the same 4-bit output data D as the conventional example.
An example of a x4 product that outputs Q0 to DQ3 is shown, and the same components as those in the conventional example will be described with the same reference numerals.

The bit lines BL0, BL0, BL
4, the bar BL4 is connected to the data buses DB0 and DB0 via the transfer gates Tg, and the bit lines BL1, BL1, BL5 and BL5 are connected to the data buses DB1 and DB1 via the transfer gates Tg.
Connected to.

Bit line BL2, bar BL2, BL
6, the bar BL6 are connected to the data buses DB2, DB2 via the transfer gates Tg, and the bit lines BL3, BL3, BL7, BL7 are connected to the data buses DB3, DB3 via the transfer gates Tg.
Connected to.

The bit lines BL0 and BL0 to BL
3, bar BL3, data bus DB0, bars DB0-D
Transfer gate Tg interposed between B3 and DB3 of bar
Is a test mode signal TEST and a column selection signal CL0.
The bit line B is opened / closed by an inverted signal of NOR logic with
The transfer gate Tg interposed between L4, BL4 to BL7 and BL7 and the data buses DB0, DB0 to DB3 and DB3 is an inverted signal of the NOR logic of the test mode signal TEST and the column selection signal CL1. Is opened and closed.

The bit lines BL0, BL0 to BL
A large number of memory cells (not shown) are connected to each of 7 and bar BL7, and cell information is read from the memory cells selected based on the selection of the word line.
Amplified by

The bit lines BL0 and BL0 to BL
7, the cell information read to the bar BL7 is transferred to the data bus DB0 and the bar DB via the transfer gate Tg, respectively.
It is output to 0 to DB3 and DB3.

Data bus DB0, bars DB0-DB
3, a larger number of bit line pairs are connected to the DB3, and each of these bit line pairs is 4 by a column selection signal.
Selected column by column.

Data bus DB0, bars DB0-DB
3, the cell information read into the bar DB3 is output to the sense buffers SB0 to SB3 and the data compression circuit 11. The sense buffers SB0 to SB3 output the output signals obtained by amplifying the inputted cell information to the output circuits 4a to 4d via the transfer gate Td, respectively.

A test mode signal TEST which becomes H level in the test mode is input to the transfer gate Td through the inverter circuit 12a. Therefore, when the test mode signal TEST becomes L level during the normal read operation, the transfer gate Td becomes conductive.

Further, the test mode signal TEST is input to the data compression circuit 11, and when the test mode signal TEST becomes H level in the test mode, the data compression circuit 11 is activated. Then, the output signal of the data compression circuit 11 is output to the output circuit 4a.

A concrete structure of the data compression circuit 11 is shown in FIG. The cell information read to the data buses DB0 to DB3 is input to the + side input terminals of the comparators 13a to 13d, respectively, and the cell information read to the data bus bars DB0 to DB3 is the comparator. 13e-13
It is input to the + side input terminal of h.

The reference voltage Vcc.3 / 4 generated by dividing the power supply Vcc into 3/4 by a resistor is input to the-side input terminals of the comparators 13a to 13d. The comparators 13e-1
A reference voltage Vcc · 1/4 generated by dividing the power supply Vcc into ¼ by a resistor is input to the − side input terminal of 3h.

Therefore, if the output signals of the data buses DB0 to DB3 have a potential higher than Vcc.3 / 4, the comparator 13a.
The output signal of ~ 13d becomes H level. In addition, the output signals of the data bus bar DB0 to bar DB3 are Vcc.1 / 4.
When the potential becomes lower, the output signals of the comparators 13e to 13h become L level.

The output signals of the comparators 13a to 13d are N
It is input to the AND circuit 14a, and the comparators 13e to 13e.
The output signal of h is input to the NAND circuit 14b. The output signal of the NAND circuit 14a is the NAND circuit 14a.
c and 14d, which are respectively input to the NAND circuit 14
The output signal of b is also input to the NAND circuits 14c and 14d, respectively.

Then, the output signal of the NAND circuit 14c is output to the output circuit 4a, and at the same time, the N signal is output.
The output signal of the AND circuit 14d is input to the output circuit 4a via the inverter circuit 12b.

The comparators 13a to 13h have the same structure and are composed of a differential circuit including MOS transistors as shown in FIG. The gate of the N-channel MOS transistor Tr3 whose gate is connected to its drain serves as the + side input terminal, and the gate of the N-channel MOS transistor Tr4 whose output terminal To is connected to its drain is- It becomes the side input terminal.

The gate of the N-channel MOS transistor Tr5 connected between the sources of the transistors Tr3 and Tr4 and the ground GND is connected to the test mode signal TE.
ST is input.

When test mode signal TEST attains the H level, this differential circuit is activated. When the input level of the + side input terminal becomes higher than the input level of the − side input terminal, an output signal of H level is output from the output terminal To, and the input level of the + side input terminal is higher than the input level of the − side input terminal. When it becomes low, an L level output signal is output from the output terminal To.

In the data read circuit configured as described above, in the normal read mode, the test mode signal TEST becomes L level, the data compression circuit 11 is inactivated, and the transfer gate Td is rendered conductive.

In this state, the column selection signals CL0, CL
1 becomes H level and bit lines BL0, BL0 to BL3, BL3 and BL4, BL4.
~ Data bus DB from either BL7 or BL7
0, bar DB0 to DB3, cell information is read out to bar DB3.

Data bus DB0, bars DB0-DB3,
The cell information read to the bar DB3 is amplified by the sense buffers SB0 to SB3 and output to the output circuits 4a to 4d.

The output circuits 4a-4d are the sense buffer S.
Output data DQ0-D based on the output signals of B0-SB3
Output Q3. On the other hand, in the test mode, the same data is written in all memory cells prior to the operation test.
This write data is data in which the bit lines BL0 to BL7 are at H level and the same bars BL0 to BL7 are at L level.

Then, the test mode signal TEST becomes H level, the transfer gate Td becomes non-conductive, and the data compression circuit 11 is activated. In this state, the column selection signals CL0 and CL1 are both at the H level, and the cell information read on the bit line BL0, the bars BL0 to BL7 and the bar BL7 is the data bus DB0 and the bars DB0 to DB3.
It is output to the bar DB3.

Data bus DB0, bars DB0-DB3,
The cell information read into the bar DB3 is output to the data compression circuit 11. When the read cell information matches, the data buses DB0 to DB3 are at the H level, that is, almost at the power supply Vcc level, and the data bus bar DB0.
~ Bar DB3 is at L level, that is, almost ground GND
Level.

Then, the output signals of the comparators 13a to 13d become H level, and the output signals of the comparators 13e to 13h become L level. The output signal of the NAND circuit 14a becomes L level, and the output signal of the NAND circuit 14b becomes H level.

Then, the output signals of the NAND circuits 14c and 14d attain the H level, and the output signal of the inverter circuit 12b attains the L level. As a result, the output signal DQ0 of the output circuit 4a becomes H level, and the bit lines BL0, B
The cell information read in L0 to BL7 and the bar BL7 match, and it can be determined that all the selected memory cells are operating normally.

When at least one of the read cell information does not match, at least a pair of bit lines is read with the cell information inverted from the other bit lines. For example, the bit line BL0 is at the L level and the same bar BL0 is at the H level, so that the other bit lines BL1 and BL1 to BL1
7, when the cell information read to the bar BL7 does not match, the bit line BL is set to the data bus DB0 and the bar DB0.
Since different cell information is output from 0, bar BL0 and the same BL4, bar BL4, data bus DB0, bar DB
The potential of 0 is an intermediate potential between the power source Vcc and the ground GND.

Then, the output signal of the comparator 13a becomes L level and the output signal of the comparator 13e becomes H level.
The output signals of the NAND circuits 14a and 14b become H level, the output signals of the NAND circuits 14c and 14d become L level, and the output signal of the inverter circuit 12b becomes H level.

As a result, the output signal DQ0 of the output circuit 4a
Goes to L level, and bit lines BL0 and BL0 to BL
7, the cell information read out to the bar BL7 does not match, and it is possible to determine that any one of the selected memory cells has a defect.

Further, other bit lines BL1 and bars BL1 to BL1
Even when the cell information read out to either BL7 or BL7 becomes inconsistent, one of the output signals of the comparators 13a to 13d becomes L level, and the same operation as above is performed. Bit line BL0, bar BL0 to BL7, bar BL
Even when two or more pieces of cell information in the cell information read in 7 do not match, at least one or more of the output signals of the comparators 13a to 13d become L level, and the same operation is performed.

The data read circuit configured as described above can obtain the following operational effects. (A) Multiple selection of column selection signals CL0 and CL1
Eight pairs of bit lines BL0, BL0 to BL7, BL
Select 7 and store the cell information in 4 pairs of data bus DBs.
0, bar DB0 to DB3, and bar DB3, the data bus DB0 and bar DB0 to DB0 when the cell information does not match and when the cell information matches.
3, The output voltage of DB3 is different. Therefore, by detecting changes in the output voltages of the data buses DB0, DB0 to DB3, and DB3, it is possible to detect inconsistencies in cell information. (B) 4 pairs of data buses DB0 and D required for 4 x products
B0 to DB3, bar DB3, and four sense buffers S
An operation test for compressing 8-bit data can be performed with B0 to SB3. (C) Since the operation test can be performed while compressing the data larger than the number of the data buses and the sense buffers without increasing the number of the data buses and the sense buffers, the time required for the operation test can be shortened, In addition, it is possible to prevent an increase in circuit scale. (D) By connecting three or more pairs of bit lines to a pair of data buses at the same time and simultaneously outputting three or more pieces of cell information to a common data bus, further multi-bit data compression can be performed. it can. At this time, it is necessary to change the setting of the reference voltage input to the comparator.

The above-described embodiment can be applied to SRAM and other semiconductor memory devices.

[0079]

As described above in detail, the present invention can provide a semiconductor memory device which has a data compression function and can prevent a decrease in the degree of integration due to the data compression function.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing one embodiment.

FIG. 3 is a circuit diagram showing a data compression circuit according to an embodiment.

FIG. 4 is a circuit diagram showing a comparator.

FIG. 5 is a circuit diagram showing a conventional example.

FIG. 6 is a circuit diagram showing a conventional data compression circuit and output circuit.

FIG. 7 is a circuit diagram showing a conventional selector.

[Explanation of symbols]

 21 multiple selection circuit 22 determination circuit BL bit line DB data bus Vr reference voltage

Claims (3)

[Claims] 1. The cell information of a large number of memory cells in which the same data is written is read to a large number of bit lines, the cell information read to the bit lines is read to a large number of data buses, and is read to the data bus. A semiconductor memory device having a data compression test mode in which the operation of a large number of storage cells is collectively determined by logically processing a large number of stored cell information and compressing it into a single signal. , And simultaneously connect a plurality of bit lines to the cell information read out to the plurality of bit lines,
By comparing the output voltage of each of the data buses and a preset reference voltage with a multiplex selection circuit for outputting to a common data bus, a plurality of storage cells whose cell information has been read out to the data bus are compared. A semiconductor memory device, comprising: a determination circuit for collectively determining operations. 2. The determination circuit includes a plurality of comparators that compare the output voltage of each of the data buses with the reference voltage, and a logic that determines whether the output signals of the plurality of comparators match. The semiconductor memory device according to claim 1, wherein the semiconductor memory device comprises a circuit. 3. The reference voltage is such that at least one of the output voltage of the data bus when a plurality of cell information read out to the data bus matches with at least one of the plurality of cell information read out to the data bus. 3. The semiconductor memory device according to claim 2, wherein the semiconductor memory device is set at an intermediate level with respect to the output voltage of the data bus when it becomes low.