TW200507215A - Semiconductor package substrate with protective layer on pads formed thereon and method for fabricating the same - Google Patents

Semiconductor package substrate with protective layer on pads formed thereon and method for fabricating the same

Info

Publication number
TW200507215A
TW200507215A TW092122208A TW92122208A TW200507215A TW 200507215 A TW200507215 A TW 200507215A TW 092122208 A TW092122208 A TW 092122208A TW 92122208 A TW92122208 A TW 92122208A TW 200507215 A TW200507215 A TW 200507215A
Authority
TW
Taiwan
Prior art keywords
layer
pads
semiconductor package
resist layer
package substrate
Prior art date
Application number
TW092122208A
Other languages
Chinese (zh)
Other versions
TWI224387B (en
Inventor
Shih-Ping Hsu
Kun-Chen Tsai
Original Assignee
Phoenix Prec Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Phoenix Prec Technology Corp filed Critical Phoenix Prec Technology Corp
Priority to TW092122208A priority Critical patent/TWI224387B/en
Application granted granted Critical
Publication of TWI224387B publication Critical patent/TWI224387B/en
Publication of TW200507215A publication Critical patent/TW200507215A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Manufacturing Of Printed Wiring (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A semiconductor package substrate with a protective layer on pads formed thereon and a method for fabricating the same are proposed. An insulating layer is formed with a plurality of blind vias to expose an inner trace structure underneath the insulating layer. After a conductive film is formed on the surface of the insulating layer and the blind vias, a first resist layer is formed thereon with a plurality of openings to expose the conductive film. A patterned trace structure including a plurality of pads is formed within the openings and conductive blind vias are formed within the blind vias of the insulating layer by an electroplating process, wherein at least a pad is electrically connected to the conductive blind via. A second resist layer is partially formed on the patterned trace structure and a barrier metal layer is partially formed on the pads without covering the second resist layer by an electroplating process. After the second resist layer, the first resist layer, and the conductive film underneath the resist layer are removed, a solder mask is formed over the substrate with a plurality of openings formed to expose the pads. An organic solderability preservative layer is formed on the pads without covering the barrier metal layer, for providing a semiconductor package substrate with pads covered by either a barrier metal layer or an organic solderability preservative layer.
TW092122208A 2003-08-13 2003-08-13 Semiconductor package substrate with protective layer on pads formed thereon and method for fabricating the same TWI224387B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW092122208A TWI224387B (en) 2003-08-13 2003-08-13 Semiconductor package substrate with protective layer on pads formed thereon and method for fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW092122208A TWI224387B (en) 2003-08-13 2003-08-13 Semiconductor package substrate with protective layer on pads formed thereon and method for fabricating the same

Publications (2)

Publication Number Publication Date
TWI224387B TWI224387B (en) 2004-11-21
TW200507215A true TW200507215A (en) 2005-02-16

Family

ID=34568475

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092122208A TWI224387B (en) 2003-08-13 2003-08-13 Semiconductor package substrate with protective layer on pads formed thereon and method for fabricating the same

Country Status (1)

Country Link
TW (1) TWI224387B (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI392405B (en) * 2009-10-26 2013-04-01 Unimicron Technology Corp Circuit structure
TWI405312B (en) * 2009-07-17 2013-08-11 Advanced Semiconductor Eng Semiconductor package structure, carrier thereof and manufacturing method for the same
TWI451550B (en) * 2011-01-14 2014-09-01 Unimicron Technology Corp Package substrate and method of forming same
TWI470757B (en) * 2009-10-22 2015-01-21 Unimicron Technology Corp Package substrate and fabrication method thereof
TWI762279B (en) * 2021-04-21 2022-04-21 翔名科技股份有限公司 Semiconductor part protective coating and method of fabricating the same
TWI802973B (en) * 2021-08-24 2023-05-21 矽品精密工業股份有限公司 Substrate structure

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI405312B (en) * 2009-07-17 2013-08-11 Advanced Semiconductor Eng Semiconductor package structure, carrier thereof and manufacturing method for the same
TWI470757B (en) * 2009-10-22 2015-01-21 Unimicron Technology Corp Package substrate and fabrication method thereof
TWI392405B (en) * 2009-10-26 2013-04-01 Unimicron Technology Corp Circuit structure
TWI451550B (en) * 2011-01-14 2014-09-01 Unimicron Technology Corp Package substrate and method of forming same
TWI762279B (en) * 2021-04-21 2022-04-21 翔名科技股份有限公司 Semiconductor part protective coating and method of fabricating the same
TWI802973B (en) * 2021-08-24 2023-05-21 矽品精密工業股份有限公司 Substrate structure

Also Published As

Publication number Publication date
TWI224387B (en) 2004-11-21

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees