TW200520189A - Electric connection structure of semiconductor package substrate and method for fabricating the same - Google Patents

Electric connection structure of semiconductor package substrate and method for fabricating the same

Info

Publication number
TW200520189A
TW200520189A TW092134979A TW92134979A TW200520189A TW 200520189 A TW200520189 A TW 200520189A TW 092134979 A TW092134979 A TW 092134979A TW 92134979 A TW92134979 A TW 92134979A TW 200520189 A TW200520189 A TW 200520189A
Authority
TW
Taiwan
Prior art keywords
layer
fabricating
semiconductor package
electric connection
protective metal
Prior art date
Application number
TW092134979A
Other languages
Chinese (zh)
Other versions
TWI223426B (en
Inventor
Gin-Win Hu
Chien-Chih Chen
Tai-Fu Sun
Shing-Ru Wang
Original Assignee
Phoenix Prec Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Phoenix Prec Technology Corp filed Critical Phoenix Prec Technology Corp
Priority to TW92134979A priority Critical patent/TWI223426B/en
Application granted granted Critical
Publication of TWI223426B publication Critical patent/TWI223426B/en
Publication of TW200520189A publication Critical patent/TW200520189A/en

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

An electric connection structure of a semiconductor package substrate and a method for fabricating the same are proposed. A conductive layer is formed on an insulating layer of a substrate, and a first patterned resist layer is applied over the conductive layer and formed with first openings to expose the conductive layer. After a pattern circuit layer is formed within the first openings by an electroplating process, a second patterned resist layer is applied over the substrate formed with the circuit layer. And the second resist layer is formed with second openings to expose portions of the circuit layer which are used for pads, wherein the size of the second opening is bigger than the first opening over the pad. A first protective metal layer is formed on the pad within the first opening and a second protective metal layer is formed thereon by an electroplating process, wherein the second protective metal layer is formed like a cap structure for covering the upper and lateral side of the first protective metal layer.
TW92134979A 2003-12-11 2003-12-11 Electric connection structure of semiconductor package substrate and method for fabricating the same TWI223426B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW92134979A TWI223426B (en) 2003-12-11 2003-12-11 Electric connection structure of semiconductor package substrate and method for fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW92134979A TWI223426B (en) 2003-12-11 2003-12-11 Electric connection structure of semiconductor package substrate and method for fabricating the same

Publications (2)

Publication Number Publication Date
TWI223426B TWI223426B (en) 2004-11-01
TW200520189A true TW200520189A (en) 2005-06-16

Family

ID=34546537

Family Applications (1)

Application Number Title Priority Date Filing Date
TW92134979A TWI223426B (en) 2003-12-11 2003-12-11 Electric connection structure of semiconductor package substrate and method for fabricating the same

Country Status (1)

Country Link
TW (1) TWI223426B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI447873B (en) 2011-12-21 2014-08-01 矽品精密工業股份有限公司 Package structure, package substrate and method of forming same

Also Published As

Publication number Publication date
TWI223426B (en) 2004-11-01

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees