JP2005311215A5 - - Google Patents

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JP2005311215A5
JP2005311215A5 JP2004129256A JP2004129256A JP2005311215A5 JP 2005311215 A5 JP2005311215 A5 JP 2005311215A5 JP 2004129256 A JP2004129256 A JP 2004129256A JP 2004129256 A JP2004129256 A JP 2004129256A JP 2005311215 A5 JP2005311215 A5 JP 2005311215A5
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Japan
Prior art keywords
main surface
via hole
forming
pad electrode
wiring layer
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JP2004129256A
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Japanese (ja)
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JP2005311215A (en
JP4544902B2 (en
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Priority to JP2004129256A priority Critical patent/JP4544902B2/en
Priority claimed from JP2004129256A external-priority patent/JP4544902B2/en
Publication of JP2005311215A publication Critical patent/JP2005311215A/en
Publication of JP2005311215A5 publication Critical patent/JP2005311215A5/ja
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Publication of JP4544902B2 publication Critical patent/JP4544902B2/en
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Claims (11)

半導体チップの第１の主面上に形成されたパッド電極と、
前記半導体チップの第１の主面に接着された支持体と、
前記半導体チップの第２の主面から前記パッド電極上に到達するビアホールと、
前記ビアホールよりも小さい開口径を有して前記半導体チップの第２の主面に形成された溝と、
前記ビアホールの側壁及び前記溝内を含む前記半導体チップの第２の主面上に形成された絶縁膜と、
前記ビアホールの底部で露出する前記パッド電極と電気的に接続され、かつ前記絶縁膜を介して前記ビアホールから前記半導体チップの第２の主面上に延びて形成された配線層と、を有することを特徴とする半導体装置。 A pad electrode formed on the first main surface of the semiconductor chip;
A support bonded to the first main surface of the semiconductor chip;
A via hole reaching the pad electrode from the second main surface of the semiconductor chip;
A groove having an opening diameter smaller than that of the via hole and formed in the second main surface of the semiconductor chip;
An insulating film formed on a second main surface of the semiconductor chip including the side wall of the via hole and the inside of the groove;
A wiring layer electrically connected to the pad electrode exposed at the bottom of the via hole and extending from the via hole to the second main surface of the semiconductor chip via the insulating film. A semiconductor device characterized by the above. 半導体チップの第１の主面上に形成されたパッド電極と、A pad electrode formed on the first main surface of the semiconductor chip;
前記半導体チップの第２の主面から前記パッド電極上に到達するビアホールと、A via hole reaching the pad electrode from the second main surface of the semiconductor chip;
前記ビアホールよりも小さい開口径を有して前記半導体チップの第２の主面に形成された溝と、A groove having an opening diameter smaller than that of the via hole and formed in the second main surface of the semiconductor chip;
前記ビアホールの側壁及び前記溝内を含む前記半導体チップの第２の主面上に形成された絶縁膜と、An insulating film formed on a second main surface of the semiconductor chip including the side wall of the via hole and the inside of the groove;
前記ビアホールの底部で露出する前記パッド電極と電気的に接続され、かつ前記絶縁膜を介して前記ビアホールから前記半導体チップの第２の主面上に延びて形成された配線層と、を有することを特徴とする半導体装置。A wiring layer electrically connected to the pad electrode exposed at the bottom of the via hole and extending from the via hole onto the second main surface of the semiconductor chip via the insulating film. A semiconductor device characterized by the above. 前記溝は、前記半導体チップの第２の主面のうち、前記配線層の端部に対応する位置に形成されていることを特徴とする請求項１または請求項２に記載の半導体装置。3. The semiconductor device according to claim 1, wherein the groove is formed at a position corresponding to an end of the wiring layer in the second main surface of the semiconductor chip. 前記配線層を覆い、かつ前記配線層の一部を露出する開口部を有した保護層と、A protective layer that covers the wiring layer and has an opening that exposes a portion of the wiring layer;
前記開口部で露出する前記配線層上に形成された導電端子と、を有することを特徴とする請求項１乃至請求項３のいずれかに記載の半導体装置。The semiconductor device according to claim 1, further comprising: a conductive terminal formed on the wiring layer exposed at the opening. パッド電極が形成された半導体基板を準備し、前記半導体基板の第１の主面に支持体をA semiconductor substrate having a pad electrode formed thereon is prepared, and a support is provided on the first main surface of the semiconductor substrate.
接着する工程と、Bonding, and
前記半導体基板の第２の主面から前記パッド電極上に到達するビアホールを形成すると共に、当該ビアホールよりも小さい開口径を有した溝を、当該半導体基板の第２の主面上に形成する工程と、Forming a via hole reaching the pad electrode from the second main surface of the semiconductor substrate and forming a groove having an opening diameter smaller than the via hole on the second main surface of the semiconductor substrate; When,
前記ビアホールの側壁及び前記溝内を含む前記半導体チップの第２の主面上に絶縁膜を形成する工程と、Forming an insulating film on the second main surface of the semiconductor chip including the side wall of the via hole and the inside of the groove;
前記ビアホールの底部で露出する前記パッド電極と電気的に接続され、かつ前記絶縁膜を介して前記ビアホールから前記半導体チップの第２の主面上に延びる配線層を形成する工程と、を有することを特徴とする半導体装置の製造方法。Forming a wiring layer electrically connected to the pad electrode exposed at the bottom of the via hole and extending from the via hole onto the second main surface of the semiconductor chip via the insulating film. A method of manufacturing a semiconductor device. 第１の主面にパッド電極が形成された半導体基板を準備し、Preparing a semiconductor substrate having a pad electrode formed on the first main surface;
前記半導体基板の第２の主面から前記パッド電極上に到達するビアホールを形成すると共に、当該ビアホールよりも小さい開口径を有した溝を、当該半導体基板の第２の主面上に形成する工程と、Forming a via hole reaching the pad electrode from the second main surface of the semiconductor substrate and forming a groove having an opening diameter smaller than the via hole on the second main surface of the semiconductor substrate; When,
前記ビアホールの側壁及び前記溝内を含む前記半導体チップの第２の主面上に絶縁膜を形成する工程と、Forming an insulating film on the second main surface of the semiconductor chip including the side wall of the via hole and the inside of the groove;
前記ビアホールの底部で露出する前記パッド電極と電気的に接続され、かつ前記絶縁膜を介して前記ビアホールから前記半導体チップの第２の主面上に延びる配線層を形成する工程と、を有することを特徴とする半導体装置の製造方法。Forming a wiring layer electrically connected to the pad electrode exposed at the bottom of the via hole and extending from the via hole onto the second main surface of the semiconductor chip via the insulating film. A method of manufacturing a semiconductor device. 前記ビアホール及び前記溝を形成する工程は、The step of forming the via hole and the groove includes
第１の開口部及び当該第１の開口部よりも小さい開口径を有する第２の開口部が設けられたレジスト層を、第２の主面上に形成する工程と、  Forming a resist layer provided with a first opening and a second opening having an opening diameter smaller than the first opening on the second main surface;
前記レジスト層をマスクとして、前記半導体基板の第２の主面をエッチングする工程と、を含むことを特徴とする請求項５または請求項６に記載の半導体装置の製造方法。  The method for manufacturing a semiconductor device according to claim 5, further comprising: etching the second main surface of the semiconductor substrate using the resist layer as a mask. 前記溝は、前記半導体基板の第２の主面のうち、前記配線層の端部に対応する位置に形成されることを特徴とする請求項５乃至請求項７のいずれかに記載の半導体装置の製造方法。The semiconductor device according to claim 5, wherein the groove is formed at a position corresponding to an end portion of the wiring layer in the second main surface of the semiconductor substrate. Manufacturing method. 前記レジスト層に設けられた前記第２の開口部は、前記半導体基板の第２の主面のうち、前記配線層の端部に対応する位置に形成されることを特徴とする請求項５乃至請求項８のいずれかに記載の半導体装置の製造方法。6. The second opening provided in the resist layer is formed at a position corresponding to an end of the wiring layer in the second main surface of the semiconductor substrate. A method for manufacturing a semiconductor device according to claim 8. 前記配線層を形成する工程の後に、After the step of forming the wiring layer,
前記配線層を覆う保護層を形成する工程と、Forming a protective layer covering the wiring layer;
前記保護層の一部に前記配線層の一部を露出する開口部を形成して、当該開口部で露出する前記配線層上に、導電端子を形成する工程と、Forming an opening exposing a part of the wiring layer in a part of the protective layer, and forming a conductive terminal on the wiring layer exposed in the opening;
前記半導体基板を複数の半導体チップに分割する工程と、を有することを特徴とする請求項５乃至請求項９のいずれかに記載の半導体装置の製造方法。The method for manufacturing a semiconductor device according to claim 5, further comprising a step of dividing the semiconductor substrate into a plurality of semiconductor chips. 第１の主面にパッド電極が形成された半導体基板を準備し、Preparing a semiconductor substrate having a pad electrode formed on the first main surface;
前記半導体基板の第２の主面から前記パッド電極上に到達するビアホールを形成すると共に、当該ビアホールよりも小さい開口径を有した溝を、当該半導体基板の第２の主面上に形成する工程を有することを特徴とする半導体装置の製造方法。Forming a via hole reaching the pad electrode from the second main surface of the semiconductor substrate and forming a groove having an opening diameter smaller than the via hole on the second main surface of the semiconductor substrate; A method for manufacturing a semiconductor device, comprising:
JP2004129256A 2004-04-26 2004-04-26 Semiconductor device and manufacturing method thereof Expired - Fee Related JP4544902B2 (en)

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JP2004129256A JP4544902B2 (en) 2004-04-26 2004-04-26 Semiconductor device and manufacturing method thereof

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JP2004129256A JP4544902B2 (en) 2004-04-26 2004-04-26 Semiconductor device and manufacturing method thereof

Publications (3)

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JP2005311215A JP2005311215A (en) 2005-11-04
JP2005311215A5 true JP2005311215A5 (en) 2007-06-07
JP4544902B2 JP4544902B2 (en) 2010-09-15

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JP5194537B2 (en) * 2007-04-23 2013-05-08 株式会社デンソー Semiconductor device and manufacturing method thereof
TWI394260B (en) * 2007-10-31 2013-04-21 Adl Engineering Inc Semiconductor device package structure with multi-chips and method of the same
JP2009295676A (en) * 2008-06-03 2009-12-17 Oki Semiconductor Co Ltd Semiconductor device and production method thereof
JP2010245292A (en) * 2009-04-06 2010-10-28 Panasonic Corp Optical device, electronic apparatus, and method of manufacturing the same
US8853072B2 (en) * 2011-06-06 2014-10-07 Micron Technology, Inc. Methods of forming through-substrate interconnects
JP6012998B2 (en) * 2012-03-29 2016-10-25 芝浦メカトロニクス株式会社 Plasma processing method

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JP3494100B2 (en) * 2000-01-11 2004-02-03 富士通株式会社 Semiconductor device and method of mounting the same
JP3530149B2 (en) * 2001-05-21 2004-05-24 新光電気工業株式会社 Wiring board manufacturing method and semiconductor device
JP4212293B2 (en) * 2002-04-15 2009-01-21 三洋電機株式会社 Manufacturing method of semiconductor device
JP2003347471A (en) * 2002-05-24 2003-12-05 Fujikura Ltd Semiconductor device and method for manufacturing the same

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