JP4434778B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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Description
図1は、本発明の実施の形態1による半導体装置の構成を示す一部破断断面図である。図に示されるように、基板(インターポーザ)2上に半導体チップ3aが接着剤や銀ペースト等により固定されている。接着剤は、例えばシール型の接着剤が用いられる。この半導体チップ3aには、メモリIC、ロジックIC等様々な種類のICが含まれ、主にシリコンやガリウムヒ素によりなる。以下の半導体チップ3b、3cも同様である。
以上説明したように、本発明の実施の形態1においては、主面の面積が異なるスペーサを2枚組み合わせて構成したため、スペーサの上面に固定される半導体チップの撓みを抑制できる。特に、スペーサは、上側のスペーサを下側のスペーサよりもその主面の面積が大きくなるようにすると、下側にある半導体チップのワイヤボンディングのための空間を確保しつつ、効果的に上面に固定される半導体チップの撓みを抑制することができる。
本発明の実施の形態2においては、発明の実施の形態1と同様に、主面の面積が異なるスペーサを2枚組み合わせて構成しているが、特に、これらのスペーサの厚みに特徴を有する。スペーサ以外の構成については、基本的に発明の実施の形態1において説明した構成と同じであり、説明を省略する。
本発明の実施の形態3においては、発明の実施の形態1、2と同様に、主面の面積が異なるスペーサを2枚組み合わせて構成しているが、特に、これらのスペーサの厚みに特徴を有する。スペーサ以外の構成については、基本的に発明の実施の形態1において説明した構成と同じであり、説明を省略する。この例では、発明の実施の形態2と異なり、図3に示されるように、スペーサ4aよりもスペーサ4bの方がその主面の面積が小さい。
本発明の実施の形態4においては、発明の実施の形態1、2と同様に、主面の面積が異なるスペーサを2枚組み合わせて構成しているが、特に、これらのスペーサのうち、上側にあるスペーサ4bの主面の面積が、上側にある半導体チップ3bの主面の面積以上であることを特徴とする。
上述した各発明の実施の形態では、スペーサ4は、2つのスペーサ4a、4bにより構成した例を説明したが、これに限らず、スペーサ4は、3つ以上のスペーサにより構成するようにしても同様の効果を奏する。この場合に、発明の実施の形態1に関しては、上側の半導体チップ3bに近い側、即ち上側にいくに従って、段階的にスペーサの主面の面積が大きくなるようにするとよい。また、発明の実施の形態2に関しては、スペーサの主面の面積が交互に大小を繰り返すように構成すると、発生するボイドの大きさをより小さくすることが可能となる。例えば、一番下のスペーサ4aよりも次のスペーサ4bの方が大きくなるように、その次のスペーサ4cはスペーサ4bよりも小さくなるようにし、さらに、その次のスペーサ4dはスペーサ4cよりも大きくなるようにする。
2 基板
3 半導体チップ
4 スペーサ
5 ワイヤ
6 封止用樹脂
Claims (12)
- 複数の半導体チップをスペーサを介して積層してパッケージングした半導体装置であって、前記スペーサは、少なくとも第1のスペーサと前記第1のスペーサの上方に設けられた第2のスペーサとを備え、
前記第2のスペーサは、前記第2のスペーサよりも上方に設けられた半導体チップ以上の主面の面積を有し、前記第2のスペーサの少なくとも一面の全領域に渡って電磁波遮断膜が形成されていることを特徴とする半導体装置。 - 前記第1のスペーサと前記第2のスペーサの厚さの総和は、前記スペーサの下側に位置する半導体チップのワイヤボンディングに必要とされる厚みであることを特徴とする請求項1記載の半導体装置。
- 前記第1のスペーサと前記第2のスペーサのいずれか一方は、前記半導体チップの厚さよりも薄いことを特徴とする請求項1記載の半導体装置。
- 前記第1のスペーサと前記第2のスペーサは、略同じ厚さを有することを特徴とする請求項2又は3記載の半導体装置。
- 前記電磁波遮断膜は、アルミ膜であることを特徴とする請求項1記載の半導体装置。
- 前記電磁波遮断膜は、金属膜であることを特徴とする請求項1記載の半導体装置。
- 第1の半導体チップと、
前記第1の半導体チップの上面に接して設けられた第1の接着層と、
前記第1の接着層の上面に接して設けられた第1のスペーサと、
前記第1のスペーサの上に設けられた第2のスペーサと、
前記第2のスペーサの上面に接して設けられた第2の接着層と、
前記第2の接着層の上面に接して設けられた第2の半導体チップと、
から成る積層構造を有し、
前記第2のスペーサの下面の面積が、前記第1のスペーサの上面の面積よりも大きいことを特徴とする半導体装置。 - 前記第1のスペーサと前記第2のスペーサが略同じ厚みであることを特徴とする請求項7記載の半導体装置。
- 前記第1のスペーサと前記第2のスペーサの厚さの総和は、前記第1の半導体チップのワイヤボンディングに必要とされる厚みであることを特徴とする請求項8記載の半導体装置。
- 前記第1のスペーサ及び前記第2のスペーサがシリコンから成ることを特徴とする請求項7乃至9のいずれか1項に記載の半導体装置。
- 基板の上面に設けられた第1の半導体チップと、
前記第1の半導体チップの上面に第1の接着層を介して設けられ、前記第1の半導体チップよりもその主面の面積が小さい第1のスペーサと、
第2の半導体チップと、
前記第2の半導体チップの下面に第2の接着層を介して設けられた第2のスペーサと、
を有し、
前記第1の半導体チップと前記第2の半導体チップは少なくとも前記第1のスペーサと前記第2のスペーサを介して積層され、前記第1のスペーサよりも前記第2のスペーサの方がその主面の面積が大きいことを特徴とする半導体装置。 - 前記第1のスペーサ及び前記第2のスペーサがシリコンウエハから成ることを特徴とする請求項11記載の半導体装置。
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JP2004048992A JP4434778B2 (ja) | 2004-02-25 | 2004-02-25 | 半導体装置 |
US11/063,852 US7323786B2 (en) | 2004-02-25 | 2005-02-24 | Semiconductor device package of stacked semiconductor chips with spacers provided therein |
US11/934,976 US7888805B2 (en) | 2004-02-25 | 2007-11-05 | Semiconductor device package of stacked semiconductor chips with spacers provided therein |
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JP2004048992A JP4434778B2 (ja) | 2004-02-25 | 2004-02-25 | 半導体装置 |
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JP2005243754A JP2005243754A (ja) | 2005-09-08 |
JP4434778B2 true JP4434778B2 (ja) | 2010-03-17 |
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JP2004048992A Expired - Fee Related JP4434778B2 (ja) | 2004-02-25 | 2004-02-25 | 半導体装置 |
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JP (1) | JP4434778B2 (ja) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4000547A (en) * | 1975-07-25 | 1977-01-04 | Eisenpresser Marvin L | Snap fastener |
US6351028B1 (en) * | 1999-02-08 | 2002-02-26 | Micron Technology, Inc. | Multiple die stack apparatus employing T-shaped interposer elements |
KR100401020B1 (ko) * | 2001-03-09 | 2003-10-08 | 앰코 테크놀로지 코리아 주식회사 | 반도체칩의 스택킹 구조 및 이를 이용한 반도체패키지 |
JP4577228B2 (ja) * | 2006-02-09 | 2010-11-10 | セイコーエプソン株式会社 | 半導体装置および半導体装置の製造方法 |
US7675180B1 (en) * | 2006-02-17 | 2010-03-09 | Amkor Technology, Inc. | Stacked electronic component package having film-on-wire spacer |
US7633144B1 (en) | 2006-05-24 | 2009-12-15 | Amkor Technology, Inc. | Semiconductor package |
KR100809701B1 (ko) * | 2006-09-05 | 2008-03-06 | 삼성전자주식회사 | 칩간 열전달 차단 스페이서를 포함하는 멀티칩 패키지 |
US8154881B2 (en) * | 2006-11-13 | 2012-04-10 | Telecommunication Systems, Inc. | Radiation-shielded semiconductor assembly |
FR2910715B1 (fr) * | 2006-12-21 | 2009-06-26 | St Microelectronics Sa | Procede et appareillage pour realiser des micro-lentilles optiques sur un dispositif semi-conducteur |
US8148825B2 (en) * | 2007-06-05 | 2012-04-03 | Stats Chippac Ltd. | Integrated circuit package system with leadfinger |
SG150395A1 (en) * | 2007-08-16 | 2009-03-30 | Micron Technology Inc | Stacked microelectronic devices and methods for manufacturing stacked microelectronic devices |
KR20090022433A (ko) * | 2007-08-30 | 2009-03-04 | 삼성전자주식회사 | 반도체 패키지 |
US8533853B2 (en) * | 2009-06-12 | 2013-09-10 | Telecommunication Systems, Inc. | Location sensitive solid state drive |
JP6418605B2 (ja) * | 2015-07-31 | 2018-11-07 | 東芝メモリ株式会社 | 半導体装置および半導体装置の製造方法 |
DE112018006518T5 (de) | 2017-12-20 | 2020-09-03 | Sony Semiconductor Solutions Corporation | Halbleitervorrichtung |
JP7034706B2 (ja) * | 2017-12-27 | 2022-03-14 | キオクシア株式会社 | 半導体装置 |
Family Cites Families (8)
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JP3943165B2 (ja) | 1996-07-26 | 2007-07-11 | ハネウェル・インターナショナル・インコーポレーテッド | チップ・スタックおよびコンデンサ取付の配置 |
JP3266815B2 (ja) * | 1996-11-26 | 2002-03-18 | シャープ株式会社 | 半導体集積回路装置の製造方法 |
JP2001308262A (ja) | 2000-04-26 | 2001-11-02 | Mitsubishi Electric Corp | 樹脂封止bga型半導体装置 |
JP2002057272A (ja) | 2000-08-04 | 2002-02-22 | ▲せき▼品精密工業股▲ふん▼有限公司 | スタックト・ダイ・パッケージ構造 |
JP2002261233A (ja) | 2001-03-05 | 2002-09-13 | Sony Corp | 半導体装置及びその製造方法 |
DE10142120A1 (de) * | 2001-08-30 | 2003-03-27 | Infineon Technologies Ag | Elektronisches Bauteil mit wenigstens zwei gestapelten Halbleiterchips sowie Verfahren zu seiner Herstellung |
SG120073A1 (en) * | 2002-07-18 | 2006-03-28 | United Test & Assembly Ct Ltd | Multiple chip semiconductor packages |
US7409572B1 (en) * | 2003-12-05 | 2008-08-05 | Lsi Corporation | Low power memory controller with leaded double data rate DRAM package arranged on a two layer printed circuit board |
-
2004
- 2004-02-25 JP JP2004048992A patent/JP4434778B2/ja not_active Expired - Fee Related
-
2005
- 2005-02-24 US US11/063,852 patent/US7323786B2/en not_active Expired - Fee Related
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Also Published As
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US20080087989A1 (en) | 2008-04-17 |
US7888805B2 (en) | 2011-02-15 |
US20050184378A1 (en) | 2005-08-25 |
JP2005243754A (ja) | 2005-09-08 |
US7323786B2 (en) | 2008-01-29 |
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