CN101604638B - 圆片级扇出芯片封装方法 - Google Patents

圆片级扇出芯片封装方法 Download PDF

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CN101604638B
CN101604638B CN2009100318850A CN200910031885A CN101604638B CN 101604638 B CN101604638 B CN 101604638B CN 2009100318850 A CN2009100318850 A CN 2009100318850A CN 200910031885 A CN200910031885 A CN 200910031885A CN 101604638 B CN101604638 B CN 101604638B
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张黎
赖志明
陈栋
陈锦辉
曹凯
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Jiangyin Changdian Advanced Packaging Co Ltd
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    • HELECTRICITY
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    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
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Abstract

本发明涉及一种圆片级扇出芯片封装方法,包括以下工艺过程:在载体圆片表面依次覆盖剥离膜和薄膜介质层I,在薄膜介质层I上形成光刻图形开口I;在图形开口I及其表面实现与基板端连接之金属电极和再布线金属走线;在与基板端连接之金属电极表面、再布线金属走线表面以及薄膜介质层I的表面覆盖薄膜介质层II,并在薄膜介质层II上形成光刻图形开口II;在光刻图形开口II实现与芯片端连接之金属电极;将芯片倒装至与芯片端连接之金属电极后进行注塑封料并固化,形成带有塑封料的封装体;将载体圆片和剥离膜与带有塑封料的封装体分离,形成塑封圆片;植球回流,形成焊球凸点;单片切割,形成最终的扇出芯片结构。本发明方法成本低,具备载带功能,且能很好解决工艺过程芯片移位问题。

Description

圆片级扇出芯片封装方法
(一)技术领域
本发明涉及一种芯片封装结构及其封装方法。属半导体芯片封装技术领域。
(二)背景技术
在当前的半导体行业中,电子封装已经成为行业发展的一个重要方面。几十年的封装技术的发展,传统的周边布线型低引脚数的封装形式越来越无法满足当前高密度、小尺寸的封装要求,球栅阵列(BGA)封装技术的诞生为封装技术从周边布线到面阵布线提供了完整的解决方案。其优势在于:
增加了单位芯片面积上的引脚数目。
与传统的引线键合结构相比,球栅阵列结构缩短了芯片电路到基板之间的距离,增加了电信号的传输速度,提高了芯片功能。
引线键合结构由于结构本身的限制,封装尺寸较大,球栅阵列结构大大减小封装尺寸,为电子产品的小型化提供了必需的解决方案。
与引线键合结构相比较,球栅阵列提供高效的散热能力。
球栅阵列封装结构中,有两种典型结构:引线键合型和倒装芯片型。引线键合型在芯片和载体之间采用引线键合的方式进行连接,相对于采用倒装方式的连接结构而言,其芯片散热和信号传输方面都处于劣势。所以倒装芯片型球栅阵列结构在对信号和导热要求较高的产品中使用较为广泛,但前提是载体的电极节距满足芯片节距要求。
随着电子产品向更薄、更轻、更高引脚密度、更低成本方面发展,采用单颗芯片封装技术已经逐渐无法满足产业需求,一种新的封装技术——圆片级封装技术的出现为封装行业向低成本封装发展提供了契机。同时,制约着封装技术向高密度方向发展的另外一个重要原因是基板技术本身在细小电极节距方面的加工能力,必须通过载体,如塑料载带球栅阵列(PBGA)中的塑料载体和陶瓷载带球栅阵列(CBGA)中的陶瓷载体,对阵列节距的放大完成封装过程。虽然行业中也有相关的圆片级扇出(Fanout)封装技术,但在工艺过程中芯片的偏移是该技术发展的重大障碍。
(三)发明内容
本发明的目的在于克服上述不足,提供一种封装成本低、具备载带功能、且能很好解决工艺过程芯片移位问题的圆片级扇出芯片封装方法和封装方法。
本发明的目的是这样实现的:一种圆片级扇出芯片封装方法,其特征在于所述方法包括以下工艺过程:
步骤一、准备与圆片尺寸一致的载体圆片,在载体圆片表面覆盖剥离膜;
步骤二、在剥离膜表面覆盖薄膜介质层I,并在所述薄膜介质层I上形成设计的光刻图形开口I;
步骤三、通过电镀、化学镀或溅射的方式在所述薄膜介质层I的图形开口及其表面实现与基板端连接之金属电极和再布线金属走线,
重复步骤二和步骤三实现多层走线;
步骤四、在步骤三形成的与基板端连接之金属电极表面、再布线金属走线表面以及没有实现与基板端连接之金属电极和再布线金属走线的薄膜介质层I的表面覆盖薄膜介质层II,并在所述薄膜介质层II上形成设计的光刻图形开口II;
步骤五、通过电镀、化学镀或溅射的方式在所述光刻图形开口II实现与芯片端连接之金属电极;
步骤六、将带有IC芯片、金属柱/金属凸点和焊料的芯片倒装至与芯片端连接之金属电极,回流形成可靠连接,完成芯片倒装;
步骤七、对完成芯片倒装的圆片进行注塑封料并固化,形成带有塑封料的封装体;
步骤八、将载体圆片和剥离膜与带有塑封料的封装体分离,形成塑封圆片;
步骤九、在步骤八形成塑封圆片后的与基板端连接之金属电极上植球回流,形成焊球凸点;
步骤十、对形成焊球凸点的带有塑封料的封装体进行单片切割,形成最终的扇出芯片结构。
本发明的特点是通过在载体圆片上制作再布线电路和电极载体,完成扇出结构薄膜载带的制作,再通过倒装的方式重建圆片级结构,实现芯片与薄膜载带的连接,利用焊料在回流过程中自对位的特性,解决芯片工艺中的移位问题,然后对倒装完的结构进行注模,实现扇出结构之塑封过程,最终切割成单颗的芯片。
本发明的圆片级扇出(Fanout)结构为先进封装技术提供全新的解决方案。首先,利用圆片级封装的方式降低封装成本,其次,扇出(Fanout)结构的载体薄膜具备了塑料载带球栅阵列(PBGA)和陶瓷载带球栅阵列(CBGA)中载带的功能,与此同时,本发明的倒装焊接技术很好的解决了工艺过程芯片移位的问题。
(四)附图说明
图1为本发明金属柱结构的扇出(Fanout)示意图,塑封料对芯片完全覆盖。
图2为本发明金属柱结构的扇出(Fanout)示意图,塑封料与芯片等高覆盖。
图3为本发明金属凸点结构的扇出(Fanout)示意图,塑封料对芯片完全覆盖。
图4为本发明金属凸点结构的扇出(Fanout)示意图,塑封料与芯片等高覆盖。
图5~17为本发明扇出(Fanout)结构封装方法示意图。
图中:薄膜介质层I 101、与基板端连接之金属电极102、再布线金属走线103、薄膜介质层II 104、与芯片端连接之金属电极105、IC芯片106、金属柱/金属凸点107、焊料108、塑封料109、焊球凸点110、载体圆片111、剥离膜112;光刻图形开口I 1011、光刻图形开口II 1041。
(五)具体实施方式
参见图1,本发明圆片级扇出(Fanout)芯片封装结构,包括薄膜介质层I 101,所述薄膜介质层I 101上形成有光刻图形开口I 1011,在所述图形开口I 1011以及薄膜介质层I 101的表面设置有与基板端连接之金属电极102和再布线金属走线103,在与基板端连接之金属电极102表面、再布线金属走线103表面以及薄膜介质层I 101的表面覆盖有薄膜介质层II104,在所述薄膜介质层II 104上形成有光刻图形开口II 1041,在所述光刻图形开口II 1041设置有与芯片端连接之金属电极105,将带有IC芯片106、金属柱/金属凸点107和焊料108的芯片倒装在与芯片端连接之金属电极105上,形成芯片倒装的圆片,在所述圆片表面注塑封料109,在所述与基板端连接之金属电极102上设置有焊球凸点110。
本发明圆片级扇出(Fanout)芯片封装结构的实现过程如下:
步骤一、准备与圆片尺寸一致的载体圆片111(如6”、8”等圆片或石英玻璃等),在载体圆片111表面覆盖剥离膜112。如图5、图6。
步骤二、在剥离膜表面覆盖薄膜介质层I 101,并在所述薄膜介质层I101上形成设计的光刻图形开口I 1011。如图7。
步骤三、通过电镀、化学镀或溅射的方式在所述薄膜介质层I 101的图形开口I 1011以及所述薄膜介质层I 101表面实现与基板端连接之金属电极102和再布线金属走线103。如图8。
重复步骤二和步骤三可实现多层走线。
步骤四、在步骤三形成的与基板端连接之金属电极102表面、再布线金属走线103表面以及没有实现与基板端连接之金属电极102和再布线金属走线103的薄膜介质层I 101的表面覆盖薄膜介质层II 104,并在所述薄膜介质层II 104上形成设计的光刻图形开口II 1041。如图9。
步骤五、通过电镀、化学镀或溅射的方式在所述光刻图形开口II 1041实现与芯片端连接之金属电极105。如图10。
步骤六、将带有IC芯片106、金属柱/金属凸点107和焊料108的芯片按照载体圆片上的图形排列倒装至与芯片端连接之金属电极105,回流形成可靠连接,完成芯片倒装。如图11、12。
步骤七、对完成芯片倒装的圆片进行注塑封料109并固化。形成带有塑封料的封装体。如图13。
步骤八、将载体圆片111和剥离膜112与带有塑封料的封装体分离。形成塑封圆片。如图14。
步骤九、在步骤八形成的塑封圆片表面的与基板端连接之金属电极102上植球回流,形成焊球凸点110。如图15。
步骤十、对形成焊球凸点的带有塑封料的封装体进行单片切割,形成最终的扇出(Fanout)芯片结构。如图16和图17。
所述薄膜介质层I 101和薄膜介质层II 104均为具有光刻特征的树脂,如聚酰亚胺(PI)、苯并环丁烯(BCB)等。
所述与基板端连接之金属电极102、再布线金属走线103、与芯片端连接之金属电极105均为单层或多层金属结构,如金属铜、镍或钛/铜、钛钨/镍等。
所述金属柱/金属凸点107为铜、镍等导电金属。
所述焊料108为纯锡或锡基焊料合金。
所述塑封料109为环氧类树脂材料(包括含有填充料和不含填充料)。
所述焊球凸点110为锡基合金或纯锡焊料。
所述塑封料可以对芯片完全覆盖,如图1和3所示;也可以与芯片等高覆盖,如图2。

Claims (9)

1.一种圆片级扇出芯片封装方法,其特征在于所述方法包括以下工艺过程:
步骤一、准备与圆片尺寸一致的载体圆片,在载体圆片表面覆盖剥离膜;
步骤二、在剥离膜表面覆盖薄膜介质层Ⅰ,并在所述薄膜介质层Ⅰ上形成设计的光刻图形开口Ⅰ;
步骤三、通过电镀、化学镀或溅射的方式在所述薄膜介质层Ⅰ的图形开口Ⅰ及其表面实现与基板端连接之金属电极和再布线金属走线,
重复步骤二和步骤三实现多层走线;
步骤四、在步骤三形成的与基板端连接之金属电极表面、再布线金属走线表面以及没有实现与基板端连接之金属电极和再布线金属走线的薄膜介质层Ⅰ的表面覆盖薄膜介质层Ⅱ,并在所述薄膜介质层Ⅱ上形成设计的光刻图形开口Ⅱ;
步骤五、通过电镀、化学镀或溅射的方式在所述光刻图形开口Ⅱ实现与芯片端连接之金属电极;
步骤六、将带有IC芯片、金属柱/金属凸点和焊料的芯片倒装至与芯片端连接之金属电极,回流形成可靠连接,完成芯片倒装;
步骤七、对完成芯片倒装的圆片进行注塑封料并固化,形成带有塑封料的封装体;
步骤八、将载体圆片和剥离膜与带有塑封料的封装体分离,形成塑封圆片;
步骤九、在步骤八形成塑封圆片后的与基板端连接之金属电极上植球回流,形成焊球凸点;
步骤十、对形成焊球凸点的带有塑封料的封装体进行单片切割,形成最终的扇出芯片结构。
2.根据权利要求1所述的一种圆片级扇出芯片封装方法,其特征在于所述薄膜介质层Ⅰ和薄膜介质层Ⅱ均为具有光刻特征的树脂。
3.根据权利要求2所述的一种圆片级扇出芯片封装方法,其特征在于所述具有光刻特征的树脂为聚酰亚胺或苯并环丁烯。
4.根据权利要求1所述的一种圆片级扇出芯片封装方法,其特征在于所述与基板端连接之金属电极、再布线金属走线、与芯片端连接之金属电极均为单层或多层金属。
5.根据权利要求4所述的一种圆片级扇出芯片封装方法,其特征在于所述单层金属为金属铜或镍,所述多层金属为钛/铜或钛钨/镍。
6.根据权利要求1所述的一种圆片级扇出芯片封装方法,其特征在于所述金属柱/金属凸点为铜或镍。
7.根据权利要求1所述的一种圆片级扇出芯片封装方法,其特征在于所述焊料为纯锡或锡基焊料合金。
8.根据权利要求1所述的一种圆片级扇出芯片封装方法,其特征在于所述焊球凸点为锡基合金或纯锡焊料。
9.根据权利要求1所述的一种圆片级扇出芯片封装方法,其特征在于所述塑封料与芯片完全覆盖,或与芯片等高覆盖。
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