US20070096288A1 - Double-sided circuit board and multi-chip package including such a circuit board and method for manufacture - Google Patents

Double-sided circuit board and multi-chip package including such a circuit board and method for manufacture Download PDF

Info

Publication number
US20070096288A1
US20070096288A1 US11606284 US60628406A US2007096288A1 US 20070096288 A1 US20070096288 A1 US 20070096288A1 US 11606284 US11606284 US 11606284 US 60628406 A US60628406 A US 60628406A US 2007096288 A1 US2007096288 A1 US 2007096288A1
Authority
US
Grant status
Application
Patent type
Prior art keywords
circuit board
chip
surface
area
multi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11606284
Inventor
Hee Choi
Cheol Yoo
Original Assignee
Choi Hee K
Yoo Cheol J
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565Moulds
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009Pre-treatment of the layer connector or the bonding area
    • H01L2224/83051Forming additional members, e.g. dam structures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
    • H01L2224/854Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85463Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/8547Zirconium (Zr) as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/0651Wire or wire-like electrical connections from device to substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06572Auxiliary carrier between devices, the carrier having an electrical connection structure
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06582Housing for the assembly, e.g. chip scale package [CSP]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06582Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586Housing with external bump or bump-like connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01068Erbium [Er]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01087Francium [Fr]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/15165Monolayer substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

A multi-chip package includes a double-sided circuit board having first and second surfaces. Each surface has a package area and a peripheral area. Each package area has a chip mounting area on which a chip is attached, and a bonding area with which the chip is electrically connected. The peripheral area of the first surface has a runner area on which molding compound flows, and the peripheral area of the second surface has an external connection pattern with which the bonding areas are electrically connected. In particular, the circuit board has gate holes, which are co-located on each surface to result in a common hole.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a semiconductor chip packaging technique and more particularly to a double-sided circuit board and a multi-chip package including the circuit board.
  • 2. Description of the Related Art
  • Since recent trends in electronics development have been toward miniaturization and high performance, chips (integrated circuits) are more integrated. In addition, different types of chips need to be contained in a single package body, in order to achieve various semiconductor devices. In order to satisfy these pressing demands, a multi-chip packaging technique is applied.
  • FIG. 1 is a sectional view showing a conventional multi-chip package using a circuit board.
  • A conventional multi-chip package 100 is a fine-pitch ball grid array (FBGA). A first chip 120 is attached to a first surface of a circuit board 110, and a second chip 130 is attached to the first chip 120 with an adhesive tape 135. The first chip 120 and the second chip 130 are electrically connected to bonding pads 140 by bonding wires 143, 145 which are formed on the circuit board 110. The conventional FBGA multi-chip package 100 uses a chip stacking technique and a wire bonding technique.
  • The first and second chips 120, 130 and the bonding wires 143, 145 are protected by package body 150 of molding compound. A plurality of solder balls 160 is attached on the second surface of the circuit board 110. The solder balls 160 are connected to solder ball pads 141, which are formed on the first surface of the circuit board 110, thereby electrically connecting the multi-chip package 100 with a mother-board or other electrical devices.
  • In the conventional multi-chip package 100, adhesive tape 135, which is used for attaching the second chip 130 to the first chip 120, does not encroach upon the wire bonding area of the first chip 120. Therefore, the second chip 130 must be smaller than the first chip 120. Since the second chip 130 is distant from the bonding pads l40 of the circuit board 110, the bonding wire 145 must be formed in an almost straight-lined loop, so as to shorten the length of the bonding wires 145. Accordingly, it requires an additional apparatus and technique for the wire bonding process.
  • SUMMARY OF THE INVENTION
  • The present invention provides a circuit board that embodies a multi-chip package without requiring necessarily a special wiring technique and apparatus.
  • Further, the present invention provides a multi-chip package that can easily be embodied regardless of the size of the chips and circuit board.
  • Additionally, the present invention provides a multi-chip package manufactured using wire bonding techniques and molding techniques which are used in conventional plastic packaging processes.
  • Also, the present invention provides a multi-chip package that has a thin width regardless of the stacked chips and the circuit board used in such multi-chip packages.
  • A multi-chip package according to the present invention provides chips mounted to two obverse sides of a circuit board. These chips may be mounted in recesses in the board. This mounting arrangement allows for chips of differing sizes to be mounted without the concerns raised by chip stacking methods. The chips may be mounted in package areas which have both a chip mounting area and a bonding area used to electrically connect a mounted chip to the circuit board. The circuit board may also have a peripheral area and may provide for a connection area which is used to connect the chip or chips to external devices or other electrical connections. The circuit board surfaces may have gate holes which are co-located on each surface to result in a through hole in the board.
  • The gate hole allows for the encapsulation of the chips in a molding compound to occur on both sides of the board in one molding process that uses a molding die over each of the two circuit board surfaces. The molding dice may enter the gate holes to some extent to form a gate neck which enhances the strength of the gate hole area after the molding process.
  • The circuit board according to the present invention supports the fabrication of the multi-chip package as described above.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • These and other objects, features and advantages of the present invention will be readily understood with reference to the following detailed description thereof provided in conjunction with the accompanying drawings, wherein like reference numerals designate like structural elements, and in which:
  • FIG. 1 is a sectional view showing a conventional multi-chip package using a circuit board;
  • FIG. 2 is a sectional view showing a multi-chip package using a double-sided circuit board according to one embodiment of the present invention;
  • FIG. 3 is a sectional view showing a multi-chip package using a double-sided circuit board according to another embodiment of the present invention;
  • FIG. 4 is a detailed sectional view showing the circuit board used in the multi-chip package of FIG. 3;
  • FIG. 5 is a plan view showing the first surface of a double-sided circuit board according to one embodiment of the present invention;
  • FIG. 6 is a plan view showing the second surface of a double-sided circuit board according to one embodiment of the present invention;
  • FIG. 7 a is a sectional view showing a molding die used in a molding process of the present invention;
  • FIG. 7 b is a partially enlarged sectional view of a position C of the molding die of FIG. 7 a;
  • FIGS. 8 a to FIG. 8 c are plan views showing examples of a gate hole formed on the circuit board of the present invention; and
  • FIGS. 9 a and 9 b are detailed sectional views of the molding die of the present invention.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.
  • In some embodiments, as shown in FIG. 2 a multi-chip package is manufactured using a double-sided circuit board.
  • A multi-chip package 1 comprises a circuit board 10, chips 20, 30, package bodies 50, 52, bonding wires 60, 62 and solder balls 80. The circuit board 10 has a first surface 10 a and a lower surface 10 b. Circuit board 10, is a printed circuit board with dielectric layers and wiring patterns thereon in some embodiments. The dielectric layers may comprise FR-4 material and glass fiber and the wiring patterns are made of copper.
  • The first chip 20 is attached to the first surface 10 a with an adhesive tape 25 and the second chip 30 is attached to the second surface 10 b with an adhesive tape 35 or other methods. The same or different types of chips may be used. For example, the Flash memory and SRAM or logic IC and memory chip may both be in one multi-chip package. The adhesive tapes 25, 35 may be silver filled epoxy compound adhesive. A substrate area to which the first and second chip 20, 30 are attached, may be plated with nickel(Ni) and platinum(Pt) in order to increase the adhesion force. The electrode pads 22 of the first chip 20 are electrically connected with bonding pads 70 by wires 60,62. Bonding pads70 are formed on the first surface 10 a of the circuit board 10. The electrode pads 32 of the second chip 30 are also electrically connected with bonding pads 72, which are formed on the second surface 30 b of the circuit board 10. The bonding pads 70, 72 may be formed by photolithography using copper.
  • The first and second chip 20, 30 and bonding wire 60, 62 are sealed by package body 50, 52 in order to protect them from external environmental stress. The package bodies 50, 52 are made of epoxy molding compound (EMC) and are simultaneously formed by a transfer molding process (or an injection molding process) at the same time. This molding process is described below.
  • External connection pattern 74 is formed on the second surface 10 b of the circuit board 10 and may serve as an electrical connection means for electrically connecting the multi-chip package 1 to an, external apparatus. The solder bump area 80 is formed on the external connection patterns 74. The external connection patterns 74 are exposed from a solder mask 76 coated on the second surface 10 b of the circuit board 10. A solder ball is mounted on the exposed external connection patterns 74 and heated by reflow-soldering, thereby forming the solder bump area 80.
  • Since the above-identified multi-chip package 1 of the first embodiment of the present invention comprises dies mounted on both surfaces of the circuit board 10, multi-chip packages can be achieved regardless of the die size, Further, the multi-chip package 1 may be manufactured by using conventional wire bonding and injection molding techniques, thereby being able to achieve mass-production. Moreover since the chips are closer to the bonding pads, additional wire looping technique is not required.
  • FIG.3 is a sectional view showing a multi-chip package using a double-sided circuit board according to another embodiment of the present invention.
  • The same elements are represented with the same reference numerals in both FIG. 2 and FIG. 3.
  • As shown in FIG. 3, the multi-chip package 1 a has recess 90 on the first surface 300 a and the second surface 300 b. This recess 90 is located on both sides of the circuit board in some embodiments. The first and second chips 20, 30 are mounted in recesses 90 by means of adhesive tape 25, 35.
  • With such an embodiment it is possible to decreases the total thickness of the package and to increase the reliability of bonding wires. The recess 90 is formed on the circuit board 300 of FIG. 4.
  • FIG. 4 is a detailed section view showing a circuit board which is suited to be used in the manufacture of the multi-chip package of FIG. 3 according to one embodiment of the present invention.
  • Like a conventional circuit board, the circuit board 300 may comprise BT prepare 310 and a first and second BT CCL(Bisamaleimide-Triazine copper clad laminate) 320, 330 attached to the upper and lower surface of the BT prepare. The first BT CCL 320 has copper foils 325, 327, which are attached to both sides of the BT compound 323, and the second BT CCL 330 also has copper foils 335, 337, which are attached to both sides of the BT compound 333. The first and second BT CCL 320, 330 have the hole on the center. The hole, formed by a punching process, has the same size as the chip mounting area and becomes to the recess 90 on the circuit board 300.
  • FIG. 5 is a plan view showing a first surface of a double-sided circuit board according to one embodiment of the present invention. FIG. 6 is a plan view showing a second surface of the double-sided mounting circuit board according to one embodiment of the present invention. The circuit boards in FIGS. 5 and 6 are an array type which is suitable for mass production of multi-chip packages.
  • The circuit board in the array type is separated into a plurality of unit circuit boards along to the slot 12. An electrically conductive wiring pattern is formed on the circuit board 10 but the detailed configuration of the wiring pattern is omitted here. The wiring pattern varies according to the chip. The wiring patterns may be formed on the surfaces or the inside of the circuit board.
  • The package area 13 and the peripheral area 11 are formed on the first surface 10 a of the circuit board 10. The package area 13 comprises the chip mounting area 14 to which the chip is attached and the bonding area 15 connected to the chip by bonding wires. The bonding area 15 is a portion where the bonding pads 70 of FIGS. 2 and 3 are formed. On the other side, the gate hole 16 and the runner area 17 are formed on the peripheral area 11. The gate hole 16 is formed on the boundary between the packaging area 13 and the peripheral area 11, and is a through-hole which passes through the first and second surface 10 a and 10 b of the circuit board 10. The runner area 17 is formed on the gate hole 16, the peripheral area 11 and the outer boundary of the circuit board 10. This runner area 17 is a path for injecting the molten molding compound to form package body.
  • In some embodiments as shown in FIG. 6, the package area 13 b and the peripheral area 11 b are formed on the second surface 10 b of the circuit board 10. The package area 13 b comprises the chip mounting area 14 b to which the chip is attached and the bonding area 15 b connected to the chip by bonding wires. Outer connection patterns 18 are formed on the peripheral area 11 b of the second surface 10 b and serve to electrically connect the chips attached to the chip mounting area 14 and 14 b of the first and second surface. For example, the outer connection pattern 18 may be a solder ball land or the external connection pattern 74 of FIGS. 2 and 3.
  • The gate hole 16 passes through the circuit board 10. Therefore, the molten molding compound coming from the runner area 17 of the first surface 10 a is injected to the first and second surface 10 a, 10 b through the gate hole 16.
  • FIG. 7 a is a sectional view showing a molding die used in the molding process of the present invention and FIG. 7 b is a partially enlarged sectional view of a position C of the molding die of FIG. 7 a.
  • As shown in FIG. 7 a, a molding die 200 comprises an upper molding die 210 and a lower molding die 220. The circuit board comprising the upper and lower chips is interposed between the upper molding die 210 and lower molding die 220. The upper molding die 210 encompasses concave area 230 a. The lower molding die 220 encompasses concave area 230 b. After closing the upper molding die 210 and the lower molding die 220, the first and second chips 20, 30 are kept in the cavity 230. The cavity 230 is a space for forming the package body (50, 52 of FIG. 2) and is surrounded by the concave areas 230 a, 230 b.
  • In some embodiments of the present invention a solid state pellet is positioned on a port 224 of the lower molding die 220. Upper molding die 210 has a through hole 214 through which transfer ram 260 may pass. The runner 270 is formed between the port 224 and the cavity 230.
  • In some embodiments of the present invention, the circuit board 10 is placed on the molding die 200 so that the second chip 30 is located in the concave area 230 b of the lower molding die 220. Pellet 250 is put on the post 224 and the upper molding die 210 is combined with the lower molding die 220. The pellet 250 is compressed by descending the transfer ram 260. At this time, the molten molding compound 250 a is injected into the cavity 230 along the runner 270 by heating the molding die 200 and the pellet 250.
  • The circuit board 10 has gate hole 16 which passes through the circuit board 10. Therefore, the molten molding compound 250 a is simultaneously injected into the concave areas 230 a, 230 b of the upper molding die 210 and the lower molding die 220 along the gate hole 16 (refer to the arrows “A” and “B” in FIG. 7 b). The multi-chip package body formed on both the first and second surface of the circuit board 10 is made by one injection of molding compound. Preferably, the concave area 230 a of the upper molding die 210 is symmetrical with the concave area 230 b of the lower molding die 220.
  • As shown in FIG. 7 b, a gate neck 240 formed by the upper gate piece 215 of the upper molding die 210 and the lower gate piece 225 of the lower molding die 220 is located on the gate hole 16. The gate neck 240 is a narrow pathway along which the molten molding compound 250 a passes. Thereby, the molding compound of the runner area 270 can be easily removed after finishing the molding and adhesion force between the molding compound and the circuit board near the gate neck 240 does not decreased.
  • After completely filling the cavity 230 with the molten molding compound 250 a, the molding compound 250 a is cooled and hardened, the upper and lower molding die 210, 220 are separated from each other. By cutting the circuit board 10 along the slot 12, single multi-chip packages can be obtained.
  • Although FIG. 7 a describes the molding die with two cavities, the molding die may comprise a plurality of cavities connected to radial runners. The number, arrangement and length of the runner 270 are determined by pressure and viscosity of the molten molding compound 250 a and size of desired package body.
  • FIGS. 8 a to FIG. 8 c are plan views showing examples of a gate hole formed on the circuit board of the present invention. It is to be understood that other embodiments of the gate hole may be used.
  • The gate hole 16 can be embodied in various figures on the circuit board 10, 300. For example, the gate hole can be formed, in a plan view, into a square-shaped gate hole 16 a as shown in FIG. 8 a or a trapezoid-shaped gate hole 16 b as shown in FIG. 8 b. Alternatively, the gate hole in the peripheral area 11 can be extended to the package area 13 as designated by reference number 16 c of FIG. 8 c.
  • In order to facilitate the removal of the molded package body at the gate 280 without the adhesion force between the molded package body and the circuit board, the trapezoid shaped gate hole 16 b may be used. Because the gate hole 16 b has a gate with a narrow width and a small dimension, a gate neck may not be required.
  • In the case of the square shaped gate hole 16 a, 16 c, the molten molding compound 250 a can easily flow because the width of the gate 280 is broad and the dimension of the gate 280 is large. As shown in FIG. 9 a, the gate neck 240 is formed within the gate hole 16 a, 16 c. Therefore, the molding body of the runner area can be easily removed and the adhesion force between the molding body and the circuit board does not decrease in the gate area. Particularly, the extended gate hole 16 c of the square type increases the flowing ability of the molten molding compound 250 a passed through gate neck 240 into cavity 230.
  • FIG. 9 b is an enlarged sectional view of FIG. 9 a. In this particular embodiment the gate has a length of the gate is 2 mm.
  • The upper gate piece 215 comprises a first incline 215 a and a second incline 215 b. The first incline 215 a is connected to the runner 270 and the second incline 215 b is connected to the cavity 230. The first incline 215 a and the second incline 215 b form the upper surface of the gate. The lower gate piece 225 comprises a third incline 225 a and a forth incline 225 b. The third incline 225 a is connected to the runner 270 and the forth incline 225 b is connected to the cavity 230. The second incline 225 a and the forth incline 225 b form the second surface of the gate. The length of the gate neck 240 is 0.5 mm and the height of the gate neck 240 is 0.16 mm. The distance from the gate neck 240 to the cavity 230 is 0.6 mm. The dimension of the cavity 230 is 0.85 mm and the horizontal angle for the second and forth inclines 215 b, 225 b is 30 degrees. The horizontal angle for the first incline 215 a is 50 degrees and the horizontal angle for the third incline 225 a is 8 degrees.
  • In some embodiments of the present invention, a multi-chip package having a package body on both surfaces of the circuit board is manufactured by a wire bonding technique and an injection molding technique using conventional plastic package fabrication processes.
  • Since the package body is formed on both sides of the circuit board by one molding step, the productivity of manufacture of the multi-chip package can be increased.
  • Further, the multi-chip package of the present invention having the double dies may be thinner than conventional packages.
  • According to the present invention, mass production of the multi-chip package can be performed without any additional wire looping technique.
  • According to the present invention, the multi-chip package may use various chips.
  • Embodiments listed above illustrate, but do not limit, the invention. Although the present invention has been described in detail herein above with respect to the preferred embodiments thereof many variations and/or modifications thereof will be apparent to those of ordinary skill in the art. Therefore, all such variations and modifications are seen to fall within the true spirit and scope of the present invention as defined by the appended claims.

Claims (4)

  1. 1-22. (canceled)
  2. 23. A method of manufacturing a multi-chip package, comprising:
    providing a circuit board between an upper molding die and a lower molding die, the circuit board including a first surface having a first chip mounted and electrically connected thereto, a second surface having a second chip mounted and electrically connected thereto, and a gate hole formed from the first surface to the second surface, wherein the second surface faces the lower molding die;
    closing the molding dies to form a cavity in which the chips are kept; and
    injecting molding compound into the cavity, wherein the molding compound flows through the gate hole to encase portions of the first surface and the second surface.
  3. 24. The method of claim 23, further comprising:
    compressing a molding pellet into a through hole in the upper molding die.
  4. 25. The method of claim 23, wherein the upper molding die and the lower molding die combine to form a gate neck located in the gate hole.
US11606284 2001-06-29 2006-11-30 Double-sided circuit board and multi-chip package including such a circuit board and method for manufacture Abandoned US20070096288A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR20010038191A KR100415281B1 (en) 2001-06-29 2001-06-29 Double-side Mounting Circuit Board and Multi Chip Package including the Such a Circuit Board
KR2001-0038191 2001-06-29
US10186101 US7170158B2 (en) 2001-06-29 2002-06-27 Double-sided circuit board and multi-chip package including such a circuit board and method for manufacture
US11606284 US20070096288A1 (en) 2001-06-29 2006-11-30 Double-sided circuit board and multi-chip package including such a circuit board and method for manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11606284 US20070096288A1 (en) 2001-06-29 2006-11-30 Double-sided circuit board and multi-chip package including such a circuit board and method for manufacture

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10186101 Division US7170158B2 (en) 2001-06-29 2002-06-27 Double-sided circuit board and multi-chip package including such a circuit board and method for manufacture

Publications (1)

Publication Number Publication Date
US20070096288A1 true true US20070096288A1 (en) 2007-05-03

Family

ID=19711543

Family Applications (2)

Application Number Title Priority Date Filing Date
US10186101 Active US7170158B2 (en) 2001-06-29 2002-06-27 Double-sided circuit board and multi-chip package including such a circuit board and method for manufacture
US11606284 Abandoned US20070096288A1 (en) 2001-06-29 2006-11-30 Double-sided circuit board and multi-chip package including such a circuit board and method for manufacture

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US10186101 Active US7170158B2 (en) 2001-06-29 2002-06-27 Double-sided circuit board and multi-chip package including such a circuit board and method for manufacture

Country Status (3)

Country Link
US (2) US7170158B2 (en)
KR (1) KR100415281B1 (en)
DE (1) DE10229692B4 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080179722A1 (en) * 2007-01-31 2008-07-31 Cyntec Co., Ltd. Electronic package structure
DE102010062761A1 (en) * 2010-12-09 2012-06-14 Zf Friedrichshafen Ag Electronic circuit module for motor car, has overmold material which is bonded on both sides of printed circuit board mounted with electronic component
US9930789B2 (en) 2010-04-12 2018-03-27 Seagate Technology Llc Flexible printed circuit cable with multi-layer interconnection and method of forming the same

Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10297823T5 (en) * 2002-12-10 2005-10-20 Infineon Technologies Ag A method of intergrated circuits and capsules made on the procedure integrated circuit blocks
US7279785B2 (en) * 2005-02-14 2007-10-09 Stats Chippac Ltd. Stacked die package system
US20070052079A1 (en) * 2005-09-07 2007-03-08 Macronix International Co., Ltd. Multi-chip stacking package structure
US7511371B2 (en) * 2005-11-01 2009-03-31 Sandisk Corporation Multiple die integrated circuit package
US8203214B2 (en) * 2007-06-27 2012-06-19 Stats Chippac Ltd. Integrated circuit package in package system with adhesiveless package attach
CN101656246B (en) 2008-08-19 2011-11-09 南茂科技股份有限公司 Chip-stacked package structure of substrate with opening and packaging method thereof
US20100052186A1 (en) * 2008-08-27 2010-03-04 Advanced Semiconductor Engineering, Inc. Stacked type chip package structure
KR100997793B1 (en) 2008-09-01 2010-12-02 주식회사 하이닉스반도체 Semiconductor pacakge and method of manufacturing thereof
KR100949551B1 (en) * 2009-04-10 2010-03-25 (주)비엠케이테크놀로지 Hybrid memory module and method for manufacturing the same
KR101583719B1 (en) * 2009-07-21 2016-01-11 삼성전자주식회사 The semiconductor package and a method of manufacturing the same
US8008121B2 (en) 2009-11-04 2011-08-30 Stats Chippac, Ltd. Semiconductor package and method of mounting semiconductor die to opposite sides of TSV substrate
US8569885B2 (en) * 2010-10-29 2013-10-29 Advanced Semiconductor Engineering, Inc. Stacked semiconductor packages and related methods
US8514576B1 (en) * 2011-06-14 2013-08-20 Juniper Networks, Inc. Dual sided system in a package
US8823165B2 (en) 2011-07-12 2014-09-02 Invensas Corporation Memory module in a package
US8513817B2 (en) 2011-07-12 2013-08-20 Invensas Corporation Memory module in a package
US8502390B2 (en) 2011-07-12 2013-08-06 Tessera, Inc. De-skewed multi-die packages
US8603859B2 (en) 2011-09-16 2013-12-10 Stats Chippac Ltd. Integrated circuit packaging system with dual side mold and method of manufacture thereof
US8659140B2 (en) 2011-10-03 2014-02-25 Invensas Corporation Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate
EP2764544A1 (en) 2011-10-03 2014-08-13 Invensas Corporation Stub minimization for multi-die wirebond assemblies with parallel windows
US8659141B2 (en) 2011-10-03 2014-02-25 Invensas Corporation Stub minimization using duplicate sets of terminals for wirebond assemblies without windows
US8441111B2 (en) 2011-10-03 2013-05-14 Invensas Corporation Stub minimization for multi-die wirebond assemblies with parallel windows
US8917532B2 (en) 2011-10-03 2014-12-23 Invensas Corporation Stub minimization with terminal grids offset from center of package
US8525327B2 (en) * 2011-10-03 2013-09-03 Invensas Corporation Stub minimization for assemblies without wirebonds to package substrate
JP5947904B2 (en) 2011-10-03 2016-07-06 インヴェンサス・コーポレイション Stub minimized for multi-die wire bond assembly with orthogonal window
US8405207B1 (en) 2011-10-03 2013-03-26 Invensas Corporation Stub minimization for wirebond assemblies without windows
US8436457B2 (en) 2011-10-03 2013-05-07 Invensas Corporation Stub minimization for multi-die wirebond assemblies with parallel windows
US8848392B2 (en) 2012-08-27 2014-09-30 Invensas Corporation Co-support module and microelectronic assembly
US8787034B2 (en) 2012-08-27 2014-07-22 Invensas Corporation Co-support system and microelectronic assembly
US8848391B2 (en) 2012-08-27 2014-09-30 Invensas Corporation Co-support component and microelectronic assembly
US9368477B2 (en) 2012-08-27 2016-06-14 Invensas Corporation Co-support circuit panel and microelectronic packages
US9070423B2 (en) 2013-06-11 2015-06-30 Invensas Corporation Single package dual channel memory with co-support
US9123555B2 (en) 2013-10-25 2015-09-01 Invensas Corporation Co-support for XFD packaging
KR20150053579A (en) * 2013-11-08 2015-05-18 삼성전기주식회사 Electric component module and manufacturing method threrof
US9281296B2 (en) 2014-07-31 2016-03-08 Invensas Corporation Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard design
US9691437B2 (en) 2014-09-25 2017-06-27 Invensas Corporation Compact microelectronic assembly having reduced spacing between controller and memory packages
US9240370B1 (en) * 2014-12-15 2016-01-19 Industrial Technology Research Institute Power module
US9418921B2 (en) 2014-12-15 2016-08-16 Industrial Technology Research Institute Power module
US20160339616A1 (en) * 2015-05-22 2016-11-24 Infineon Technologies Ag Method and Apparatus for Simultaneously Encapsulating Semiconductor Dies with Layered Lead Frame Strips
US9484080B1 (en) 2015-11-09 2016-11-01 Invensas Corporation High-bandwidth memory application with controlled impedance loading
US9721881B1 (en) 2016-04-29 2017-08-01 Nxp Usa, Inc. Apparatus and methods for multi-die packaging
US9679613B1 (en) 2016-05-06 2017-06-13 Invensas Corporation TFD I/O partition for high-speed, high-density applications

Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5239198A (en) * 1989-09-06 1993-08-24 Motorola, Inc. Overmolded semiconductor device having solder ball and edge lead connective structure
US5275546A (en) * 1991-12-30 1994-01-04 Fierkens Richard H J Plastic encapsulation apparatus for an integrated circuit lead frame and method therefor
US5395226A (en) * 1993-02-23 1995-03-07 Mitsubishi Denki Kabushiki Kaisha Molding machine and method
US5471369A (en) * 1993-07-09 1995-11-28 Fujitsu Limited Semiconductor device having a plurality of semiconductor chips
US5527740A (en) * 1994-06-28 1996-06-18 Intel Corporation Manufacturing dual sided wire bonded integrated circuit chip packages using offset wire bonds and support block cavities
US5594626A (en) * 1992-02-07 1997-01-14 Lsi Logic Corporation Partially-molded, PCB chip carrier package for certain non-square die shapes
US5635671A (en) * 1994-03-16 1997-06-03 Amkor Electronics, Inc. Mold runner removal from a substrate-based packaged electronic device
US5679978A (en) * 1993-12-06 1997-10-21 Fujitsu Limited Semiconductor device having resin gate hole through substrate for resin encapsulation
US5684327A (en) * 1994-09-15 1997-11-04 Kabushiki Kaisha Toshiba Lead frame for use in a resin-sealed type semiconductor device
US5780779A (en) * 1995-09-11 1998-07-14 Kyoji Co., Ltd. Granule gate and granule weighing machine incorporating the same
US5815372A (en) * 1997-03-25 1998-09-29 Intel Corporation Packaging multiple dies on a ball grid array substrate
US5917242A (en) * 1996-05-20 1999-06-29 Micron Technology, Inc. Combination of semiconductor interconnect
US5981873A (en) * 1996-12-27 1999-11-09 Anam Semiconductor Inc. Printed circuit board for ball grid array semiconductor package
US6118184A (en) * 1997-07-18 2000-09-12 Sharp Kabushiki Kaisha Semiconductor device sealed with a sealing resin and including structure to balance sealing resin flow
US6441495B1 (en) * 1997-10-06 2002-08-27 Rohm Co., Ltd. Semiconductor device of stacked chips
US6489687B1 (en) * 1999-10-01 2002-12-03 Seiko Epson Corporation Semiconductor device and method of manufacturing the same, manufacturing device, circuit board, and electronic equipment

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6119117B2 (en) * 1979-09-27 1986-05-15 Hitachi Chemical Co Ltd
WO1996013855A1 (en) 1994-10-27 1996-05-09 National Semiconductor Corporation A leadframe for an integrated circuit package which electrically interconnects multiple integrated circuit die
JP3165959B2 (en) 1997-10-06 2001-05-14 ローム株式会社 The semiconductor chip mounting structure and a semiconductor device
JPH11135537A (en) 1997-10-29 1999-05-21 Rohm Co Ltd Mounting structure for semiconductor chip and semiconductor device
JP3055619B2 (en) 1998-04-30 2000-06-26 日本電気株式会社 Semiconductor device and manufacturing method thereof

Patent Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5273938A (en) * 1989-09-06 1993-12-28 Motorola, Inc. Method for attaching conductive traces to plural, stacked, encapsulated semiconductor die using a removable transfer film
US5239198A (en) * 1989-09-06 1993-08-24 Motorola, Inc. Overmolded semiconductor device having solder ball and edge lead connective structure
US5275546A (en) * 1991-12-30 1994-01-04 Fierkens Richard H J Plastic encapsulation apparatus for an integrated circuit lead frame and method therefor
US5594626A (en) * 1992-02-07 1997-01-14 Lsi Logic Corporation Partially-molded, PCB chip carrier package for certain non-square die shapes
US5395226A (en) * 1993-02-23 1995-03-07 Mitsubishi Denki Kabushiki Kaisha Molding machine and method
US5471369A (en) * 1993-07-09 1995-11-28 Fujitsu Limited Semiconductor device having a plurality of semiconductor chips
US5679978A (en) * 1993-12-06 1997-10-21 Fujitsu Limited Semiconductor device having resin gate hole through substrate for resin encapsulation
US5635671A (en) * 1994-03-16 1997-06-03 Amkor Electronics, Inc. Mold runner removal from a substrate-based packaged electronic device
US5545922A (en) * 1994-06-28 1996-08-13 Intel Corporation Dual sided integrated circuit chip package with offset wire bonds and support block cavities
US5527740A (en) * 1994-06-28 1996-06-18 Intel Corporation Manufacturing dual sided wire bonded integrated circuit chip packages using offset wire bonds and support block cavities
US5684327A (en) * 1994-09-15 1997-11-04 Kabushiki Kaisha Toshiba Lead frame for use in a resin-sealed type semiconductor device
US5780779A (en) * 1995-09-11 1998-07-14 Kyoji Co., Ltd. Granule gate and granule weighing machine incorporating the same
US5917242A (en) * 1996-05-20 1999-06-29 Micron Technology, Inc. Combination of semiconductor interconnect
US5981873A (en) * 1996-12-27 1999-11-09 Anam Semiconductor Inc. Printed circuit board for ball grid array semiconductor package
US5815372A (en) * 1997-03-25 1998-09-29 Intel Corporation Packaging multiple dies on a ball grid array substrate
US6118184A (en) * 1997-07-18 2000-09-12 Sharp Kabushiki Kaisha Semiconductor device sealed with a sealing resin and including structure to balance sealing resin flow
US6441495B1 (en) * 1997-10-06 2002-08-27 Rohm Co., Ltd. Semiconductor device of stacked chips
US6489687B1 (en) * 1999-10-01 2002-12-03 Seiko Epson Corporation Semiconductor device and method of manufacturing the same, manufacturing device, circuit board, and electronic equipment

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080179722A1 (en) * 2007-01-31 2008-07-31 Cyntec Co., Ltd. Electronic package structure
US9930789B2 (en) 2010-04-12 2018-03-27 Seagate Technology Llc Flexible printed circuit cable with multi-layer interconnection and method of forming the same
DE102010062761A1 (en) * 2010-12-09 2012-06-14 Zf Friedrichshafen Ag Electronic circuit module for motor car, has overmold material which is bonded on both sides of printed circuit board mounted with electronic component

Also Published As

Publication number Publication date Type
KR100415281B1 (en) 2004-01-16 grant
US20030015782A1 (en) 2003-01-23 application
DE10229692B4 (en) 2007-09-27 grant
KR20030002539A (en) 2003-01-09 application
US7170158B2 (en) 2007-01-30 grant
DE10229692A1 (en) 2003-03-13 application

Similar Documents

Publication Publication Date Title
US6093584A (en) Method for encapsulating a semiconductor package having apertures through a sacrificial layer and contact pads
US5900676A (en) Semiconductor device package structure having column leads and a method for production thereof
US6414391B1 (en) Module assembly for stacked BGA packages with a common bus bar in the assembly
US6201302B1 (en) Semiconductor package having multi-dies
US5872399A (en) Solder ball land metal structure of ball grid semiconductor package
US6982485B1 (en) Stacking structure for semiconductor chips and a semiconductor package using it
US6445077B1 (en) Semiconductor chip package
US6828665B2 (en) Module device of stacked semiconductor packages and method for fabricating the same
US7008822B2 (en) Method for fabricating semiconductor component having stacked, encapsulated dice
US6861737B1 (en) Semiconductor device packages having semiconductor chips attached to circuit boards, and stack packages using the same
US6781242B1 (en) Thin ball grid array package
US6836009B2 (en) Packaged microelectronic components
US6781243B1 (en) Leadless leadframe package substitute and stack package
US7777351B1 (en) Thin stacked interposer package
US8618659B2 (en) Package-on-package assembly with wire bonds to encapsulation surface
US6818980B1 (en) Stacked semiconductor package and method of manufacturing the same
US20070045834A1 (en) Interconnecting substrates for microelectronic dies, methods for forming vias in such substrates, and methods for packaging microelectronic devices
US20070290376A1 (en) Integrated circuit (IC) package stacking and IC packages formed by same
US6566168B2 (en) Semiconductor package having implantable conductive lands and method for manufacturing the same
US6060778A (en) Ball grid array package
US20020142513A1 (en) Ball grid array interposer, packages and methods
US20020158318A1 (en) Multi-chip module
US20030164543A1 (en) Interposer configured to reduce the profiles of semiconductor device assemblies and packages including the same and methods
US6720666B2 (en) BOC BGA package for die with I-shaped bond pad layout
US6692987B2 (en) BOC BGA package for die with I-shaped bond pad layout