JP2000058699A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize high density integration such as multipins and narrow pitchs at a low manufacturing cost and with high efficiency, by arranging a plurality of terminals connected with a semiconductor chip terminals in such a manner that intervals between neighboring terminals are made equal. SOLUTION: Solder bumps (HB) 15 are arranged as I/O terminals of a BGA on the bottom surface of a PCB board in such a manner that intervals between the neighboring HB's 15 are made equal. Since the interval between the neighboring HB's 15 are equal, a line connecting the center line S of six HB 15b, 15c, 15g, 15j, 15e which are adjacent to an HB 15f forms a hexagon. As a result, density per unit area of the HB's 15 is increased as compared with conventional grid arrangement shown by a two-dod chain line, and a semiconductor device coping with high density integration such as multipins and narrow pitchs can be realized at a low manufacturing cost and with high efficiency.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a plurality of input / output terminals and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, semiconductor devices such as IC chips have been mounted on various electronic devices, and the range of use thereof has tended to further expand in the future. With the expansion of applications for semiconductor devices,
There is an increasing demand for further improving the performance and reducing the size of electronic devices on which semiconductor devices are mounted.

In general, the number of I / O points of a semiconductor chip increases as the speed and performance of the semiconductor chip increase. An increase in the number of I / O points leads to an increase in input / output terminals (hereinafter, referred to as “pins” or simply “terminals”), which often leads to an increase in semiconductor package size. In recent years, with the progress of semiconductor package technology, there is a tendency that the increase in the package size is suppressed as much as possible in response to the movement to increase the number of pins and to narrow the pitch between pins. Further, a technology that can further reduce the pitch between pins has been developed, and further miniaturization of semiconductor devices has been progressing along with miniaturization and higher performance of semiconductor chips.

As a semiconductor device corresponding to such a multi-pin and narrow pitch, a PGA (Pin Grid Arr) in which terminals are two-dimensionally arranged in one plane of a semiconductor package is known.
ay), LGA (Land Grid Array), or BGA
(Ball Grid Array) and the like are generally well known. In recent years, a CSP (Chip Size Packag) packaged with almost the same dimensions as the outer shape of a semiconductor chip has recently appeared.
e) and MCMs (Multi Chip Modules) in which a plurality of semiconductor chips are densely mounted in one semiconductor device in order to reduce signal delay between chips, etc. Are arranged to cope with multi-pin and narrow pitch.

[0005]

As shown in FIG. 4, terminals of a so-called "high-density" semiconductor device such as a multi-pin structure and a narrow pitch generally have a grid (or "grid") in one plane. ). However, since the terminal arrangement shown in FIG. 4 is a grid-like arrangement, the PIN 105, the PIN 102, the PIN 104,
For the spacing between PIN 106 and PIN 108, P
IN105, PIN101, PIN103, PIN10
Naturally, the distance between the terminal 7 and the PIN 109 is widened, and there is a disadvantage that the terminal arrangement cannot be further densified.

In manufacturing a semiconductor device, a through-hole (or "via hole") is often formed in an interposer of a package in accordance with a pin arrangement position in order to conduct between formation layers. In such a case, as shown in FIG. 4, a PIN 102, a PIN 104, and a PIN
6 and PIN108, PIN101, PIN103, PIN1 which are diagonally adjacent to PIN105.
Since the distance between the through hole and the PIN 107 is smaller than the distance between the through hole and the PIN 109, the hole diameter of the through hole needs to be determined based on the former narrower distance. That is, since the drill diameter for forming the through hole is limited to the smaller diameter, the wear of the drill is accelerated, so that the drill needs to be replaced frequently. As a result, there is a disadvantage that the manufacturing cost of the semiconductor device increases. In addition, frequent replacement of drills is inefficient in terms of work efficiency.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a semiconductor device and a semiconductor device capable of realizing high density such as increase in the number of pins and narrow pitch with low manufacturing cost and high working efficiency. The manufacturing method will be provided.

[0008]

In order to achieve the above object, in a semiconductor device according to the present invention, at least one semiconductor chip is sealed, and at least one surface is connected to a connection terminal of the semiconductor chip. A semiconductor device in which a plurality of terminals are arranged, wherein the plurality of terminals are arranged such that intervals between adjacent terminals are equal to each other. Further, in the semiconductor device of the present invention, preferably, the base on which the semiconductor chip is mounted is formed with a plurality of through holes for conducting the semiconductor chip and the terminals, and the plurality of through holes are formed. The through holes are arranged such that the intervals between the adjacent through holes are equal to each other. More preferably, the through-hole is disposed at substantially the same position as the terminal.

According to a method of manufacturing a semiconductor device of the present invention, at least one semiconductor chip is sealed, and a plurality of terminals connected to connection terminals of the semiconductor chip are arranged on at least one surface side. A method of forming pad portions on which the terminals are mounted on a base on which the semiconductor chip is mounted so that the intervals between adjacent pad portions are equal to each other; and Attaching the terminals to the respective pad portions formed in the above. In the method of manufacturing a semiconductor device according to the present invention, preferably, after the pad portion is formed, a plurality of through-holes for electrically connecting the semiconductor chip and the terminal are formed on the base, respectively. Forming the pad portion at substantially the same position as the position where the pad portion is formed, and filling the through hole with a conductive material so that the semiconductor chip and the terminal are electrically connected. And a process.

[0010] According to the semiconductor device of the present invention, a plurality of terminals are arranged on one surface side of the semiconductor device so that the intervals between adjacent terminals are equal to each other. This allows
Even if the connection terminals of the semiconductor chip increase, the terminals connected to the connection terminals can be arranged, for example, in a high-density state.

According to the method of manufacturing a semiconductor device of the present invention,
On a base on which at least one semiconductor chip is mounted, pad portions connected to respective connection terminals of the semiconductor chips are formed such that intervals between adjacent pad portions are equal to each other. After the formation of the pad portion, a plurality of through holes for conducting the semiconductor chip and the terminals are formed at the same position as the pad portion formation position. Thereafter, the through hole is filled with, for example, copper, and finally, for example, a terminal such as a substantially spherical solder body is attached.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described below in detail with reference to the drawings. 1A is a perspective view of a semiconductor device according to the present invention, FIG. 1B is an enlarged sectional view of a main part of the semiconductor device shown in FIG. 1A, and FIG. 2 is a semiconductor device shown in FIG. And FIG. 3 is a diagram for explaining a position where a through hole is formed in the semiconductor device shown in FIG.

The semiconductor device shown in FIG. 1 is a BGA 1 as a surface mount area array package, and a PCB substrate 10 is used as a printed circuit board. PCB
The substrate 10 is made of a BT epoxy material (Bi Bi) having improved heat resistance in consideration of severe heat treatment until it becomes a BGA package.
Smallemide Triazine) has been used.

On the upper surface of the PCB board 10, a wiring pattern 12, a diamond touch pattern, a signal pattern, a ground pattern, and a power supply pattern are respectively wired. These wiring patterns 12 are formed by plated copper wiring.

A die pad 13 is provided on the upper surface of the PCB substrate 10.
Are mounted, and the IC chip 14 is further mounted on the die pad 13. The IC chip 14 and the die pad 13 are die-bonded via an epoxy-based silver paste applied to a region 13a shown in FIG. The IC chip 14 is wire-bonded to the wiring pattern 12 including a diamond touch pattern, a signal pattern, a ground pattern, a power supply pattern, and the like by a gold wire bonder as shown in FIG. 1B. ing.

As shown in FIG. 2, a solder bump (FIG. 2) formed in a substantially ball shape is formed on the bottom surface of the PCB substrate 10.
In this case, “HB” 15 is disposed as an I / O terminal of the BGA 1 such that the intervals between the adjacent solder bumps 15 are equal to each other. Therefore, FIG.
As can be seen from FIG. 7, the intervals between the adjacent solder bumps 15 are equal to each other, and the six solder bumps 15b, 15c, 15g, and 15 adjacent to the solder bump 15f are provided.
The line connecting the center points (not shown) of j, 15i, and 15e forms a regular hexagon. Therefore, the density per unit area of the solder bumps 15 is increased as compared with the conventional grid-like arrangement shown by a two-dot chain line in FIG. 2, and it is possible to cope with an increase in the number of pins and a narrow pitch. .

The solder bumps 15 are automatically mounted by a solder ball mounting device (not shown) so that the solder bumps 15 are arranged as described above. At this time, the arrangement state, that is, the deviation from the reference value of the arrangement position and the PCB board 1
From the viewpoint of preventing a mounting failure on the motherboard due to a variation in the height of the solder bumps 15, the height of the height from the bottom of the solder bumps 15 is automatically checked by a measuring device.
Note that a eutectic metal of lead and tin is used as a material for forming the solder bump 15.

At the mounting position of the solder bump 15 on the PCB substrate 10, a solder resist 11 is formed as an opening. Since the width of the opening of the solder resist 11 and the thickness of the solder resist 11 affect the height of the solder bump 15, it is necessary to accurately control the width and the thickness of the opening of the solder resist 11. is there.

Further, as shown in FIG. 1B, a plurality of thermal vias (Thermal VIA) 16 are formed on the diamond matching surface on the PCB substrate 10 to improve heat dissipation. -It is connected to the bump 15. The ground solder bumps 15 (not shown) are further coupled to a ground plane of a mother board (not shown) so as to more effectively dissipate heat dissipation.

As shown in FIG. 1B, the IC chip 14
Is molded by a mold resin 17 so that the IC chip 14 is sealed. Further, since the adhesion between the gold-plated portion on the wiring and the mold resin 17 is extremely important for the performance of the BGA 1, it is desirable to limit the gold-plated portion to only the wire bonder region.

The BGA 1 has a solder
A through-hole (not shown) is arranged near a bonding pad (not shown) to which the bump 15 is attached. Copper is inserted into this through-hole, whereby the input / output terminals of the IC chip 14 and the solder bumps 15 are directly connected to each other at the shortest distance, thereby shortening the wiring and further increasing the speed.

A method for manufacturing the BGA 1 of the present invention will be described. Through holes and thermal vias 16 (not shown) are formed on the PCB substrate 10 cut into a predetermined size using a drill or the like such that six adjacent holes are equally spaced from each other. The formed through holes and the thermal vias 16 are filled with a highly conductive metal such as gold or copper in advance. Next, a solder resist 11 is formed on both sides of the PCB substrate 10 using a dry film. The positions of the openings for the solder bumps 15 formed on the bottom surface side of the PCB substrate 10 are such that six adjacent openings are equally spaced from each other.

After the solder resist 11 is formed, a die pad 13 made of a metal material having a smaller thermal expansion coefficient than the material of the mold resin 17 is placed on the center of the upper surface of the PCB substrate 10, and a resist film is deposited from above. . After depositing the resist film, the copper-based material and the die pad 13 are processed by photoetching to form the wiring pattern 12.

Silver paste application area 1 on die pad 13
A silver paste is applied to 3a, and the IC chip 14 cut out from the semiconductor wafer by dicing is placed on the silver paste application area 13a and pressure-bonded. The silver paste contains a thermosetting resin. After the pressure bonding, the substrate is cured by heating at a high temperature, so that the IC chip 14 is completely bonded to the die pad 13.

After the IC chip 14 is bonded to the die pad 13, the external connection terminals of the IC chip 14 and the wiring pattern 12 are wire-bonded using gold wires. After this,
The regions shown in FIGS. 1A and 1B are resin-sealed with, for example, a mold resin mainly containing an epoxy resin, a curing agent and a filler. After resin sealing, the solder pieces punched from the solder ribbon are mounted on pads formed on the bottom surface of the PCB substrate 10 and reflowed, and the solder bumps 15 are formed.
Are automatically mounted using a mounting device so that they are substantially equidistant between adjacent ones. Finally, remove burrs and finish.

BGA1 manufactured through the above-described steps
Are attached to a motherboard (not shown) via solder bumps 15. At this time, since the solder bumps 15 are arranged at substantially equal intervals between adjacent ones, the number of the solder bumps 15 per unit area increases, and more connection points are formed on the motherboard. Will be attached. Therefore, the BGA 1 and the motherboard are more firmly connected.

As described above, according to the present embodiment, the solder bumps 15 as the external connection terminals adjacent to each other are arranged on the bottom surface of the PCB substrate 10 at substantially equal intervals. As shown in FIG. 2, a higher density terminal arrangement can be realized as compared with a conventional grid-like arrangement state (indicated by a two-dot chain line in FIG. 2) in which the same spacing as in the present embodiment is provided. Becomes possible. As a result, the number of terminals per unit area increases, so that it is not necessary to increase the size of the semiconductor package as the number of terminals increases.
In addition, since it is possible to connect to the motherboard at more connection points, the BGA1 as a semiconductor package is used.
And the connection strength between the motherboard and
The mounting quality of GA1 is also improved.

According to the present embodiment, through holes (not shown) are formed at respective positions of the solder bumps 15 arranged on the BGA 1 and copper is inserted therein.
The input / output terminals of the C chip 14 and the solder bumps 15 are directly connected to each other at the shortest distance. Thus, a semiconductor device which can sufficiently cope with high speed operation can be provided.

Further, according to the present embodiment, the solder
Since the distance between the adjacent solder bumps 15 is equal to each other when the through hole is formed at each position of the bump 15, as shown in FIG. A drill diameter 2 / √3 times larger than the standard can be selected. As a result, the diameter of the drill can be increased, so that the drill lasts longer, and at the same time, the number of man-hours for drill replacement can be reduced. As a result, the semiconductor package can be manufactured at lower cost.

In this embodiment, the arrangement of the BGA terminals has been described, but the arrangement of the external terminals is not limited to this. In other words, a hermetic sealing type package PG often used for a semiconductor device of a high-performance electronic device or a large semiconductor device.
A pin layout, LGA pad layout, CS described above
The same can be applied to the terminal arrangement of P or the terminal arrangement of MCM described above. In the case of PGA or the like, for example, lead pins are set up at the positions of pads to which solder balls are attached.

[0031]

According to the present invention, there is an advantage that a semiconductor device corresponding to high density such as increase in the number of pins and narrow pitch can be realized with low manufacturing cost and high work efficiency.

[Brief description of the drawings]

FIG. 1A is a perspective view of a semiconductor device according to the present invention, and FIG. 1B is an enlarged cross-sectional view of a main part of the semiconductor device shown in FIG. 1A.

FIG. 2 is a diagram for explaining an arrangement state of input / output terminals of the semiconductor device shown in FIG. 1;

FIG. 3 is a view for explaining positions where through holes are formed in the semiconductor device shown in FIG. 1;

FIG. 4 is a diagram illustrating an arrangement of pins of a conventional semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... BGA, 10 ... PCB board, 11 ... Solder resist, 12 ... Wiring pattern, 13 ... Die pad, 13a ...
Silver paste application area, 14: IC chip, 15: Solder bump, 16: Thermal via, 17: Mold resin

Claims (8)

[Claims] At least one semiconductor chip is sealed,
A semiconductor device in which a plurality of terminals connected to connection terminals of the semiconductor chip are arranged on at least one surface side, wherein the plurality of terminals are arranged such that intervals between adjacent terminals are equal to each other. Semiconductor device. 2. A base on which the semiconductor chip is mounted has a plurality of through-holes for conducting the semiconductor chip and the terminals, and the plurality of through-holes are respectively adjacent to the through-holes. 2. The semiconductor device according to claim 1, wherein the distance from the holes is equal to each other. 3. The semiconductor device according to claim 2, wherein said through hole is disposed at substantially the same position as said terminal. 4. The base has a plurality of radiating holes for cooling the semiconductor chip when the semiconductor chip is conductive. The plurality of radiating holes are spaced apart from adjacent radiating holes. The semiconductor device according to claim 2, wherein the semiconductor devices are formed near the arrangement position of the terminals so as to be at equal intervals. 5. The semiconductor device according to claim 2, wherein said terminal comprises a solder body formed in a substantially spherical shape, and said base has a plurality of pad portions connected to said solder body. 6. The semiconductor device according to claim 2, wherein said terminal comprises a lead pin, and said base has a plurality of pad portions connected to said lead pin. 7. At least one semiconductor chip is sealed,
A method of manufacturing a semiconductor device in which a plurality of terminals connected to connection terminals of the semiconductor chip are arranged on at least one surface side, wherein a pad portion to which the terminals are attached is provided on a base on which the semiconductor chip is mounted. And a step of attaching the terminal to each of the pad portions formed on the base, and forming the terminals so that the intervals between the adjacent pad portions are equal to each other. 8. After the pad portion is formed, a plurality of through holes for electrically connecting the semiconductor chip and the terminals are formed on the base so that intervals between adjacent through holes are equal to each other. 8. The semiconductor device according to claim 7, further comprising: a step of forming the pad portion at substantially the same position as a position where the pad portion is formed; and a step of filling the through hole with a conductive material so that the semiconductor chip and the terminal are electrically connected. Manufacturing method.