CN114068470A - Structure for expanding ball grid array packaging I/O port and manufacturing method thereof - Google Patents

Structure for expanding ball grid array packaging I/O port and manufacturing method thereof Download PDF

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Publication number
CN114068470A
CN114068470A CN202111354586.8A CN202111354586A CN114068470A CN 114068470 A CN114068470 A CN 114068470A CN 202111354586 A CN202111354586 A CN 202111354586A CN 114068470 A CN114068470 A CN 114068470A
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CN
China
Prior art keywords
substrate
lead frame
grid array
pads
ball grid
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Pending
Application number
CN202111354586.8A
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Chinese (zh)
Inventor
胡文华
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Center for Advanced Packaging Co Ltd
Shanghai Xianfang Semiconductor Co Ltd
Original Assignee
National Center for Advanced Packaging Co Ltd
Shanghai Xianfang Semiconductor Co Ltd
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Publication date
Application filed by National Center for Advanced Packaging Co Ltd, Shanghai Xianfang Semiconductor Co Ltd filed Critical National Center for Advanced Packaging Co Ltd
Priority to CN202111354586.8A priority Critical patent/CN114068470A/en
Publication of CN114068470A publication Critical patent/CN114068470A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

The invention relates to a structure for expanding a ball grid array packaging I/O port, which comprises: a substrate having a first side and a second side opposite the first side; a lead frame which is arranged at the edge of the substrate and is connected with the substrate in a welding mode; a chip flip-chip mounted on the substrate; the heat dissipation cover is attached to the first surface of the substrate, and the periphery of the heat dissipation cover is bonded to the first surface of the lead frame; and solder balls disposed on the pads on the second side of the substrate and the second side of the lead frame.

Description

Structure for expanding ball grid array packaging I/O port and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a structure for expanding a ball grid array packaging I/O port and a manufacturing method thereof.
Background
The FCBGA (Flip Chip Ball Grid array) package is called a flip Chip Ball Grid array package, and has the following advantages:
(1) the FCBGA package not only provides excellent electrical performance, but also reduces the loss and inductance between the component interconnections, reduces the problem of electromagnetic interference, and bears higher frequency, and the breakthrough of the over-frequency limit becomes possible.
(2) With FCBGA packaging, I/O leads can be arranged in an array on the surface of the chip, providing a higher density of I/O layout, resulting in the best utilization efficiency, and because of this advantage, the flip-chip technology is reduced in area by 30% to 60% compared to conventional packaging.
(3) Based on the unique flip-chip packaging form of the FCBGA, the back surface of the chip can be contacted with air, heat can be directly dissipated, and the stability of the chip in high-speed operation is improved.
FCBGA packages are increasingly used because of their many advantages.
Fig. 4 shows top, bottom and interface views of a FCBGA package of the prior art.
The substrate is an indispensable part in FCBGA encapsulation, and the substrate can provide functions such as electric connection, protection, support, heat dissipation, equipment for the chip to realize the purposes of multi-pin, reduce the volume of the encapsulated product, improve electrical property and heat dissipation, and ultrahigh density or multi-chip modularization. As the package size gradually increases, the cost of the package substrate also gradually increases. Reducing the cost of the substrate can greatly reduce the cost of the FCBGA package.
Disclosure of Invention
The invention aims to provide a structure for expanding a ball grid array packaging I/O port and a manufacturing method thereof, which effectively save the area of a packaging substrate under the condition of keeping the total quantity of I/O of a packaging chip unchanged by welding a connecting pad at the edge of the substrate, thereby reducing the cost of the substrate.
In a first aspect of the present invention, aiming at the problems in the prior art, the present invention provides a structure for expanding I/O ports of a ball grid array package, comprising:
a substrate having a first side and a second side opposite the first side;
a lead frame which is arranged at the edge of the substrate and is connected with the substrate in a welding mode;
a chip flip-chip mounted on the substrate;
the heat dissipation cover is attached to the first surface of the substrate, and the periphery of the heat dissipation cover is bonded to the first surface of the lead frame; and
solder balls disposed on the pads on the second side of the substrate and the second side of the lead frame.
In a preferred embodiment of the invention, the first and second surfaces of the substrate have pre-formed circuits and pads, the substrate has one or more layers of conductive tracks and conductive structures therein for making electrical and signal connections between the first and second surfaces, and the edge of the substrate has connection pads.
In a further preferred embodiment of the invention, it is provided that the leadframe comprises:
a pad;
a metal connection pin integral with the pad;
and the dielectric layer is bonded with the bonding pad and the metal connecting pin.
In a further preferred embodiment of the present invention, it is provided that the metal connection pins of the lead frame are fixed to the connection pads of the substrate by soldering, and the second surface of the lead frame is flush with the second surface of the substrate, the solder ball surface.
In a further preferred embodiment of the invention, it is provided that the dielectric layer is an insulating adhesive tape.
In a second aspect of the present invention, aiming at the problems existing in the prior art, the present invention provides a method for manufacturing a structure for expanding an I/O port of a ball grid array package, comprising:
manufacturing a lead frame, wherein the lead frame comprises a bonding pad; the metal connecting pins are integrally connected with the bonding pads; a dielectric layer bonded on the pad;
manufacturing a connecting bonding pad at the edge of the BGA welding spherical surface of the substrate;
welding the lead frame on a connecting bonding pad of the substrate through a metal connecting pin;
flip-chip mounting the chip on the substrate;
mounting a pre-designed heat dissipation cover on the substrate, and bonding the periphery of the heat dissipation cover on the lead frame;
and arranging the BGA solder balls on the lead frame and the BGA ball bonding pads of the substrate through a ball mounting process.
In a preferred embodiment of the present invention, the lead frame further includes a metal connecting rib integrally connected to the metal connecting pin and the pad.
In another preferred embodiment of the present invention, it is further provided that: the metal connecting ribs of the lead frame are cut off, then the metal connecting pins connected with the connecting bonding pads are bent, so that the lower surface of the bonding pad of the substrate is flush with the disc surface of the bonding pad of the lead frame to ensure the consistency of the subsequent ball-planting height, and the dielectric layer is reserved.
In a further preferred embodiment of the invention, provision is made for the leadframe to be produced by etching, stamping or electroplating.
In a further preferred embodiment of the invention, it is provided that the heat sink cover has a fixing effect on the bonding pads of the leadframe.
The invention has at least the following beneficial effects: the structure for expanding the ball grid array packaging I/O port and the manufacturing method thereof disclosed by the invention have the advantages that the process is simple, the cost is low, and the area of the packaging substrate is effectively saved under the condition that the total quantity of the I/O ports of the packaging chip is not changed by welding the connecting bonding pad at the edge of the substrate.
Drawings
To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, the same or corresponding parts will be denoted by the same or similar reference numerals for clarity.
Fig. 1 shows a structure for expanding I/O ports of a ball grid array package according to the present invention.
Fig. 2 shows the structure of a lead frame before attachment to a substrate according to the invention.
Fig. 3A to 3F are schematic diagrams illustrating a manufacturing process of expanding the structure of I/O port of ball grid array package according to the present invention.
Fig. 4 shows top, bottom and interface views of a FCBGA package of the prior art.
Detailed Description
It should be noted that the components in the figures may be exaggerated and not necessarily to scale for illustrative purposes.
In the present invention, the embodiments are only intended to illustrate the aspects of the present invention, and should not be construed as limiting.
In the present invention, the terms "a" and "an" do not exclude the presence of a plurality of elements, unless otherwise specified.
It is further noted herein that in embodiments of the present invention, only a portion of the components or assemblies may be shown for clarity and simplicity, but those of ordinary skill in the art will appreciate that, given the teachings of the present invention, required components or assemblies may be added as needed in a particular scenario.
It is also noted herein that, within the scope of the present invention, the terms "same", "equal", and the like do not mean that the two values are absolutely equal, but allow some reasonable error, that is, the terms also encompass "substantially the same", "substantially equal".
It should also be noted herein that in the description of the present invention, the terms "central", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In addition, the embodiments of the present invention describe the process steps in a specific order, however, this is only for convenience of distinguishing the steps, and does not limit the order of the steps.
Fig. 1 shows a structure for expanding I/O ports of a ball grid array package according to the present invention.
As shown in fig. 1, a structure 100 for expanding an I/O port of a ball grid array package includes a substrate 110, a lead frame 120, a chip 130, a heat dissipation cap 140, and solder balls 150.
The first side (upper surface) and the second side (lower surface or solder ball surface) of the substrate 110 have pre-formed circuits (not shown) and pads, and the substrate 110 has one or more layers of conductive traces and conductive structures pre-formed therein to form electrical and signal connections between the first and second sides. For example, the substrate 110 may be a package substrate produced according to specific requirements. There are connection pads at the edge of the substrate 110.
The lead frame 120 is disposed at an edge of the substrate 110 and connected to the connection pad of the substrate 110 by soldering. The material of the lead frame can be iron-nickel alloy, copper-iron alloy, copper-chromium-zirconium alloy and other alloy materials. The second (lower) surface of the lead frame 120 is flush with the second ball-side surface of the substrate 110. The specific structure of the lead frame 120, the connection manner of the lead frame 120 and the substrate 110 will be described in detail below with reference to fig. 2 and 3B.
The chip 130 is flip-chip mounted on the first side of the substrate 110. The chip 130 may be a logic chip such as a processor, an FPGA, and an MCU, or may be a memory chip such as an EPROM, a FLASH, and a DRAM.
The heat dissipation cover 140 is attached to the substrate 110, and the periphery of the heat dissipation cover 140 is fixed to the first surface (upper surface) of the lead frame 120.
The solder balls 150 are disposed on the pads of the second side of the substrate 110 and the second side of the lead frame 120.
Fig. 2 shows the structure of a lead frame before attachment to a substrate according to the invention.
As shown in fig. 2, the lead frame 220 includes a metal connection pin 221, a pad 222, and a metal connection rib 223. The metal connection pins 221, the pads 222, and the metal tie bars 223 are integrally connected. Dielectric layer 224 is bonded to bond pad 222 to ensure stability of bond pad 222.
The metal connection pins 221 are used to connect the lead frame 220 with the substrate. The pads 222 are used to arrange solder balls. In one embodiment of the present invention, the dielectric layer 223 may be an insulating tape.
Fig. 3A to 3F are schematic diagrams illustrating a manufacturing process of expanding the structure of I/O port of ball grid array package according to the present invention.
In step 1, a pad structure with edge connection is designed, and then the lead frame 320 is manufactured by etching, stamping or electroplating.
In step 2, as shown in fig. 3A, when the substrate 310 is processed, connection pads 311 are formed on the edge of the BGA ball surface of the substrate 310.
In step 3, as shown in fig. 3B, 4 lead frames 320 are soldered on the connection pads 311 of the substrate 310 through the metal connection pins 321.
In step 4, as shown in fig. 3C, the metal connecting rib 324 of the lead frame is cut off, and then the metal connecting pin 321 connected with the connecting pad 311 is bent, so that the lower surface of the pad 312 of the substrate 310 is flush with the surface of the pad 322 of the lead frame to ensure that the subsequent ball-planting height is consistent, and the dielectric layer is reserved.
At step 5, as shown in fig. 3D, the chip 330 is flip-chip mounted on the substrate 310.
In step 6, as shown in fig. 3E, a pre-designed heat dissipation cover 340 is attached to the substrate 310, and the periphery of the heat dissipation cover 340 is bonded to the lead frame 320, so as to fix the pad of the lead frame 320.
In step 7, as shown in fig. 3F, BGA solder balls 350 are arranged on the lead frame 320 and the pads of the substrate 310 through a ball-mounting process.
The invention has at least the following beneficial effects: the structure for expanding the ball grid array packaging I/O port and the manufacturing method thereof disclosed by the invention have the advantages that the process is simple, the cost is low, and the area of the packaging substrate is effectively saved under the condition that the total quantity of the I/O ports of the packaging chip is not changed by welding the connecting bonding pad at the edge of the substrate.
Although some embodiments of the present invention have been described herein, those skilled in the art will appreciate that they have been presented by way of example only. Numerous variations, substitutions and modifications will occur to those skilled in the art in light of the teachings of the present invention without departing from the scope thereof. It is intended that the following claims define the scope of the invention and that methods and structures within the scope of these claims and their equivalents be covered thereby.

Claims (10)

1. A structure for expanding I/O port of ball grid array package includes:
a substrate having a first side and a second side opposite the first side;
a lead frame which is arranged at the edge of the substrate and is connected with the substrate in a welding mode;
a chip flip-chip mounted on the substrate;
the heat dissipation cover is attached to the first surface of the substrate, and the periphery of the heat dissipation cover is bonded to the first surface of the lead frame; and
solder balls disposed on the pads on the second side of the substrate and the second side of the lead frame.
2. The structure for expanding I/O ports of a ball grid array package of claim 1, wherein the first and second sides of the substrate have pre-formed circuitry and pads, the substrate has one or more layers of conductive traces and conductive structures therein for making electrical and signal connections between the first and second sides, and the edge of the substrate has connection pads.
3. The structure for extending an I/O port of a ball grid array package of claim 1, wherein said lead frame comprises:
a pad;
a metal connection pin integral with the pad;
and the dielectric layer is bonded with the bonding pad and the metal connecting pin.
4. The structure for expanding I/O ports of a ball grid array package of claim 3, wherein said metal connection pins of said lead frame are fixed to said connection pads of said substrate by soldering, and said second side of said lead frame is flush with said second side of said substrate, said solder ball side of said lead frame being flush with said second side of said substrate.
5. The structure for expanding I/O ports of a ball grid array package of claim 3, wherein said dielectric layer is an insulating tape.
6. A manufacturing method for expanding a structure of a ball grid array packaging I/O port comprises the following steps:
manufacturing a lead frame, wherein the lead frame comprises a bonding pad; the metal connecting pins are integrally connected with the bonding pads; a dielectric layer bonded on the pad;
manufacturing a connecting bonding pad at the edge of the BGA welding spherical surface of the substrate;
welding the lead frame on a connecting bonding pad of the substrate through a metal connecting pin;
flip-chip mounting the chip on the substrate;
mounting a pre-designed heat dissipation cover on the substrate, and bonding the periphery of the heat dissipation cover on the lead frame;
and arranging the BGA solder balls on the lead frame and the BGA ball bonding pads of the substrate through a ball mounting process.
7. The method of claim 6, wherein the lead frame further comprises metal connecting ribs integrally connected to the metal connecting pins and the bonding pads.
8. The method of claim 7, further comprising: the metal connecting ribs of the lead frame are cut off, then the metal connecting pins connected with the connecting bonding pads are bent, so that the lower surface of the bonding pad of the substrate is flush with the disc surface of the bonding pad of the lead frame to ensure the consistency of the subsequent ball-planting height, and the dielectric layer is reserved.
9. The method of claim 6 wherein said lead frame is formed by etching, stamping or electroplating.
10. The method of claim 6, wherein the heat sink cap secures the bonding pads of the leadframe.
CN202111354586.8A 2021-11-16 2021-11-16 Structure for expanding ball grid array packaging I/O port and manufacturing method thereof Pending CN114068470A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111354586.8A CN114068470A (en) 2021-11-16 2021-11-16 Structure for expanding ball grid array packaging I/O port and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111354586.8A CN114068470A (en) 2021-11-16 2021-11-16 Structure for expanding ball grid array packaging I/O port and manufacturing method thereof

Publications (1)

Publication Number Publication Date
CN114068470A true CN114068470A (en) 2022-02-18

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111354586.8A Pending CN114068470A (en) 2021-11-16 2021-11-16 Structure for expanding ball grid array packaging I/O port and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN114068470A (en)

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