CN103579022B - 半导体封装件的结构及制法 - Google Patents

半导体封装件的结构及制法 Download PDF

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CN103579022B
CN103579022B CN201210298753.6A CN201210298753A CN103579022B CN 103579022 B CN103579022 B CN 103579022B CN 201210298753 A CN201210298753 A CN 201210298753A CN 103579022 B CN103579022 B CN 103579022B
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packing colloid
layer
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CN103579022A (zh
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许习彰
周信宏
刘鸿汶
廖信
廖信一
张江城
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Siliconware Precision Industries Co Ltd
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Abstract

一种半导体封装件的结构及制法，该制法包括将半导体组件接置于承载件上；再形成封装胶体于该承载件上；之后形成贯通该封装胶体的至少一穿孔；接着形成空心的导电通孔于该穿孔中，且同时形成线路层于该半导体组件的主动面与该封装胶体上；再形成第一绝缘保护层于该线路层上；最后移除该承载件。借由一次性地形成导电通孔与线路层，省略传统半导体封装件中的重布线路工艺以及化学机械研磨工艺，能大幅提升封装件的生产效率。

Description

半导体封装件的结构及制法
技术领域
本发明涉及一种半导体封装件及其制法，特别是关于一种可应用于立体封装的晶圆级半导体封装件及其制法。
背景技术
晶圆级封装(Wafer Level Packaging,WLP)为一种半导体封装方式，其于整片晶圆生产完成后，直接在晶圆上进行封装测试，完成之后才切割制成单颗尺寸与半导体芯片相仿的WLP封装件，不须经过打线或填胶，具有较小的封装尺寸与良好的电性表现，更可符合现今电子组件的微小化(miniaturization)的需求。
传统的WLP封装件多采用扇入(Fan in)型态，但伴随着半导体组件信号输入/输出的接脚数目增加，对球距要求趋于严格，加上部分组件对于封装后尺寸以及信号输出脚位元位置的调整需求，因此变化衍生出扇出(Fan out)，或是扇入及扇出相互运用等各式新型WLP封装型态，此外，为了因应半导体组件的电路密度持续增加，且封装体积逐渐缩小的趋势，更借由结合导电硅穿孔(Through Silicon Via,TSV)或导电通孔(Pin Through Hole,PTH)的设计，以完成积集度更高的立体晶圆级封装结构(3D WLP)。
如图1A所示，现有半导体封装件1的制法中，先于包含有半导体组件10的封装胶体12中形成穿孔120。
再如图1B所示，于穿孔120中电镀形成导电通孔15。
然后如图1C所示，依序形成介电层16、线路层17以及绝缘保护层18。
然而，在形成导电通孔时，上下表面会有过载(overburden)的情况发生，同时在半导体组件所外露的电性接触垫上也会形成有金属，因此必须以化学机械研磨(ChemicalMechanical Polishing,CMP)将突出的金属磨平，并移除电性接触垫上的金属层，以避免电性接触垫之间短路，此种利用CMP工艺的半导体封装件的制法成本较高。再者，后续工艺还需要形成介电层之后才能形成线路层，也提高制作成本。
因此，如何克服上述现有技术的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的缺陷，本发明的主要目的在于提供一种半导体封装件的结构及制法，可省略传统半导体封装件中的重布线路工艺以及化学机械研磨工艺，能大幅提升封装件的生产效率。
本发明的半导体封装件的制法包括：将具有主动面与非主动面的半导体组件以该非主动面接置于承载件上；形成封装胶体于该承载件上，以包覆该半导体组件的侧面，其中，该封装胶体具有第一表面与相对的第二表面；形成贯通该封装胶体的至少一穿孔；形成空心的导电通孔于该穿孔中，且同时形成线路层于该外露的半导体组件的主动面与该封装胶体的第一表面上；形成第一绝缘保护层于该线路层上，且该第一绝缘保护层填入该空心的导电通孔内；以及移除该承载件。
前述的半导体封装件的制法中，该封装胶体的第一表面可与该半导体组件的主动面齐平。
前述的半导体封装件的制法中，于形成贯通该封装胶体的至少一穿孔后，还包括形成图案化阻层于该半导体组件的主动面与该封装胶体的第一表面上，并外露出部分该半导体组件的主动面与该封装胶体的第一表面，再于形成空心的导电通孔于该穿孔中及形成线路层于该外露的半导体组件的主动面与该封装胶体的第一表面上之后，移除该图案化阻层。
前述的半导体封装件的制法中，于形成贯通该封装胶体的至少一穿孔后，还包括于形成图案化阻层之前，先于该半导体组件的主动面与该封装胶体的第一表面上及该穿孔中形成晶种层，且形成该晶种层与该线路层的材料可为铜。
前述的半导体封装件的制法中，形成该穿孔的方式可为激光钻孔，且该第一绝缘保护层可为干膜，再以压合的方式将该干膜压入该空心的导电通孔内。
前述的半导体封装件的制法中，于形成该第一绝缘保护层于该线路层上之后，在移除该承载件之前，还包括于该第一绝缘保护层上形成多个第一开孔，以外露部分的该线路层，之后，于该开孔中形成导电组件，其中，该导电组件可为焊锡凸块或铜柱。
前述的半导体封装件的制法中，于该第一绝缘保护层上形成该多个第一开孔之后，还包括于该封装胶体的第二表面上形成线路重布层；以及于该线路重布层上形成具有多个第二开孔的第二绝缘保护层。
本发明还提供一种半导体封装件结构，其包括：半导体组件，其具有相对的主动面与非主动面；封装胶体，其包覆该半导体组件的侧面，且该封装胶体具有第一表面与相对的第二表面；至少一穿孔，其形成于该封装胶体中且贯通该封装胶体；空心的导电通孔，其形成于该穿孔中；线路层，其形成于该半导体组件的主动面与该封装胶体的第一表面上，且该线路层电性连接该空心的导电通孔；以及第一绝缘保护层，其形成于该线路层上，且该第一绝缘保护层填入该空心的导电通孔内。
前述的半导体封装件结构中，该封装胶体的第一表面可与该半导体组件的主动面齐平，且该封装胶体的第二表面可与该半导体组件的非主动面齐平。
前述的半导体封装件结构中，还包括形成于该线路层与封装胶体之间、线路层与半导体组件之间及空心的导电通孔与封装胶体之间的晶种层。
前述的半导体封装件结构中，该第一绝缘保护层可为干膜，且该第一绝缘保护层具有外露部分该线路层的多个第一开孔，又该半导体封装件还包括导电组件，可形成于该第一开孔中，以电性连接该线路层。
前述的半导体封装件结构中，还可包括线路重布层，其形成于该封装胶体的第二表面上；以及具有多个第二开孔的第二绝缘层，其形成于该线路重布层上。
由上可知，本发明的半导体封装件结构及其制法，其借由先于封装胶体中形成穿孔，再一次性的形成导电通孔与线路层，省略传统半导体封装件中先形成绝缘保护层的重布线路工艺以及CMP工艺，故相比于现有技术，本发明的半导体封装件的制法能有效节省工艺步骤，以大幅提升封装件的生产效率。
附图说明
图1A至图1C为现有半导体封装件的制法的剖面示意图；以及
图2A至图2I’为本发明的半导体封装件的制法的剖面示意图；其中，图2A至图2H为第一实施例，图2H’至图2I’为另一实施例。
主要组件符号说明
1,2,2’ 半导体封装件
10,20 半导体组件
12,22 封装胶体
120,220 穿孔
15 导电通孔
16 介电层
17 线路层
18 绝缘保护层
20a 主动面
20b 非主动面
201 电性接触垫
21 承载件
21’ 第二承载件
22a 第一表面
22b 第二表面
23 晶种层
24 图案化阻层
25 空心的导电通孔
26 线路层
27 第一绝缘保护层
270 第一开孔
27’ 第二绝缘保护层
270’ 第二开孔
28 导电组件
29 线路重布层
290 介电层
291 导电盲孔
292 第二线路层。
具体实施方式
以下借由特定的具体实施例说明本发明的实施方式，熟知本领域技术的人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供熟知本领域技术的人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“下”及“一”等用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
请参阅图2A至图2H，其为本发明的半导体封装件2的制法的剖面示意图。
如图2A所示，将具有主动面20a与非主动面20b的半导体组件20以该非主动面20b接置于承载件21上，其中，该主动面上可具有电性接触垫201。
于本实施例中，该半导体组件20为半导体芯片，且该承载件21的材质为玻璃纤维板（FR4）、玻璃或金属。
如图2B所示，形成封装胶体22于该承载件21上，以包覆该半导体组件20的侧面，其中，该封装胶体22具有与该半导体组件20的主动面20a齐平的第一表面22a与相对的第二表面22b。
于本实施例中，该封装胶体22可为环氧树脂，其可利用压合（lamination）或模压（molding）方式形成。又有关该封装胶体22的材料并不限于上述。
如图2C所示，形成贯通该封装胶体22的至少一穿孔220。
于本实施例中，形成该穿孔220的方法可为激光钻孔。
如图2D所示，于该半导体组件20的主动面20a与该封装胶体22的第一表面22a上及该穿孔220中形成晶种层23。
于本实施例中，形成该晶种层23的材料可为铜，该晶种层23作为后续电镀工艺时的电流路径。
如图2E所示，形成图案化阻层24于该半导体组件20的主动面20a与该封装胶体22的第一表面22a上，并外露出部分该半导体组件的主动面与该封装胶体的第一表面。
如图2F所示，电镀形成空心的导电通孔25于该穿孔220中，且同时形成线路层26于该外露的半导体组件20的主动面20a与该封装胶体22的第一表面22a上。
于本实施例中，形成该线路层的材料可为铜。
如图2G所示，移除该图案化阻层24，再形成第一绝缘保护层27于该线路层26上，接着于该第一绝缘保护层27上形成多个第一开孔270，以外露部分的该线路层26。
于本实施例中，该第一绝缘保护层27可为干膜，并以压合的方式将该干膜压入该该空心的导电通孔25内。
如图2H所示，于该第一开孔270中形成导电组件28，从而使该半导体封装件2能借由该些导电组件28接置于如电路板的电子装置上，再移除该承载件21。
于本实施例中，该导电组件28可为焊锡凸块或铜柱。
于另一实施例中，如图2H’所示的半导体封装件2’，于形成第一绝缘保护层27于该线路层26上，且于该第一绝缘保护层27上形成该多个第一开孔270之后，先于该第一绝缘保护层27上接置第二承载件21’，再移除承载件21。
接着，于该封装胶体22的第二表面22b上形成线路重布层29，其中，该线路重布层29由介电层290、导电盲孔291与第二线路层292所组成，再于该线路重布层29上形成具有多个第二开孔270’的第二绝缘保护层27’，以外露出部份的该第二线路层292。
如图2I’所示，移除该第二承载件21’，再于该第一开孔270中形成导电组件28，以使半导体封装件2’能借由该些导电组件28相互堆栈以形成立体封装结构或接置于如电路板的电子装置上。
本发明提供一种半导体封装件2,2’，其包括：半导体组件20，其具有相对的主动面20a与非主动面20b，其中，该主动面上具有电性接触垫201；封装胶体22，其包覆该半导体组件20的侧面，且该封装胶体22具有与该半导体组件20的主动面20a齐平的第一表面22a以及与该半导体组件20的非主动面22b齐平的第二表面22b；至少一穿孔220，其形成于该封装胶体22中且贯通该封装胶体22；空心的导电通孔25，其形成于该穿孔220中；线路层26，其形成于该半导体组件20的主动面20a与该封装胶体22的第一表面22a上，且该线路层26电性连接该空心的导电通孔25；以及第一绝缘保护层27，其形成于该线路层26上，且该第一绝缘保护层27填入该空心的导电通孔25内。
所述的半导体封装件2,2’，还包括晶种层23，其形成于该线路层26与封装胶体22之间、线路层26与半导体组件20之间及空心的导电通孔25与封装胶体22之间。
于本实施例中，该第一绝缘保护层27可为干膜，且该第一绝缘保护层27具有外露部分该线路层26的多个第一开孔270，且该半导体封装件2,2’还包括导电组件28，其形成于该第一开孔270中，以电性连接该线路层26。
所述的半导体封装件2’，还包括由介电层290、导电盲孔291与第二线路层292所组成的线路重布层29，其形成于该封装胶体22的第二表面22b上；以及具有多个第二开孔270’的第二绝缘层27’，其形成于该线路重布层29上，以外露出部份的该第二线路层292，以使该半导体封装件2’可借由该导电组件28电性连接外露的该线路层26与该第二线路层292，以形成3D立体封装件(如图2I’所示)。
综上所述，本发明的半导体封装件及其制法，主要借由先于封装胶体中形成穿孔，然后一次性地形成导电通孔与线路层，省略传统半导体封装件中先形成绝缘保护层的重布线路工艺，此外，本发明能避免形成过载，因此可省略CMP工艺，故能有效节省工艺步骤，以大幅提升能应用于立体封装的晶圆级封装件的生产效率及节省成本。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟知本领域技术的人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (17)

1.一种半导体封装件的制法，其包括：
将具有主动面与非主动面的半导体组件以该非主动面接置于承载件上；
形成封装胶体于该承载件上，以包覆该半导体组件的侧面，其中，该封装胶体具有第一表面与相对的第二表面，该封装胶体的第一表面与该半导体组件的主动面齐平，且该封装胶体的第二表面与该半导体组件的非主动面齐平；
形成仅贯通该封装胶体的至少一穿孔；
形成空心的导电通孔于该穿孔中，且同时形成线路层于该半导体组件的主动面与该封装胶体的第一表面上；
形成第一绝缘保护层于该线路层上，且该第一绝缘保护层填入该空心的导电通孔内；以及
形成第一绝缘保护层于该线路层上后，移除该承载件。
2.根据权利要求1所述的半导体封装件的制法，其特征在于，于形成贯通该封装胶体的至少一穿孔后，还包括形成图案化阻层于该半导体组件的主动面与该封装胶体的第一表面上，并外露出部分该半导体组件的主动面与该封装胶体的第一表面，再于形成空心的导电通孔于该穿孔中及形成线路层于该外露的半导体组件的主动面与该封装胶体的第一表面上之后，移除该图案化阻层。
3.根据权利要求2所述的半导体封装件的制法，其特征在于，于形成贯通该封装胶体的至少一穿孔后，还包括于形成图案化阻层之前，先于该半导体组件的主动面与该封装胶体的第一表面上及该穿孔中形成晶种层。
4.根据权利要求3所述的半导体封装件的制法，其特征在于，形成该晶种层的材料为铜。
5.根据权利要求1所述的半导体封装件的制法，其特征在于，形成该穿孔的方式为激光钻孔。
6.根据权利要求1所述的半导体封装件的制法，其特征在于，形成该线路层的材料为铜。
7.根据权利要求1所述的半导体封装件的制法，其特征在于，该第一绝缘保护层为干膜。
8.根据权利要求7所述的半导体封装件的制法，其特征在于，是以压合的方式将该干膜压入该空心的导电通孔内。
9.根据权利要求1所述的半导体封装件的制法，其特征在于，于形成该第一绝缘保护层于该线路层上之后，在移除该承载件之前，还包括于该绝缘保护层上形成多个第一开孔，以外露部分的该线路层。
10.根据权利要求9所述的半导体封装件的制法，其特征在于，于该绝缘保护层上形成该多个第一开孔之后，还包括于该第一开孔中形成导电组件。
11.根据权利要求10所述的半导体封装件的制法，其特征在于，该导电组件为焊锡凸块或铜柱。
12.根据权利要求9所述的半导体封装件的制法，其特征在于，于该绝缘保护层上形成多个第一开孔之后，还包括：
于该封装胶体的第二表面上形成线路重布层；以及
于该线路重布层上形成具有多个第二开孔的第二绝缘保护层。
13.一种半导体封装件结构，其包括：
半导体组件，其具有相对的主动面与非主动面；
封装胶体，其包覆该半导体组件的侧面，且该封装胶体具有第一表面以及相对的第二表面，该封装胶体的第一表面与该半导体组件的主动面齐平，且该封装胶体的第二表面与该半导体组件的非主动面齐平；
至少一穿孔，其仅形成于该封装胶体中且贯通该封装胶体；
空心的导电通孔，其形成于该穿孔中；
线路层，其形成于该半导体组件的主动面与该封装胶体的第一表面上，且该线路层电性连接该空心的导电通孔；以及
第一绝缘保护层，其形成于该线路层上，且该第一绝缘保护层填入该空心的导电通孔内。
14.根据权利要求13所述的半导体封装件结构，其特征在于，该结构还包括晶种层，其形成于该线路层与封装胶体之间、线路层与半导体组件之间及空心的导电通孔与封装胶体之间。
15.根据权利要求13所述的半导体封装件结构，其特征在于，该第一绝缘保护层为干膜。
16.根据权利要求13所述的半导体封装件结构，其特征在于，该第一绝缘保护层具有外露部分该线路层的多个第一开孔，且该半导体封装件还包括导电组件，其形成于该第一开孔中，以电性连接该线路层。
17.根据权利要求13所述的半导体封装件结构，其特征在于，该结构还包括线路重布层，其形成于该封装胶体的第二表面上；以及具有多个第二开孔的第二绝缘层，其形成于该线路重布层上。
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