CN102386180A - 半导体集成电路 - Google Patents

半导体集成电路 Download PDF

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CN102386180A
CN102386180A CN2011100832841A CN201110083284A CN102386180A CN 102386180 A CN102386180 A CN 102386180A CN 2011100832841 A CN2011100832841 A CN 2011100832841A CN 201110083284 A CN201110083284 A CN 201110083284A CN 102386180 A CN102386180 A CN 102386180A
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朴炳权
李锺天
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SK Hynix Inc
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Abstract

本发明公开了一种半导体集成电路，包括：半导体芯片，所述半导体芯片包括存储器单元阵列；多个第一穿通芯片通孔，所述多个第一穿通芯片通孔被配置为垂直地贯穿所述半导体芯片且作为信号和电源电压的接口而操作；以及半导体衬底。半导体衬底包括：外围电路区域，所述外围电路区域与所述多个第一穿通芯片通孔相耦接且被配置为控制所述半导体芯片；以及导电图案区域，所述导电图案区域被配置为在所述外围电路区域与外部控制器之间作为信号和电源电压的接口而操作。

Description

半导体集成电路
相关申请的交叉引用
本申请要求2010年8月27日提交的韩国专利申请No.10-2010-0083498的优先权，其全部内容以引用的方式并入在本文中。
技术领域
本发明的示例性实施例涉及半导体设计技术，且更具体而言涉及具有三维(3D)层叠封装的半导体集成电路(IC)。
背景技术
半导体集成电路(IC)的封装技术已在使半导体IC小型化和获得安装可靠性方面取得进步。例如，尽管使电气/电子器件小型化，但为了能获得足够的性能，已开发出层叠封装。由于需要电气/电子产品的小型化和高性能，本领域已经公开了各种层叠封装的技术。
术语“层叠”在半导体工业中指的是两个或更多的芯片或封装体的垂直层叠的堆积体。通过使用层叠封装，例如在存储器件的情况下，存储器件的存储容量可以是传统的半导体集成工艺所能获得的存储器件的存储容量的两倍或更多倍。此外，层叠封装不仅使存储容量增加，而且使安装密度和安装面积利用效率提高。
可以通过将个体半导体芯片层叠且然后以一个步骤将层叠的半导体芯片封装的方法或者通过将预先封装的个体半导体芯片层叠起来的方法来制造层叠封装。层叠封装的个体半导体芯片可以经由金属线或穿通芯片通孔(through chip via)来彼此电耦接。这里，使用穿通芯片通孔的层叠封装具有这样的结构：穿通芯片通孔被形成在半导体芯片内，且所述半导体芯片经由穿通芯片通孔垂直地彼此物理耦接和电耦接。此处，穿通芯片通孔可以是穿通硅通孔(through silicon via，TSV)。
图1图示的是现有的层叠封装的半导体芯片。
参见图1，通过在半导体芯片A中形成通孔(via)并用导电率大的金属例如铜(Cu)填充所述通孔来形成穿通芯片通孔B，以形成用于层叠封装的半导体芯片C。通过层叠多个半导体芯片C并将层叠的所述多个半导体芯片C安装在印刷电路板(PCB)上来制造半导体集成电路(IC)。所制造的半导体集成电路(IC)可以被称为三维(3D)层叠封装半导体集成电路(IC)。
图2是说明三维(3D)层叠封装半导体集成电路(IC)的截面图。
在本说明书中，以包括一个主芯片和四个从芯片的半导体集成电路(IC)为例来描述三维(3D)层叠封装半导体集成电路(IC)。
参见图2，示出了现有的三维(3D)层叠封装半导体集成电路(IC)100。半导体集成电路(IC)100包括：与外部控制器300相耦接的封装衬底110；层叠在封装衬底110的上侧面之上的主芯片120；垂直穿透主芯片120的第二穿通芯片通孔130；垂直层叠在主芯片120的上侧面上的第一至第四从芯片140a、140b、140c和140d；以及垂直穿透第一至第四从芯片140a、140b、140c和140d的多个第一穿通芯片通孔150a、150b、150c和150d。
封装衬底110使主芯片120与外部控制器300电耦接。与第二穿通芯片通孔130相耦接的金属线被形成在封装衬底110的上侧面上。与外部控制器300相耦接的焊料球112被形成在封装衬底110的底部上。金属线与焊料球112经由相应的线路彼此耦接。
封装衬底110经由焊料球112与外部控制器300连接以将各种信号和电源电压传送给主芯片120。另一方面，封装衬底110经由焊料球112将来自主芯片120的各种信号和电源电压传送给外部控制器300。这里，封装衬底110可以是由聚合物制成的印刷电路板(PCB)。
响应于从外部控制器300经由封装衬底110所施加的信号和电源电压，主芯片120经由多个第一穿通芯片通孔150a、150b、150c和150d控制第一至第四从芯片140a、140b、140c和140d。主芯片120包括用于控制第一至第四从芯片140a、140b、140c和140d的外围电路区域(未图示)。
此处，主芯片120的外围电路区域包括用于输入/输出各种信号的输入/输出缓冲器、用于输入/输出数据的数据输入/输出电路、以及用于输入/输出地址和命令的状态机，而不包括用于储存数据的存储器单元阵列区域。
第一至第四从芯片140a、140b、140c和140d包括上述存储器单元阵列区域，所述存储器单元阵列区域用于响应于主芯片120的控制来储存数据或提供所储存的数据。存储器单元阵列区域包括存储器单元阵列和用于储存数据或提供所储存的数据的最小电路。
第二穿通芯片通孔130和所述多个第一穿通芯片通孔150a、150b、150c和150d是用于信号和电源电压的接口的穿通硅通孔(TSV)。
现有的半导体集成电路(IC)100具有以下特征。
当与一次性地或顺序地将第一至第四从芯片140a、140b、140c和140d层叠在主芯片120上的步骤分开地执行将主芯片120层叠在衬底120上的步骤时，生产成本可能增加。
另外，由于主芯片120中所包括的外围电路区域被设置在未形成焊料球112和金属线的区域中，因此主芯片120可能面临信号完整性(SI)恶化的问题。
此外，封装衬底110、主芯片120以及第一至第四从芯片140a、140b、140c和140d可能各自需要独立的设备来制造。归因于在改变芯片布置和印刷电路板设计时对设备的重新设置，生产成本和时间可能增加。
发明内容
本发明的实施例涉及一种半导体集成电路(IC)，所述IC用于使穿通芯片通孔的数量最小化以在信号完整性(SI)方面作出改善并减少生产成本和生产时间。
根据本发明的一个实施例，一种半导体集成电路(IC)包括：半导体芯片，所述半导体芯片包括存储器单元阵列；多个第一穿通芯片通孔，所述多个第一穿通芯片通孔被配置为垂直地贯穿所述半导体芯片并且作为信号和电源电压的接口而操作；以及半导体衬底，所述半导体衬底包括外围电路区域和导电图案区域，所述外围电路区域与所述多个第一穿通芯片通孔相耦接并被配置为控制所述半导体芯片，所述导电图案区域被配置为在所述外围电路区域与外部控制器之间作为所述信号和所述电源电压的接口而操作。
根据本发明的另一个实施例，一种制造半导体集成电路(IC)的方法包括以下步骤：在半导体衬底上层叠半导体芯片，所述半导体芯片包括存储器单元阵列；以及形成外围电路区域和导电图案区域，所述外围电路区域被布置为与多个第一穿通芯片通孔相耦接，所述导电图案区域被配置为在外围电路区域与外部控制器之间作为信号和电源电压的接口而操作，其中所述第一穿通芯片通孔被耦接在所述半导体芯片与所述外围电路区域之间，且所述外围电路区域和所述导电图案区域的部分是同时形成的。
附图说明
图1图示的是现有的层叠封装的半导体芯片；
图2是说明现有的具有三维(3D)层叠封装的半导体集成电路(IC)的截面图；
图3是说明根据本发明的一个实施例的具有三维(3D)层叠封装的半导体集成电路(IC)的截面图；以及
图4是说明图3的封装衬底的俯视图。
具体实施方式
下面将参照附图更加详细地描述本发明的示例性实施例。然而，本发明可以用不同的方式来实施，并且不应当被解释为限于本文所提出的实施例。确切地说，提供这些实施例是为了使得本说明书将是清楚且完整的，且将会向本领域技术人员充分传达本发明的范围。在本说明书中，在本发明的各个附图和实施例中相同的附图标记表示相同的部分。
在本说明书中，以包括半导体衬底和四个穿通芯片通孔的封装为例来描述本发明。
图3是说明根据本发明的一个实施例的具有三维(3D)层叠封装的半导体集成电路(IC)的截面图。
图3中示出了半导体芯片和穿通芯片通孔的截面图，其中每个芯片或通孔与图2中的相应元件实质上相同。
参见图3，半导体集成电路(IC)200包括：用于与外部控制器300进行各种信号和电源电压的接口的半导体衬底210；垂直地层叠在半导体衬底210的上侧面之上的第一至第四半导体芯片220A、220B、220C和220D；以及垂直地穿透进第一至第四半导体芯片220A、220B、220C和220D中的第一穿通芯片通孔230A、230B、230C及230D。第一穿通芯片通孔包括穿通硅通孔(TSV)。
半导体衬底210包括形成在半导体衬底210的上侧面上的外围电路区域212和导电图案区域214。半导体衬底210包括形成在半导体衬底210的底侧面上的外部连接端子216。外部连接端子216包括焊料球。
半导体衬底210包括多个第二穿通芯片通孔240，所述多个第二穿通芯片通孔240垂直地贯穿半导体衬底210且将导电图案区域214与外部连接端子216电耦接。所述多个第二穿通芯片通孔240包括穿通硅通孔(TSV)。
图4是说明图3中的半导体衬底的俯视图。
参见图3和图4，外围电路区域212被耦接至多个第一穿通芯片通孔230A、230B、230C和230D，且经由所述多个第一穿通芯片通孔230A、230B、230C和230D来控制第一至第四半导体芯片220A、220B、220C和220D。
虽然图中未示出，但外围电路区域212包括各种输入/输出缓冲器、用于输入/输出数据的数据输入/输出电路和用于输入/输出地址和命令的状态机。导电图案区域214包括多个金属线，所述多个金属线用于将外围电路区域212电耦接至第二穿通芯片通孔240。所述多个金属线的每个可以是导电率大的金属，诸如铜(Cu)。
半导体衬底210可以是用于将外围电路区域212与导电图案区域214集成在衬底中的硅衬底。
同时，如同导电图案区域214一样，第二穿通芯片通孔240可以是导电率大的金属诸如，铜(Cu)。多个第二穿通芯片通孔240可以是穿通硅通孔(TSV)。
虽然图中未示出，但第一至第四半导体芯片220A、220B、220C和220D包括存储器单元阵列区域，响应于外围电路区域212的输出在所述存储器单元阵列区域中储存数据和将数据提供给存储器单元阵列区域。存储器单元阵列区域可以包括用于储存和提供数据的最小电路，例如，用于对地址进行译码的译码器和存储器单元阵列。
多个第一穿通芯片通孔230A、230B、230C和230D在外围电路区域212与第一至第四半导体芯片220A、220B、220C和220D之间作为信号和电源电压的接口。
多个第一穿通芯片通孔230A、230B、230C和230D的每个由诸如硅通孔TSV和铜(Cu)的导电率大的金属形成。
虽然图中未示出，但是多个第一穿通芯片通孔230A、230B、230C和230D的每个经由凸块焊盘(bump pad)来耦接至半导体芯片220A、220B和220C中的相应的一个半导体芯片和半导体衬底210。
根据本发明的实施例，半导体集成电路(IC)200包括用于控制第一至第四半导体芯片220A、220B、220C和220D的外围电路区域212，且包括用于将外围电路区域212与外部控制器300电耦接的导电图案区域214，其中外围电路区域212和导电图案区域214形成在单个衬底210上。以此方式，在执行层叠封装工艺时，归因于层叠工艺的数量的减少，生产成本和生产时间减少。此处，由于不将主从芯片层叠在半导体衬底110上，因此使用一步层叠工艺来简化制造过程和减少成本，其中将半导体芯片一步层叠在半导体衬底210上。
由于外围电路区域210和导电图案区域214被设置在半导体衬底210中，因此可视情况而定来确定它们的配置。因此，由于外围电路区域210和导电图案区域214既不彼此分开也不是被安置在各自的有限空间内，因此通过适当地设置外围电路区域210和导电图案区域214，可以获得适当的信号完整性(SI)以减小线路负载。
当一起执行外围电路区域210的制造和导电图案区域214的制造时，同时执行针对两个区域所执行的相同工艺例如金属线的制造工艺，以通过减少制造工艺的数量来减少生产成本和生产时间。
根据本发明的一个示例性实施例，通过使用共同的穿通芯片通孔来传送信号，可以减小用于传送根据操作模式而在不同的时刻被使能的信号的穿通芯片通孔的数量。因此，可以减小半导体集成电路(IC)的总面积，且可以增加净裸片。
虽然已经参照具体的实施例描述了本发明，但对于本领域技术人员而言明显的是，在不脱离所附权利要求所限定的本发明的精神和范围的情况下，可以进行各种变化和修改。
虽然已经说明了硅衬底，但本发明并不限于此，而是可以适用于其它情况，包括用于在同一衬底上形成外围电路区域和导电图案区域的任何合理适合的衬底。
根据本发明的示例性实施例，半导体集成电路(IC)具有第一穿通芯片通孔和第二穿通芯片通孔。然而，半导体集成电路(IC)可以包括更多的穿通芯片通孔(例如，数百或数千个)。

Claims (14)

1.一种半导体集成电路，包括：
半导体芯片，所述半导体芯片包括存储器单元阵列；
多个第一穿通芯片通孔，所述多个第一穿通芯片通孔被配置为垂直地贯穿所述半导体芯片且作为信号和电源电压的接口而操作；以及
半导体衬底，所述半导体衬底包括外围电路区域和导电图案区域，所述外围电路区域与所述多个第一穿通芯片通孔相耦接并被配置为控制所述半导体芯片，所述导电图案区域被配置为在所述外围电路区域与外部控制器之间作为所述信号和所述电源电压的接口而操作。
2.如权利要求1所述的半导体集成电路，还包括多个外部连接端子，所述多个外部连接端子被配置为与所述外部控制器电耦接。
3.如权利要求2所述的半导体集成电路，其中，所述外围电路区域和所述导电图案区域被形成在所述半导体衬底的第一侧面上，所述多个外部连接端子被形成在所述半导体衬底的相对置的侧面上。
4.如权利要求3所述的半导体集成电路，其中，所述多个外部连接端子被形成在所述半导体衬底的一个侧面上。
5.如权利要求4所述的半导体集成电路，还包括多个第二穿通芯片通孔，所述多个第二穿通芯片通孔使所述导电图案区域与所述多个外部连接端子相耦接。
6.如权利要求5所述的半导体集成电路，其中，所述多个第一穿通芯片通孔和所述多个第二穿通芯片通孔各自包括穿通硅通孔，即TSV。
7.如权利要求1所述的半导体集成电路，其中，所述半导体衬底是硅衬底。
8.如权利要求1所述的半导体集成电路，其中，所述导电图案区域包括金属线。
9.如权利要求1所述的半导体集成电路，还包括：
至少一个凸块焊盘，所述至少一凸块焊盘被配置为将所述多个第一穿通芯片通孔中的相应的一个电连接至所述外围电路区域。
10.如权利要求2所述的半导体集成电路，其中，所述多个外部连接端子包括焊料球。
11.如权利要求1所述的半导体集成电路，其中，所述导电图案区域包括导电图案，所述导电图案被形成在所述半导体衬底的一个侧面上且将所述外围电路区域连接至贯穿所述半导体衬底的多个第二穿通芯片通孔。
12.如权利要求11所述的半导体集成电路，其中，所述第二穿通芯片通孔被设置在所述外围电路区域的相对置的侧面上。
13.一种方法，包括：
在半导体衬底上层叠半导体芯片，所述半导体芯片包括存储器单元阵列；以及
形成外围电路区域和导电图案区域，所述外围电路区域被布置为与多个第一穿通芯片通孔相耦接，所述导电图案区域被配置为在所述外围电路区域与外部控制器之间作为信号和电源电压的接口而操作，其中所述第一穿通芯片通孔被耦接在所述半导体芯片与所述外围电路区域之间，且所述导电图案区域和所述外围电路区域的部分是同时形成的。
14.如权利要求13所述的方法，还包括以下步骤：形成贯穿所述半导体衬底的多个第二穿通芯片通孔，其中，所述导电图案区域包括导电图案，所述导电图案被形成在所述半导体衬底的一个侧面上且将所述外围电路区域与所述多个第二穿通芯片通孔连接。
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