CN102222651A - 在用于接合管芯的中介层中的具有不同尺寸的tsv - Google Patents

在用于接合管芯的中介层中的具有不同尺寸的tsv Download PDF

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Publication number
CN102222651A
CN102222651A CN2010102625644A CN201010262564A CN102222651A CN 102222651 A CN102222651 A CN 102222651A CN 2010102625644 A CN2010102625644 A CN 2010102625644A CN 201010262564 A CN201010262564 A CN 201010262564A CN 102222651 A CN102222651 A CN 102222651A
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China
Prior art keywords
tsv
substrate
tube core
silicon substrate
horizontal size
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CN2010102625644A
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English (en)
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蔡柏豪
林俊成
余振华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority to CN201610182673.2A priority Critical patent/CN105845636B/zh
Publication of CN102222651A publication Critical patent/CN102222651A/zh
Pending legal-status Critical Current

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Abstract

一种器件包括中介层，中介层包括具有顶面和底面的衬底。多个衬底通孔(TSV)穿过衬底。多个TSV包括具有第一长度和第一水平尺寸的第一TSV，以及具有不同于第一长度的第二长度和不同于第一水平尺寸的第二水平尺寸的第二TSV。互连结构被形成为置于衬底的顶面，并且电连接到所述多个TSV。本发明还提供了一种在用于接合管芯的中介层中的具有不同尺寸的TSV。

Description

在用于接合管芯的中介层中的具有不同尺寸的TSV
技术领域
本发明总体涉及集成电路，尤其涉及包括中介层的三维集成电路(3DIC)及其形成方法。
背景技术
自从集成电路的发明以来，由于在多种电子部件(即，晶体管、二极管、电阻器、电容器等)的集成密度方面的不断改进，半导体工业经历了连续的快速成长。主要地，集成密度方面的这些改进来源于最小部件尺寸的反复减小，使得更多组件被集成到给定芯片区域中。
这些集成改进基本上在本质上是二维(2D)的，因为由集成部件占据的体积基本在半导体晶片的表面上。虽然光刻方面的巨大改进已经导致了2D集成电路形成方面的相当大的改进，但是仍然存在对二维中能够实现的密度的物理限制。这些限制之一为制造这些组件所需要的最小尺寸。而且，当更多器件被放入一个芯片时，要求更复杂的设计。随着器件数量的增加，附加限制源于器件之间的互连件的数量和长度方面的显著增加。当互连件的数量和长度增加时，电路RC延迟和功率消耗都会增加。
由此，形成了三维集成电路(3DIC)，其中，可以堆叠两个管芯，管芯其中一个具有形成在其上的硅通孔(TSV)，以将另外一个管芯连接至封装衬底。通常在前道工序(FEOL)步骤之后，在器件管芯中形成TSV，在其中形成诸如晶体管的器件，也可能在后道工序(BEOL)步骤之后，在器件管芯中形成TSV，在其中形成有互连结构。TSV的形成可能导致已经形成的管芯的产量损失。而且，由于在形成集成电路之后，在器件管芯中形成TSV，因此还延长了用于制造的周期。
发明内容
根据一个方面，器件包括中介层，中介层包括具有顶面和底面的衬底。多个衬底通孔(TSV)穿过衬底。多个TSV包括具有第一长度和第一水平尺寸的第一TSV，以及具有不同于第一长度的第二长度和不同于第一水平尺寸的第二水平尺寸的第二TSV。互连结构形成为叠加在衬底的顶面之上并且电连接至多个TSV。
还披露了其他实施例。
附图说明
为了更好地理解实施例及其优点，现在将结合附图所进行的以下描述作为参考，其中：
图1A至图1K是根据多个实施例的制造三维集成电路(3DIC)的中间阶段的截面图，其中，管芯之一位于中介层的衬底中的凹槽内；
图2A至图2K是根据多种实施例的制造3DIC的中间阶段的截面图，其中，管芯之一位于中介层的模塑料中，并且其中，衬底通孔延伸到模塑料中；以及
图3示出了图2K中所示的结构的改变，其中，互连结构形成在模塑料的表面上。
具体实施方式
以下详细描述本发明实施例的制造和使用。然而，应该理解，本发明提供了可以在多种特定环境下被具体化的多种可应用发明思想。所述的特定实施例仅是示意性的，不限制于本发明的范围。
提供了新的三维集成电路(3DIC)及其形成方法。示出了制造多个实施例的中间阶段。描述了实施例的改变。贯穿多个视图和示意性实施例，类似参考标号被用于指定类似元件。
参考图1A，提供了衬底10。贯穿说明书，结合的衬底10和相应互连结构12和32(在图1A中未示出，请参考图3)被称为中介层晶片100。所示的结构仅为中介层晶片100中的芯片(chip)/管芯(die)的一部分，其包括与所示芯片相同的多个芯片。衬底10可以由半导体材料形成，诸如硅、锗化硅、碳化硅、砷化镓、或其他通常使用的半导体材料。可选地，衬底10由介电材料形成，诸如氧化硅。中介层晶片100可以基本不具有集成电路器件(包括有源器件，诸如晶体管和二极管)。而且，中介层晶片100可以包括，或者可以不具有无源器件，诸如电容器、电阻器、电感器、变容器、和/或其他。
衬底通孔(TSV)20被形成并且延伸至衬底10。TSV 20包括大TSV 20A和小TSV 20B。大TSV 20A的水平尺寸W1(其可以为直径或者长度/宽度，这取决于各个TSV的形状)大于小TSV 20B的水平尺寸W2。在一个实施例中，W1/W2的比率大于约1.5，或者甚至大于约2。而且，大TSV 20A的长度L1大于小TSV 20B的长度L2。在一个实施例中，L1/L2的比率大于约1.5，或者甚至大于约2。在用于形成具有不同尺寸的TSV 20A和20B的示例性实施例中，被用于形成TSV开口的光刻胶(未示出)的开口可以具有不同水平尺寸，例如，一些等于水平尺寸W1，以及另外一些等于水平尺寸W2。作为在蚀刻工艺中负载效应的结果，TSV开口和所得到的对于TSV 20A和20B的TSV开口将具有不同的水平尺寸和不同的深度。从而，小TSV 20B的长度L2可以通过调节W1/W2的比率来控制。每个TSV 20均通过绝缘层19与衬底10电绝缘。
正面互连结构12形成在TSV 20和衬底10之上，并且包括一个或多个介电层18以及介电层18中的金属线14和通孔16。遍及说明书，在图1中面向上的中介层晶片100一侧被称为正面，以及面向下的一侧被称为背面。金属线14和通孔16被称为正面重分布线(RDL)。正面RDL 14/16电连接至TSV 20。
接下来，正面(金属)凸块(或接合焊盘)24形成在中介层晶片100的正面，并且电连接至TSV 20和RDL 14/16。在一个实施例中，正面金属凸块24为焊料凸块，诸如共晶焊料凸块。在可选实施例中，正面金属凸块24为铜凸块或者由金、银、镍、钨、铝、及其合金形成的其他金属凸块。正面金属凸块24可以或者不可以从互连结构12的表面突出。
参考图1B，管芯22被接合至正面凸块24。虽然图1B示出了三个管芯被接合到同一管芯/芯片上，但是在多种实施例中，管芯22的数量的范围可以是仅一个管芯22到多个管芯22。管芯22可以为包括集成电路器件的器件管芯，集成电路器件诸如晶体管、电容器、电感器、电阻器(未示出)等。而且，管芯22可以为包括核心电路的逻辑管芯，并且可以为例如中央处理单元(CPU)管芯。在管芯22和金属凸块24之间的接合可以为焊料接合或者直接金属至金属(诸如铜至铜)接合。未充满部分23被分配到管芯22和中介层晶片100之间的间隙中，然后被固化。
参考图1C，可以为玻璃晶片的载体26通过粘合剂28被接合到中介层晶片100的正面。粘合剂28可以为紫外胶，或者可以由其他已知的粘合剂材料形成。可以执行蚀刻，以蚀刻衬底10的一部分，来形成凹槽29，使得小TSV 20B或者小TSV 20B的绝缘层19露出。
接下来，如图1D中所示，例如通过对衬底10的背面10B执行背面研磨使衬底10变薄。可以进一步蚀刻背面10B，如图1E所示，使得大TSV 20A和相应的绝缘层19可以从背面10B突出。参考图1F，覆盖层形成介电层30，其中，介电层30可以为旋涂玻璃或者其他通常使用的介电材料。
在图1G中，形成并且图案化光刻胶31，光刻胶31的开口垂直叠加在TSV 20上。然后执行蚀刻，以去除覆盖TSV20的介电材料，使得TSV 20露出。
图1H示出了凸块底部金属(UBM)36的形成。在一个实施例中，UBM36由化学镀镍钯浸金(ENEPIG)、浸锡、化学镀镍浸金(ENIG)等形成，但是可以使用其他类型的材料和方法。
接下来，如图1I所示，管芯40被接合至中介层晶片100的背面并且电连接至小TSV 20B。管芯40可以通过正面互连结构12和小TSV 20B电连接至管芯22。管芯22和40可以为不同类型的管芯。例如，管芯22可以为逻辑管芯，诸如CPU管芯，同时管芯40可以为存储器管芯。根据衬底10的厚度、管芯40的厚度和凹槽29的深度，管芯40可以全部或部分在凹槽29内侧。管芯40到中介层晶片100的接合可以为焊料接合、直接金属-金属接合等。接下来，未充满部分42被分配到管芯40和中介层晶片100之间的间隙中。
参考图1J，背面金属凸块44被形成并且电连接至大TSV 20A。类似地，背面金属凸块44可以为焊料凸块、铜凸块、或其他金属凸块(诸如含铜凸块)。在多种实施例中，包括在多个介电层中的RDL的背面互连结构(未示出，但是类似于图3中的互连结构32)可以形成在中介层晶片100的背面并且将大TSV 20A电连接至背面金属凸块44。在这些实施例中，背面金属凸块44形成在背面互连结构的表面上。
在图1K中，例如通过使UV胶28暴露至UV光，使图1J中所示的载体26去接合。然后，将切割胶带(或者临时载体)50粘附至所得到的结构的正面。接下来，沿着划线52执行切割，以使所示管芯与中介层晶片100分离。每个所得到的管芯都包括中介层管芯100’、一个或多个管芯22、以及管芯40。
图2A至图2K示出了可选实施例。除了另外说明，这些实施例中的类似参考标号表示图1A至图1K中所示的实施例中的类似元件。形成类似元件的详情还可以在图1A至图1K中所示的实施例中找到，因此在此不再重复。参考图2A，大TSV 20A和小TSV 20B形成在中介层晶片100的衬底10中。TSV 20A和20B的尺寸已经在图1A至图1K中所示的实施例中描述过，因此在此不再描述。参考图2B，正面互连结构12形成在衬底10上并且电连接至TSV 20A和20B。接下来，如在图2C中所示，载体26通过粘合剂28被接合至中介层晶片100的正面，接下来进行薄化工艺。薄化工艺可以包括研磨和/或蚀刻。在薄化工艺之后，大TSV 20A和小TSV 20B从衬底10的背面10B突出。在薄化工艺中，整个芯片/管芯的衬底10的背面10B的全部，或者甚至整个中介层晶片100的全部都是凹进的，并且所得到的衬底10的背面10B除了从TSV 20突出的部分之外基本是平坦的。
接下来，如图2D中所示，介电层60形成覆盖层，以覆盖TSV 20和背面10B。在一个实施例中，介电层60由氮化硅形成，虽然可以使用其他介电材料。然后，涂覆光刻胶62。接下来，如图2E中所示，执行蚀刻以去除介电层60的顶部，使得TSV 20可以露出。注意到，在蚀刻工艺期间，大TSV 20A的顶部20A’可以被氧化，从而可以形成诸如氧化铜的金属氧化物。
图2F示出了在小TSV 20B上形成UBM 36，其中，UBM 36的材料和形成方法可以与图1H中基本相同。然而，由于金属氧化物的形成导致没有UBM形成在大TSV 20A上。在图2G中，管芯40被接合到中介层晶片100上并且电连接至小TSV 20B。然后可以施加未充满部分42。
参考图2H，模塑料66被模制到管芯40和中介层晶片100上。模塑料66的顶面可以比大TSV 20A的顶面高或者与其齐平。参考图2I，执行研磨以平面化模塑料66和大TSV 20A的表面。而且，被氧化的大TSV 20A的顶部20A’同样通过研磨去除，直到未氧化的部分暴露。接下来如图2J所示，UBM 36被形成为覆盖大TSV 20A，接下来形成背面金属凸块44，其电连接至大TSV 20A。
图2K示出了载体26的去接合以及管芯22到中介层晶片100正面的接合。在随后的工艺步骤中，切割中介层晶片100，每个所得到的管芯都包括管芯22、管芯40、以及中介层(管芯)100’(中介层晶片100的一部分)。。在所得到的结构中，注意到，大TSV 20A穿过衬底10和模塑料66，并且模塑料66包围每个大TSV 20A的一部分。而且，大TSV 20A的底端可以延伸到管芯40的底面之下。
图3示出了可选实施例。除了背面互连结构32也形成在中介层晶片100的背面上之外，该实施例类似于图2K中所示的实施例。背面互连结构32包括在多个介电层中的多个RDL 72。注意到，一些背面金属凸块44(被标记为44’)可以垂直叠加于管芯40的多个部分，并且因此背面金属凸块44的数量增加，超过图2K中所示的结构的背面金属凸块的数量。而且，背面金属凸块44电连接至RDL 72，其可以进一步包括垂直叠加管芯40的一部分。
在多个实施例中，具有不同尺寸的TSV被形成并且电连接至被嵌入在中介层的衬底10中或者被嵌入在填充大TSV 20A之间的模塑料中的管芯40。从而，管芯40的厚度不受背面金属凸块44的尺寸限制。而且，在多个实施例中，大TSV 20A和小TSV 20B的形成通过水平尺寸自我控制，从而减少了制造成本。
尽管已经详细地描述了本发明及其优势，但应该理解，可以在不背离所附权利要求限定的本发明主旨和范围的情况下，做各种不同的改变，替换和更改。而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解，通过本发明，现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造，材料组分、装置、方法或步骤根据本发明可以被使用。因此，所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。此外，每条权利要求构成单独的实施例，并且多个权利要求和实施例的组合在本发明的范围内。

Claims (10)

1.一种器件，包括：
中介层，包括具有顶面和底面的衬底；
多个衬底通孔(TSV)，穿过所述衬底，其中，所述多个TSV包括具有第一长度和第一水平尺寸的第一TSV和具有不同于所述第一长度的第二长度以及不同于所述第一水平尺寸的第二水平尺寸的第二TSV；以及
第一互连结构，被形成为置于所述衬底的所述顶面上并且电连接至所述多个TSV。
2.根据权利要求1所述的器件，其中，所述第一水平尺寸大于所述第二TSV的所述第二水平尺寸，或者所述第一水平尺寸与所述第二水平尺寸的比大于约1.5，或者所述第一长度大于所述第二长度。
3.根据权利要求1所述的器件，进一步包括：
第一管芯，置于所述第一互连结构上；以及
第二管芯，置于所述衬底的所述底面下并且电连接至所述第二TSV。
4.根据权利要求3所述的器件，其中，所述第二管芯被接合至所述第二TSV，或者
进一步包括：置于所述衬底的所述底面下的模塑料，其中，所述第一TSV延伸以穿过所述模塑料，其中，所述第二管芯形成在所述模塑料中，所述器件进一步包括：金属凸块，在所述模塑料的底面上并且电连接至所述第一TSV；或者第二互连结构，在所述模塑料下并且电连接至所述第一TSV，或者
所述衬底包括从所述衬底的所述底面延伸到所述衬底的凹槽，并且其中，所述第二管芯的至少一部分位于所述凹槽中。
5.根据权利要求1所述的器件，进一步包括：金属凸块，置于所述第二互连结构下并且电连接至所述第一TSV；或者
其中，所述衬底为基本上不具有集成电路器件的硅衬底。
6.一种器件，包括：
硅衬底，基本不具有集成电路器件；
第一衬底通孔(TSV)，具有从所述硅衬底的顶面延伸到所述硅衬底的第一底面的第一长度；
第二TSV，具有从所述硅衬底的所述顶面延伸到所述硅衬底的第二底面的第二长度，其中所述第一长度大于所述第二长度；
第一管芯，置于所述硅衬底的所述顶面上；以及
第二管芯，置于所述硅衬底的所述第二底面下并且电连接至所述第二TSV。
7.根据权利要求6所述的器件，其中，所述第一TSV具有大于所述第二TSV的第二水平尺寸的第一水平尺寸；或者
所述硅衬底包括从所述硅衬底的所述第一底面延伸至所述第二底面的凹槽，并且其中，所述第二管芯的至少一部分位于所述凹槽中。
8.一种器件，包括：
硅衬底，基本不具有集成电路器件；
模塑料，置于所述硅衬底下；
第一衬底通孔(TSV)，从所述硅衬底的顶面延伸到所述模塑料的底面；
第二TSV，从所述衬底的所述顶面延伸到所述硅衬底的底面；
第一管芯，置于所述硅衬底的所述顶面上；以及
第二管芯，在所述模塑料中并且电连接至所述第二TSV。
9.根据权利要求8所述的器件，其中，所述第一TSV的第一水平尺寸大于所述第二TSV的第二水平尺寸。
10.根据权利要求8所述的器件，进一步包括：焊接凸块，置于所述模塑料的所述底面下并且电连接至所述第一TSV；或者
进一步包括：互连结构，置于所述模塑料的所述底面下并且电连接至所述第一TSV。
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