CN101350337A - 具有晶圆黏片胶带的集成电路及其封装方法 - Google Patents

具有晶圆黏片胶带的集成电路及其封装方法 Download PDF

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Publication number
CN101350337A
CN101350337A CNA2007103019917A CN200710301991A CN101350337A CN 101350337 A CN101350337 A CN 101350337A CN A2007103019917 A CNA2007103019917 A CN A2007103019917A CN 200710301991 A CN200710301991 A CN 200710301991A CN 101350337 A CN101350337 A CN 101350337A
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Prior art keywords
wafer
conducting film
adhesive tape
anisotropy conducting
sheet adhesive
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CN101350337B (zh
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苏昭源
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明是有关于一种具有晶圆黏片胶带的集成电路及其封装方法。该集成电路包含晶片及连接于晶片背部表面的异方性导电膜。晶片具有前表面、位于晶片前表面的反面的背部表面以及暴露于晶片背部表面的硅贯通电极。本发明利用异方性导电膜作为晶片的电性连接层，可以吸收硅贯通电极凸出长度的差异。如此可避免传统封装制程中晶片倾斜的情况，当封装完毕后，晶片可平行于相对应的封装基板。

Description

具有晶圆黏片胶带的集成电路及其封装方法
技术领域
本发明是有关于一种集成电路，特别是有关于一种半导体晶片的封装技术，且特别是有关于一种具有硅贯通电极(Through-Silicon Vias；TSV)的半导体晶片的封装技术。
背景技术
硅贯通电极亦泛指穿透晶圆的电极(Through-wafer vias；TWV)，广泛地使用于集成电路。硅贯通电极适用于作晶片堆叠。在具有第一个晶片堆叠在第二个晶片上的堆叠晶片中，第一个晶片可借由其硅贯通电极而电性连接至第二个晶片的顶部表面。硅贯通电极亦广泛地运用于提供晶片前表面至背部表面的快速且低阻力的路径。
图1至图3绘示在晶片内形成硅贯通电极及借由硅贯通电极接地的传统制程中间阶段的剖面示意图。参照图1，硅贯通电极12形成于晶片10内，并大体上自晶片10的前表面(顶部表面)延伸至基板14，基板14通常是由硅所组成。硅贯通电极12可为晶片10内的集成电路提供接地路径。鉴于制程(也就是，制造方法)的差异，硅贯通电极12可能具有不同长度L。
在图2中，使用研浆(Slurry)侵蚀硅以研磨晶片10的背部表面。为确保所有的硅贯通电极12皆暴露于背部表面，需研磨硅基板14至一定程度使至少部分硅贯通电极12稍微凸出于背部表面。由于硅贯通电极12的长度不一致，因此有些硅贯通电极12会凸出较多。
在图3中，借由银胶18将晶片10固定于基板16上，基板16可能为导线架或其他种类的封装基板。一般而言，银胶18为液态。施加银胶18于基板16后，将晶片10压合至银胶18。银胶18具有导电性，因此可电性连接硅贯通电极12。晶片10借由硅贯通电极12而接地。由于硅贯通电极12可能会以不同长度L凸出于晶片10的背部表面，因此晶片10可能会倾斜。此会导致可靠性的问题。例如，当形成打线接合后，会施加模铸材料20。由于晶片10的倾斜，打线接合的一部分(例如打线22)可能不会完全被模铸材料20所覆盖，因此易遭受机械性伤害。
解决上述问题的途径为在研磨完基板14之后，研磨凸出来的硅贯通电极12。然而，硅贯通电极12通常是由铜所组成，其所需要的研浆与研磨硅基板所用的研浆不同，故需要额外的研磨制程。再者，由于污染的问题，研磨铜的制程的成本大于研磨硅。因此，研磨背部的硅贯通电极是非理想的解决问题的办法。于是需要新的方法，可以在不会导致上述问题的情况下封装晶片于基板上。
有鉴于上述现有的集成电路制成存在的缺陷，本发明人基于从事此类产品设计制造多年丰富的实务经验及专业知识，并配合学理的运用，积极加以研究创新，以期创设一种新的集成电路结构及其封装结构的形成方法，使其更具有实用性。经过不断的研究、设计，并经反复试作样品及改进后，终于创设出确具实用价值的本发明。
发明内容
本发明的目的在于利用异方性导电膜做为晶片的电性连接层，可以吸收硅贯通电极凸出长度的差异。如此可避免传统封装制程中晶片倾斜的情况，当封装完毕后，晶片可平行于相对应的封装基板。
因此本发明的一方面是提供一种集成电路结构，包含晶片以及连接于晶片背部表面的异方性导电膜(Anisotropic Conducting Film；ACF)。晶片包含前表面、位于晶片的前表面的反面的背部表面以及暴露于晶片的背部表面的硅贯通电极。
本发明的另一方面是提供一种集成电路晶圆黏片胶带，包含紫外线晶圆黏片胶带以及异方性导电膜，异方性导电膜位于紫外线晶圆黏片胶带的一面之上。
本发明的另一方面是提供一种方法以形成封装结构，包含提供晶片，其具有前表面、位于前表面的反面的背部表面以及暴露于晶片的背部表面的硅贯通电极。此方法更包含将异方性导电膜贴附于晶片的背部表面，其中硅贯通电极穿透入异方性导电膜。
本发明的另一方面是提供一种方法以形成封装结构，包含提供半导体晶圆以及提供集成电路晶圆黏片胶带。集成电路晶圆黏片胶带具有紫外线晶圆黏片胶带以及异方性导电膜，异方性导电膜位于紫外线晶圆黏片胶带的一面之上。此方法更包含将半导体晶圆贴附到集成电路晶圆黏片胶带，其中晶圆的背部表面和异方性导电膜相接触。切割半导体晶圆以分离位于半导体晶圆中的晶片。暴露紫外线晶圆黏片胶带于紫外线下。将紫外线晶圆黏片胶带自异方性导电膜脱落。将从半导体晶圆分离的晶片固定于封装基板上，其中异方性导电膜介于晶片和封装基板之间。
借由使用异方性导电膜做为电性连接层，可以吸收硅贯通电极凸出长度的差异。当封装完毕后，晶片可平行于相对应的封装基板。
本发明的目的及解决其技术问题是采用以下技术方案来实现的。依据本发明提出的一种集成电路结构，包含：一晶片，其包含：一前表面；一背部表面位于该晶片的该前表面的反面；以及一硅贯通电极暴露于该晶片的该背部表面；以及一异方性导电膜贴附于该晶片的该背部表面。
本发明的目的及解决其技术问题还采用以下技术措施来进一步实现。
前述的集成电路结构，其中所述的硅贯通电极凸出于该晶片的该背部表面，并穿透入该异方性导电膜。
前述的集成电路结构，其还包含一封装基板，其中该异方性导电膜介于该封装基板及该晶片之间。
前述的集成电路结构，其中所述的异方性导电膜连接该封装基板。
前述的集成电路结构，其中所述的封装基板选自于由玻璃基板、双马来亚酰胺三氮六环化合物基板、印刷电路基板及导线架所组成的群组。
前述的集成电路结构，其还包含介于该封装基板及该异方性导电膜的间的一导电层。
前述的集成电路结构，其中所述的封装基板包含一导电层，且其中该导电层进一步电性连接至位于该晶片内的该硅贯通电极及额外一硅贯通电极。
前述的集成电路结构，其中所述的晶片是一晶圆的一部分，且其中该集成电路结构更包含和该异方性导电膜相连接的一紫外线晶圆黏片胶带，且其中该异方性导电膜及该紫外线晶圆黏片胶带的大小不会小于该晶圆的大小。
前述的集成电路结构，其中所述的异方性导电膜与该紫外线晶圆黏片胶带相连接，该异方性导电膜不与该晶圆相连接。
本发明的目的及解决其技术问题还采用以下技术方案来实现。依据本发明提出的一种集成电路晶圆黏片胶带，其包含一紫外线晶圆黏片胶带；以及一异方性导电膜位于该紫外线晶圆黏片胶带的一面上。
本发明的目的及解决其技术问题还采用以下技术措施来进一步实现。
前述的集成电路晶圆黏片胶带，其中所述的紫外线晶圆黏片胶带连接该异方性导电膜。
前述的集成电路晶圆黏片胶带，其还包含介于该紫外线晶圆黏片胶带和该异方性导电膜之间的一挠性导电层。
前述的集成电路晶圆黏片胶带，其中所述的挠性导电层连接该异方性导电膜。
前述的集成电路晶圆黏片胶带，其中所述的异方性导电膜的厚度约为25μM至75μM。
本发明的目的及解决其技术问题还采用以下技术方案来实现。依据本发明提出的一种封装结构的形成方法，其包含：提供一晶片，该晶片包含：一前表面；一背部表面位于该前表面的反面；以及一硅贯通电极暴露于该晶片的该背部表面；以及贴附一异方性导电膜于该晶片的该背部表面，其中该硅贯通电极穿透入该异方性导电膜。
本发明的目的及解决其技术问题还采用以下技术措施来进一步实现。
前述的封装结构的形成方法，其中所述的在贴附该异方性导电膜的步骤包含：提供一集成电路晶圆黏片胶带，该胶带包含：一紫外线晶圆黏片胶带；以及一异方性导电膜位于该紫外线晶圆黏片胶带的一面上；贴附一半导体晶圆至该集成电路晶圆黏片胶带，其中该晶片是该晶圆的一部分，且其中该晶圆的该背部表面和该异方性导电膜相接触；切割该半导体晶圆以分离位于该半导体晶圆内的多个晶片；暴露该紫外线晶圆黏片胶带于一紫外线中；以及将该紫外线晶圆黏片胶带自该异方性导电膜上脱落。
前述的封装结构的形成方法，其中所述的提供该晶圆的步骤包含：提供具有该晶片的一晶圆，其中该晶片包含许多硅贯通电极；以及研磨该晶圆背部以暴露出所述硅贯通电极。
前述的封装结构的形成方法，还包含固定该晶片及该异方性导电膜至一封装基板上，其中所述硅贯通电极包含至少二种不同的硅贯通电极长度，且其中当完成固定的步骤后，该晶片的一背部表面大体上与该封装基板的表面平行。
本发明的目的及解决其技术问题还采用以下技术方案来实现。依据本发明提出的一种封装结构的形成方法，其包含：提供一半导体晶圆；提供一集成电路晶圆黏片胶带，该胶带包含：一紫外线晶圆黏片胶带；以及一异方性导电膜位于该紫外线晶圆黏片胶带的一面上；贴附一半导体晶圆至该集成电路晶圆黏片胶带，其中该晶圆的一背部表面和该异方性导电膜相接触；切割该半导体晶圆以分离位于该半导体晶圆内的多个晶片；暴露该紫外线晶圆黏片胶带于一紫外线中；将该紫外线晶圆黏片胶带自该异方性导电膜上脱落；以及固定与该半导体晶圆分离的一晶片于一封装基板上，其中该异方性导电膜介于该晶片及该封装基板之间。
本发明的目的及解决其技术问题还采用以下技术措施来进一步实现。
前述的封装结构的形成方法，其中所述的晶片包含凸出于该晶片的一背部表面的一硅贯通电极，且其中该固定晶片的步骤中，该硅贯通电极穿透入该异方性导电膜。
前述的封装结构的形成方法，其中所述的硅贯通电极至少有二个硅贯通电极以不同长度凸出于该晶片的该背部表面。
前述的封装结构的形成方法，其中所述在切割该半导体晶圆的步骤中，切口延伸至该异方性导电膜。
前述的封装结构的形成方法，其中所述的异方性导电膜更包含介于该封装基板与该异方性导电膜之间的一导电层，且其中在将该紫外线晶圆黏片胶带自该异方性导电膜脱落的步骤之后，该导电层会贴附到该异方性导电膜上。
借由上述技术方案，本发明至少具有下列优点：
首先，借由使用异方性导电膜，可将硅贯通电极长度的差异性加以吸收。
其次，晶片可因异方性导电膜的使用而和基板维持平行。
再者，经由本发明的技术方案，可将传统上晶片封装结构可能暴露于模铸材料的情况降低。
上述说明仅是本发明技术方案的概述，为了能够更清楚了解本发明的技术手段，而可依照说明书的内容予以实施，并且为了让本发明的上述和其他目的、特征和优点能够更明显易懂，以下特举较佳实施例，并配合附图，详细说明如下。
附图说明
图1至图3是用以说明传统制造及封装半导体晶片的中间过程的代表图。
图4至图8是用以说明制造本发明实施例的中间过程的代表图。
10：晶片                   38：导电基质
12：硅贯通电极             39：导电层
14：硅基板                 40：晶圆
16：基板                   42：晶片
18：银胶                   44：半导体基板
20：模铸材料               45：电晶体
22：打线                   46：硅贯通电极
30：集成电路晶圆黏片胶带   48：接合垫
32：异方性导电膜           50：封装基板
34：紫外线晶圆黏片胶带     51：重布线路
36：导电粒子               52：模铸材料
具体实施方式
为更进一步阐述本发明为达成预定发明目的所采取的技术手段及功效，以下结合附图及较佳实施例，对依据本发明具体实施方式、结构、方法特征及其功效，详细说明如后。
依照本发明一较佳实施例的制造和使用详述如下。本发明提供许多应用性的发明概念，能在许多广大的特定本文中据以实施。在此所述的特定实施例仅做为说明本发明特定的制造和使用，其并非用以限定本发明的范围。
在此提供一种崭新的封装结构及其方法。并说明制造本发明实施例的中间过程。本发明各种不同的观点和说明的实施例，皆以类似的参考数字标示类似的元件。
参照图4A，其绘示依照本发明一较佳实施例的一种集成电路晶圆黏片胶带(Integrated wafer-mount tape)30，包含异方性导电膜32及紫外线晶圆黏片胶带34。如同已知技术，异方性导电膜32包含许多借由非导电基质38(可以为环氧树脂)而彼此隔离开来的导电粒子36。每一个导电粒子36可能是被导电物质(例如镍和金)所包覆的聚合球形。隔缘的导电粒子36以此方式分布，以降低彼此之间偶然发生的接触率。据此，导电粒子36可包埋在基质38里。在一示范性的实施例中，异方性导电膜32的厚度约为25μM至75μM。异方性导电膜32的厚度需比硅贯通电极46突出来的部分的长度大(参照图7)。细节详述如后续的图。
紫外线晶圆黏片胶带34具有黏性，而当暴露于紫外线的下则可能会失去黏性。在一实施中，如图4A所示，异方性导电膜32及紫外线晶圆黏片胶带34彼此互相接触。在另一实施例中，如图4B所示，导电层39(具有挠性较佳)可能会形成于异方性导电膜32和紫外线晶圆黏片胶带34的间。在一示范性的实施例中，导电层39是由与异方性导电膜类似的材料所形成。但导电层39的导电粒子的密度远大于异方性导电膜，使导电层39的传导度不仅为Y方向，也可以是X方向。导电层39也可由其他材料所组成，例如镍、金或其他类似物。
参照图5，晶圆40借由晶圆背部和异方性导电膜32相接触，而贴附到集成电路晶圆黏片胶带30。晶圆40包含许多晶片42，每一个晶片包含基板44及许多硅贯通电极46。晶片42更包含半导体基板44及形成于半导体基板44前表面的集成电路。电晶体45象征集成电路(未绘示)。内连线结构，包含形成于低k值介电层的金属线及介层接触，形成于集成电路之上，作为集成电路的内连线。硅贯通电极46可能会连接到晶片42内的集成电路。在一实施例中，接合垫48形成于晶片42的前表面，其中利用接合垫48以连接晶片42到封装基板或其他可能会层积在晶片42的晶片。
如同已知技术，硅贯通电极46的形成，包含形成大体上由晶圆40前表面延伸至半导体基板44的介层窗通道，并利用导电材料(如铜或铜合金)填充通道。接着研磨晶圆40的背部表面以暴露出硅贯通电极46。鉴于制程的差异，硅贯通电极46可能会包含不同长度，并以不同长度凸出于晶片42的背部表面。
当晶圆40贴覆到集成电路晶圆黏片胶带30后，需施加适当的力量，使硅贯通电极46凸出的部分能穿入至少一部分的异方性导电膜32。接着沿着切割线切割晶圆40以分离晶片42。以切口较佳系延伸至异方性导电膜，异方性导电膜亦因此亦可分离成晶片大小的片段。
接着将紫外线晶圆黏片胶带34暴露于紫外线下，使的不具黏性。晶片42可因此自紫外线晶圆黏片胶带34上脱落。其产生的结构，如同图6所示，每一个晶片42的背部会贴附到每一个异方性导电膜的片段。
图7A绘示将晶片42固定到封装基板50。封装基板50可能是玻璃基板、双马来亚酰胺三氮六环化合物(Bismaleimide Trianzine，BT)基板、印刷电路板或其他可封装晶片的常用基板。封装基板也可以是导线架。接合垫或金属导线架(未绘示)可能会形成于封装基板的表面，并和异方性导电膜32相接触。在实施例中，硅贯通电极46为接地的目的。封装基板50表面可能包含导电层52以缩短硅贯通电极46。
接着施加压力及热于图7A所示的结构上来作用基质38以确保异方性导电膜32能贴附到封装基板50上。在压力作用之下，导电粒子36会被吸附住，且隔离材料38会被排开而使硅贯通电极46借由导电粒子36电性连接封装基板50。在一示范性实施例中，作用温度约为150℃至210℃。然而最适当压力当视硅贯通电极46的数目而定。在最后产生的结构中，硅贯通电极46彼此之间导通及借由导电层52而与接地导通。
在另一实施例中，如图7B所示，若集成电路晶圆黏片胶带30包含导电层39，则当移除紫外线晶圆黏片胶带34时，会遗留导电层39于异方性导电膜32上。硅贯通电极46会借由导电层39而与接地导通。
在又一实施例中，如图7C所示，硅贯通电极46并非用以做为接地的目的。硅贯通电极46借由异方性导电膜连接封装基板50中的电性隔离的接合垫及重布电路(redistribution traces)51。
图8中，晶片42借由打线接合电性连接封装基板50。接着形成模铸材料52以保护所产生的封装基板。
本发明的实施例具有数个下列优势的特色。首先，借由异方性导电膜32，硅贯通电极46长度的差异会被异方性导电膜所吸收。使晶片42平行于封装基板50。因而降低所产生的封装结构部分暴露于模铸材料之外的可能性。
虽然本发明及其优点已详细揭露如上，在不脱离本发明后附申请专利范围的精神和范筹内，当可作各种的更动、取代与润饰。此外，本发明的应用范围并未局限于上述说明书中的特定实施例的制程、机器、制品、物质组成、工具、方法及步骤。任何熟习此技艺者将立即察知所揭露的本发明、制程、机器、制品、物质组成、工具、方法或步骤，和已存在或日后所发展的物，系与本发明所述的相对应实施例大体上执行相同功能或达到相同结果。因此，权利要求包含此类的制程、机器、制品、物质组成、工具、方法或步骤。
以上所述，仅是本发明的较佳实施例而已，并非对本发明作任何形式上的限制，虽然本发明已以较佳实施例揭露如上，然而并非用以限定本发明，任何熟悉本专业的技术人员，在不脱离本发明技术方案范围内，当可利用上述揭示的方法及技术内容作出些许的更动或修饰为等同变化的等效实施例，但是凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本发明技术方案的范围内。

Claims (23)

1、一种集成电路结构，其特征在于包含：
一晶片，其包含：
一前表面；
一背部表面位于该晶片的该前表面的反面；以及
一硅贯通电极暴露于该晶片的该背部表面；以及
一异方性导电膜贴附于该晶片的该背部表面。
2、如权利要求1所述的集成电路结构，其特征在于其中该硅贯通电极凸出于该晶片的该背部表面，并穿透入该异方性导电膜。
3、如权利要求1所述的集成电路结构，其特征在于还包含一封装基板，其中该异方性导电膜介于该封装基板及该晶片之间。
4、如权利要求3所述的集成电路结构，其特征在于其中该异方性导电膜连接该封装基板。
5、如权利要求3所述的集成电路结构，其其特征在于中该封装基板选自于由玻璃基板、双马来亚酰胺三氮六环化合物基板、印刷电路基板及导线架所组成的群组。
6、如权利要求3所述的集成电路结构，其特征在于还包含介于该封装基板及该异方性导电膜的间的一导电层。
7、如权利要求3所述的集成电路结构，其特征在于其中该封装基板包含一导电层，且其中该导电层进一步电性连接至位于该晶片内的该硅贯通电极及额外一硅贯通电极。
8、如权利要求1所述的集成电路结构，其特征在于其中该晶片是一晶圆的一部分，且其中该集成电路结构更包含和该异方性导电膜相连接的一紫外线晶圆黏片胶带，且其中该异方性导电膜及该紫外线晶圆黏片胶带的大小不会小于该晶圆的大小。
9、如权利要求8所述的集成电路结构，其特征在于其中该异方性导电膜与该紫外线晶圆黏片胶带相连接，该异方性导电膜不与该晶圆相连接。
10、一种集成电路晶圆黏片胶带，其特征在于包含
一紫外线晶圆黏片胶带；以及
一异方性导电膜位于该紫外线晶圆黏片胶带的一面上。
11、如权利要求10所述的集成电路晶圆黏片胶带，其特征在于其中该紫外线晶圆黏片胶带连接该异方性导电膜。
12、如权利要求10所述的集成电路晶圆黏片胶带，其特征在于还包含介于该紫外线晶圆黏片胶带和该异方性导电膜之间的一挠性导电层。
13、如权利要求10所述的集成电路晶圆黏片胶带，其特征在于其中该挠性导电层连接该异方性导电膜。
14、如权利要求10所述的集成电路晶圆黏片胶带，其特征在于其中该异方性导电膜的厚度约为25μM至75μM。
15、一种封装结构的形成方法，其特征在于包含：
提供一晶片，该晶片包含：
一前表面；
一背部表面位于该前表面的反面；以及
一硅贯通电极暴露于该晶片的该背部表面；以及
贴附一异方性导电膜于该晶片的该背部表面，其中该硅贯通电极穿透入该异方性导电膜。
16、如权利要求15所述的封装结构的形成方法，其特征在于其中该贴附该异方性导电膜的步骤包含：
提供一集成电路晶圆黏片胶带，该胶带包含：
一紫外线晶圆黏片胶带；以及
一异方性导电膜位于该紫外线晶圆黏片胶带的一面上；
贴附一半导体晶圆至该集成电路晶圆黏片胶带，其中该晶片是该晶圆的一部分，且其中该晶圆的该背部表面和该异方性导电膜相接触；
切割该半导体晶圆以分离位于该半导体晶圆内的多个晶片；
暴露该紫外线晶圆黏片胶带于一紫外线中；以及
将该紫外线晶圆黏片胶带自该异方性导电膜上脱落。
17、如权利要求15所述的封装结构的形成方法，其特征在于其中该提供该晶圆的步骤包含：
提供具有该晶片的一晶圆，其中该晶片包含许多硅贯通电极；以及
研磨该晶圆背部以暴露出所述硅贯通电极。
18、如权利要求17所述的封装结构的形成方法，其特征在于还包含固定该晶片及该异方性导电膜至一封装基板上，其中所述硅贯通电极包含至少二种不同的硅贯通电极长度，且其中当完成固定的步骤后，该晶片的一背部表面大体上与该封装基板的表面平行。
19、一种封装结构的形成方法，其特征在于包含：
提供一半导体晶圆；
提供一集成电路晶圆黏片胶带，该胶带包含：
一紫外线晶圆黏片胶带；以及
一异方性导电膜位于该紫外线晶圆黏片胶带的一面上；
贴附一半导体晶圆至该集成电路晶圆黏片胶带，其中该晶圆的一背部表面和该异方性导电膜相接触；
切割该半导体晶圆以分离位于该半导体晶圆内的多个晶片；
暴露该紫外线晶圆黏片胶带于一紫外线中；
Figure A2007103019910004C1
固定与该半导体晶圆分离的一晶片于一封装基板上，其中该异方性导电膜介于该晶片及该封装基板之间。
20、如权利要求19所述的封装结构的形成方法，其特征在于其中该晶片包含凸出于该晶片的一背部表面的一硅贯通电极，且其中该固定晶片的步骤中，该硅贯通电极穿透入该异方性导电膜。
21、如权利要求19所述的封装结构的形成方法，其特征在于其中所述硅贯通电极至少有二个硅贯通电极以不同长度凸出于该晶片的该背部表面。
22、如权利要求19所述的封装结构的形成方法，其特征在于其中在切割该半导体晶圆的步骤中，切口延伸至该异方性导电膜。
23、如权利要求19所述的封装结构的形成方法，其特征在于其中该异方性导电膜更包含介于该封装基板与该异方性导电膜之间的一导电层，且其中在将该紫外线晶圆黏片胶带自该异方性导电膜脱落的步骤之后，该导电层会贴附到该异方性导电膜上。
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US7825517B2 (en) 2010-11-02
US20110014749A1 (en) 2011-01-20
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CN101350337B (zh) 2011-10-05
US8124458B2 (en) 2012-02-28

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