CN107195607A - 一种芯片封装方法及芯片封装结构 - Google Patents

一种芯片封装方法及芯片封装结构 Download PDF

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Publication number
CN107195607A
CN107195607A CN201710536546.2A CN201710536546A CN107195607A CN 107195607 A CN107195607 A CN 107195607A CN 201710536546 A CN201710536546 A CN 201710536546A CN 107195607 A CN107195607 A CN 107195607A
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chip
layer
pillar
packaging method
panel level
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CN201710536546.2A
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CN107195607B (zh
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曲连杰
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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Priority to CN201710536546.2A priority Critical patent/CN107195607B/zh
Publication of CN107195607A publication Critical patent/CN107195607A/zh
Priority to US15/957,955 priority patent/US20190006196A1/en
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Publication of CN107195607B publication Critical patent/CN107195607B/zh
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Abstract

本发明的实施例提供一种芯片封装方法及芯片封装结构，涉及半导体技术领域，可提高封装效率以及产出效率。一种芯片封装方法，包括：在第一面板级衬底上形成剥离层，并在所述剥离层上各预设区域分别形成重布线层，位于不同区域的所述重布线层之间相互绝缘；在形成所述重布线层的过程中，还形成第一介质层；将芯片以及与所述芯片连接的支柱，通过所述支柱上的焊料帽与形成在所述预设区域的所述重布线层连接；对所述芯片进行封装，形成封装层；去除所述第一面板级衬底和所述剥离层，并在所述重布线层一侧形成焊球。

Description

一种芯片封装方法及芯片封装结构
技术领域
本发明涉及半导体技术领域，尤其涉及一种芯片封装方法及芯片封装结构。
背景技术
随着集成电路技术的不断发展，电子产品越来越向小型化、智能化以及高可靠性方向发展，而集成电路封装直接影响着集成电路、电子模块乃至整机性能，在集成电路晶片逐步缩小、集成度不断提高的情况下，对集成电路封装提出了越来越高的要求。
传统的半导体行业的芯片封装主要包括如下过程：将晶片上的芯片进行切割，分割成各独立的芯片，将合格的芯片重新按规则排布在衬底上，之后进行封装、形成重布线层(Re-Distribution Layers，简称RDLs)和焊球的工艺。
然而由于半导体行业采用的衬底尺寸较小，一般为6寸、8寸、12寸，使得封装后的产出规模受到限制。
发明内容
本发明的实施例提供一种芯片封装方法及芯片封装结构，可提高封装效率以及产出效率。
为达到上述目的，本发明的实施例采用如下技术方案：
一方面，提供一种芯片封装方法，包括：在第一面板级衬底上形成剥离层，并在所述剥离层上各预设区域分别形成重布线层，位于不同区域的所述重布线层之间相互绝缘；在形成所述重布线层的过程中，还形成第一介质层；将芯片以及与所述芯片连接的支柱，通过所述支柱上的焊料帽与形成在所述预设区域的所述重布线层连接；对所述芯片进行封装，形成封装层；去除所述第一面板级衬底和所述剥离层，并在所述重布线层一侧形成焊球。
优选的，将芯片以及与所述芯片连接的支柱，通过所述支柱上的焊料帽与形成在所述预设区域的所述重布线层连接之前，所述芯片封装方法还包括：将多个晶片固定于第二面板级衬底上，所述晶片包括多个芯片；在每个所述芯片远离所述第二面板级衬底一侧形成支柱以及焊料帽；形成第二介质层，所述第二介质层填充于所述支柱周围露出所述焊料帽；通过切割形成各独立的所述芯片以及与所述芯片连接的所述支柱。
优选的，所述第一介质层在任意相邻所述预设区域之间断开；形成所述封装层之后，去除所述第一面板级衬底之前，所述芯片封装方法还包括：使相邻所述芯片之间的所述封装层在所述第一介质层的断开区域内断开；其中，所述封装层包裹所述第一介质层。
优选的，针对任意所述芯片，与其连接的所述重布线层超出所述芯片的边缘。
优选的，所述剥离层的材料为化学剥离材料或激光剥离材料。
优选的，形成所述支柱包括：依次通过曝光、显影、电铸工艺形成所述支柱。
优选的，所述第一介质层和所述第二介质层的材料相同。
优选的，述晶片的形状为规则多边形；多个所述晶片无缝排布于所述第二面板级衬底上。
基于上述，优选的，所述支柱为铜柱。所述第一面板级衬底为钢化玻璃衬底。
另一方面，提供一种芯片封装结构，可通过上述的任一种芯片封装方法制备得到。
本发明实施例提供一种芯片封装方法及芯片封装结构，通过采用面板级衬底作为第一面板级衬底，可在面板领域的产线进行大面积曝光，从而刻蚀形成位于各预设区域的重布线层，可保证重布线层中金属线的精度，在此基础上，针对每个预设区域，将一个合格的芯片与形成在该预设区域的重布线层电连接，并对芯片进行封装，可实现大规模的封装，提高了封装效率以及产出效率，而且降低了传统半导体行业封装的成本。此外，由于形成重布线层的工艺和形成具有支柱和焊料帽的芯片工艺是分开进行的，可使重布线层以及具有支柱和焊料帽的芯片的工艺复杂度较小，精度不会由于层数太多而降低太多，可保证高的分辨率，因而，本发明还可实现对高端芯片的封装。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明提供的一种芯片封装方法的流程示意图一；
图2为本发明提供的在第一面板级衬底上形成重布线层和第一介质层的示意图；
图3为在图2的基础上将芯片通过支柱上的焊料帽与重布线层连接的示意图；
图4a为在图3的基础上进行封装后的示意图一；
图4b为在图3的基础上进行封装后的示意图二；
图5a为在图4a的基础上去除剥离层和第一面板级衬底并形成焊球后的示意图；
图5b为在图4b的基础上去除剥离层和第一面板级衬底并形成焊球后的示意图；
图6为本发明提供的一种芯片封装后的示意图；
图7为本发明提供的一种芯片封装方法的流程示意图二；
图8a为本发明提供的将多个晶片固定于第二面板级衬底上的示意图一；
图8b为本发明提供的将多个晶片固定于第二面板级衬底上的示意图二；
图8c为图8a中AA′向剖视示意图；
图9为在芯片上形成支柱和焊料帽的示意图；
图10为在图9基础上形成第二介质层的示意图；
图11为在图10基础上后形成各独立的芯片以及与芯片连接的支柱以焊料帽的示意图。
附图标记：
10-第一面板级衬底；20-剥离层；30-重布线层；40-第一介质层；501-晶片；50-芯片；601-支柱；602-焊料帽；70-封装层；80-焊球；90-第二面板级衬底；100-第二介质层；110-粘胶层。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例提供一种芯片封装方法，如图1所示，包括：
S10、如图2所示，在第一面板级衬底10上形成剥离层20，并在剥离层20上各预设区域分别形成重布线层30，位于不同区域的重布线层30之间相互绝缘；其中，在形成所述重布线层30的过程中，还形成第一介质层40。
第一面板级衬底10为面板行业所用的大型衬底，例如1100mm×1300mm的衬底、2200mm×2500mm的衬底等。相对于采用硅衬底，一方面，本发明可降低对硅衬底的使用，降低成本，另一方面，本发明的衬底的尺寸可以更大。
剥离层20首先能通过相应的工艺剥离，此外，由于重布线层30和第一介质层40形成在剥离层20之上，因此，该剥离层20应能在形成重布线层30和第一介质层40的工艺过程中不受影响。基于此，优选的，剥离层20的材料为化学剥离材料或激光剥离材料。
其中，化学剥离材料包括非晶硅、树脂等。激光剥离材料包括氧化物等激光剥离材料。
重布线层30可实现对芯片引线的逐级放大，从而实现芯片引线的纳米量级到微米量级的转化，当芯片引脚达到微米量级时，就可以和其他器件精度对接。
基于重布线层30的作用可知，位于一个预设区域的重布线层30用于与一个芯片电连接。
其中，重布线层30包括多层金属布线层，金属布线层包括金属线；相邻金属布线层之间设置有一层第一介质层40，位于相邻两层金属布线层中的金属线的电连接，通过位于该两层金属布线层之间的一层第一介质层40上的过孔实现。
此处需要说明的是，图2中标识为“30”的两条线分别代表两层金属布线层中的金属线，而标识为“40”部分实质上包括了多层的第一介质层40，相邻层的第一介质层40由一层金属布线层隔离开，在此基础上，图2中并未绘示出位于两层金属布线层之间的第一介质层40上用于使该两层金属布线层中的金属线电连接的过孔。
本领域技术人员应该明白，由于重布线层30需要与芯片50实现电连接，因此，在形成重布线层30和第一介质层40后，在最远离第一面板级衬底10一侧，第一介质层40露出重布线层30的用于与芯片电连接的连接点(也可称为焊盘)。
重布线层30和第一介质层40，可通过薄膜沉积，曝光显影，刻蚀等工艺步骤形成。当然，重布线层30也可通过电铸等工艺形成。
S11、如图3所示，将芯片50以及与芯片50连接的支柱601，通过支柱601上的焊料帽602与形成在预设区域的重布线层30连接。
其中，每个预设区域的重布线层30都与一个芯片50电连接。该芯片50为测试挑选出的合格的芯片50。
芯片50可以包括已经在半导体衬底上制造的半导体器件或集成电路。例如，芯片50可包括包含硅或者其他半导体材料的衬底、位于衬底上的绝缘层、导电部件(包括诸如金属焊盘、插塞、通孔或者导线)以及位于导电部件上方的接触焊盘。
支柱601与芯片50的接触焊盘电连接，当重布线层30与焊料帽602连接后，重布线层30通过焊料帽602、支柱601实现与芯片50的电连接。
考虑到铜材料具有优异的导热及导电性能，因此，优选支柱601为铜柱。
S12、如图4a和图4b所示，对芯片50进行封装，形成封装层70。
封装层70位于每个芯片50的周围，用于保护各个芯片50。
由于环氧树脂模塑料(Epoxy Molding Compound，简称EMC)的密封性较好，塑封容易，因此，封装层70的材料优选为EMC。
其中，EMC是以环氧树脂为基体树脂，以酚醛树脂为固化剂，再加上一些填料，如填充剂、阻燃剂、着色剂、偶联剂等微量组分，在热和固化剂的作用下环氧树脂的环氧基开环与酚醛树脂发生化学反应，产生交联固化作用使之成为热固性塑料。
此处，如图4b所示，优选的，第一介质层40在任意相邻预设区域之间断开。在此基础上，形成封装层70之后，去除第一面板级衬底10之前，所述芯片封装方法还包括：使相邻芯片50之间的封装层70在第一介质层40的断开区域内断开；其中，封装层70包裹第一介质层40。
使相邻芯片50之间的封装层70在第一介质层40的断开区域内断开，例如可通过切割工艺实现。
这样，在后续去除第一面板级衬底10和剥离层20后，便可直接得到一个个封装好的芯片50(如图5b所示)。
需要说明的是，为有效保护芯片50，相邻芯片50应预留出间距，因而，在设置预设区域时，应充分考虑封装时芯片50之间的间距。
S13、如图5a和图5b所示，去除第一面板级衬底10和剥离层20，并在重布线层30一侧形成焊球80。
此处，针对图5b的情况，可通过捡拾机对每个芯片50独立进行焊点焊接，形成焊球80。
当剥离层20的材料为化学剥离材料时，可采用化学方式将剥离层20剥离于封装后的芯片50，相应的第一面板级衬底10也被剥离。当剥离层20的材料为激光剥离材料时，可采用激光照射方式将剥离层20剥离于封装后的芯片50，相应的第一面板级衬底10也被剥离。
焊球80为金属材料，包括锡、铅、铜、银、金、铋等金属或其合金。形成焊球80的方法包括印刷、植球、激光烧结、电镀、化学镀、溅射等方法。
本发明实施例提供一种芯片封装方法，通过采用面板级衬底作为第一面板级衬底10，可在面板领域的产线进行大面积曝光，从而刻蚀形成位于各预设区域的重布线层30，可保证重布线层30中金属线的精度，在此基础上，针对每个预设区域，将一个合格的芯片50与形成在该预设区域的重布线层30电连接，并对芯片50进行封装，可实现大规模的封装，提高了封装效率以及产出效率，而且降低了传统半导体行业封装的成本。此外，由于形成重布线层30的工艺和形成具有支柱601和焊料帽602的芯片50工艺是分开进行的，可使重布线层30以及具有支柱601和焊料帽602的芯片50的工艺复杂度较小，精度不会由于层数太多而降低太多，可保证高的分辨率，因而，本发明还可实现对高端芯片50的封装。
如图6所示，优选的，针对任意芯片50，与其连接的重布线层30超出芯片50的边缘。
其中，在形成重布线层30和第一介质层40时，可使重布线层30和第一介质层40的整体尺寸大于单个芯片50的尺寸。这样，当芯片50通过支柱601上的焊料帽602与重布线层30电连接后，便可使重布线层30延伸至芯片50的边缘之外。
重布线层30延伸至芯片50的边缘之外，形成扇出型封装，可以实现更好的连接性和设计灵活性。
优选的，在上述S11之前，如图7所示，所述封装方法还包括
S14、如图8a、图8b和图8c所示，将多个晶片501固定于第二面板级衬底90上，晶片501包括多个芯片50。
与第一面板级衬底10类似，第二面板级衬底90也为面板行业所用的大型衬底。优选第一面板级衬底10和第二面板级衬底90的尺寸相同。
晶片501可通过粘胶层110固定于第二面板级衬底90上。晶片501例如可以为硅晶片。
其中，为在第二面板级衬底90上尽量多的放置晶片501，可将晶片501的形状制作为规则多边形，以使多个晶片501无缝排布于第二面板级衬底90上。这样，可以提高第二面板级衬底90的利用率，从而进一步的提高产出效率。
S15、如图9所示，在每个芯片50远离第二面板级衬底90一侧形成支柱601以及焊料帽602。
此处，可依次通过曝光、显影、电铸工艺形成支柱601。
即，先通过涂覆光刻胶，经曝光、显影后，露出待形成支柱601的区域，之后采用电铸工艺形成支柱601。通过电铸工艺形成支柱601，可使形成的支柱601精确性更高。
焊料帽602可通过回流的方式形成。
需要说明的是，本发明并不限于仅通过上述工艺形成支柱601，还可以通过其他方式形成支柱601。
S16、如图10所示，形成第二介质层100，第二介质层100填充于支柱601周围露出焊料帽602。
优选的，第一介质层40和第二介质层100的材料相同，这样可以简化工艺，降低成本。第一介质层40和第二介质层100的材料例如可以是聚合物，例如聚酰亚胺(PI)。
S17、如图11所示，通过切割形成各独立的芯片50以及与芯片50连接的支柱601。
当每个晶片501包括N个芯片50，且第二面板级衬底90上设置了M个晶片501时，通过切割后，可得到M×N个独立的芯片50。其中，M、N为正整数。当然，通过切割，位于不同芯片50上的支柱601也相互分开。
为避免切割时损伤第二面板级衬底90，以重复利用第二面板级衬底90，可在本步骤切割之前，先将第二面板级衬底90去除。
其中，可根据粘胶层110的材料选择合适的方法，使粘胶层110与芯片50分离，以去除第二面板级衬底90。
粘胶层110的材料例如可以是双面胶，在此情况下，可通过加热使双面胶降低粘性，以实现其与芯片50的分离，以去除第二面板级衬底90。或者，粘胶层110的材料例如可以是UV粘合胶，在此情况下，可通过UV光照使UV粘合胶降低粘性，以实现其与芯片50的分离，以去除第二面板级衬底90。
本发明实施例，通过先将多个晶片501固定于第一面板级衬底10上，可在面板领域的产线大面积形成支柱601和焊料帽602、以及第二介质层100，因而通过切割后，便可得到更多的芯片50，从而可进一步产出效果。
基于上述，由于封装层70的应力非常大，而钢化玻璃的抗弯曲性，抗冲击性和多层工艺的耐受性较强，因此，优选采用钢化玻璃衬底作为第一面板级衬底10，可避免第一面板级衬底10由于无法承受较大的应力而导致弯曲甚至破裂的问题。
本发明实施例还提供一种芯片封装结构(如图5b和图6所示)，可通过上述任一种的芯片封装方法制备得到。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (11)

1.一种芯片封装方法，其特征在于，包括：
在第一面板级衬底上形成剥离层，并在所述剥离层上各预设区域分别形成重布线层，位于不同区域的所述重布线层之间相互绝缘；在形成所述重布线层的过程中，还形成第一介质层；
将芯片以及与所述芯片连接的支柱，通过所述支柱上的焊料帽与形成在所述预设区域的所述重布线层连接；
对所述芯片进行封装，形成封装层；
去除所述第一面板级衬底和所述剥离层，并在所述重布线层一侧形成焊球。
2.根据权利要求1所述的芯片封装方法，其特征在于，将芯片以及与所述芯片连接的支柱，通过所述支柱上的焊料帽与形成在所述预设区域的所述重布线层连接之前，所述芯片封装方法还包括：
将多个晶片固定于第二面板级衬底上，所述晶片包括多个芯片；
在每个所述芯片远离所述第二面板级衬底一侧形成支柱以及焊料帽；
形成第二介质层，所述第二介质层填充于所述支柱周围露出所述焊料帽；
通过切割形成各独立的所述芯片以及与所述芯片连接的所述支柱。
3.根据权利要求1所述的芯片封装方法，其特征在于，所述第一介质层在任意相邻所述预设区域之间断开；
形成所述封装层之后，去除所述第一面板级衬底之前，所述芯片封装方法还包括：
使相邻所述芯片之间的所述封装层在所述第一介质层的断开区域内断开；其中，所述封装层包裹所述第一介质层。
4.根据权利要求1所述的芯片封装方法，其特征在于，针对任意所述芯片，与其连接的所述重布线层超出所述芯片的边缘。
5.根据权利要求1所述的芯片封装方法，其特征在于，所述剥离层的材料为化学剥离材料或激光剥离材料。
6.根据权利要求2所述的芯片封装方法，其特征在于，形成所述支柱包括：
依次通过曝光、显影、电铸工艺形成所述支柱。
7.根据权利要求2所述的芯片封装方法，其特征在于，所述第一介质层和所述第二介质层的材料相同。
8.根据权利要求2所述的芯片封装方法，其特征在于，所述晶片的形状为规则多边形；
多个所述晶片无缝排布于所述第二面板级衬底上。
9.根据权利要求1-8任一项所述的芯片封装方法，其特征在于，所述支柱为铜柱。
10.根据权利要求1-8任一项所述的芯片封装方法，其特征在于，所述第一面板级衬底为钢化玻璃衬底。
11.一种芯片封装结构，其特征在于，通过权利要求1-10任一项所述的芯片封装方法制备得到。
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