JP4955935B2 - 貫通孔形成方法および半導体装置の製造方法 - Google Patents
貫通孔形成方法および半導体装置の製造方法 Download PDFInfo
- Publication number
- JP4955935B2 JP4955935B2 JP2005141086A JP2005141086A JP4955935B2 JP 4955935 B2 JP4955935 B2 JP 4955935B2 JP 2005141086 A JP2005141086 A JP 2005141086A JP 2005141086 A JP2005141086 A JP 2005141086A JP 4955935 B2 JP4955935 B2 JP 4955935B2
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- Prior art keywords
- hole
- silicon substrate
- crystal plane
- etching
- opening
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
Description
101 {100}シリコン基板
102 能動素子
103 絶縁膜
104 配線部
105 貫通孔
106 絶縁層
107 導電層
108 封止材
109 保護層
110 外部接続電極
111 開口部
Claims (2)
- 表面の結晶方位が{100}結晶面のシリコン基板の表面に、保護膜を形成し、
前記{100}結晶面のシリコン基板の表面の{111}結晶面の境界線に沿って、前記シリコン基板の表面から前記保護膜を除去して前記シリコン基板を露出させた四角形状の開口部を形成し、
前記開口部にレーザを照射して前記シリコン基板を貫通する貫通孔を形成し、
前記貫通孔を、TMAH水溶液を用いたウェットエッチングによって、前記貫通孔の断面形状が四角形状となるように拡大し、
前記貫通孔の断面形状の対角線が、前記開口部の四角形状の一辺の長さと等しくなる前に前記エッチングを終了することを特徴とする貫通孔形成方法。 - 貫通孔により表裏面が電気的に接続されている半導体装置の製造方法において、表面の結晶方位が{100}結晶面のシリコン基板の表面に、保護膜を形成し、
前記{100}結晶面のシリコン基板の表面の{111}結晶面の境界線に沿って、前記シリコン基板の表面から前記保護膜を除去して前記シリコン基板を露出させた四角形状の開口部を形成し、
前記開口部にレーザを照射して前記シリコン基板を貫通する貫通孔を形成し、
前記貫通孔を、TMAH水溶液を用いたウェットエッチングによって、前記貫通孔の断面形状が四角形状となるように拡大し、
前記貫通孔の断面形状の対角線が、前記開口部の四角形状の一辺の長さと等しくなる前に前記エッチングを終了し、
前記貫通孔の内側表面に絶縁層を形成し、前記絶縁層の内側表面に導電層を形成することで、前記シリコン基板の表裏面を電気的に接続することを特徴とする半導体装置の製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005141086A JP4955935B2 (ja) | 2004-05-25 | 2005-05-13 | 貫通孔形成方法および半導体装置の製造方法 |
US11/134,427 US7279776B2 (en) | 2004-05-25 | 2005-05-23 | Method of manufacturing semiconductor device and semiconductor device |
US11/844,822 US7821105B2 (en) | 2004-05-25 | 2007-08-24 | Method of manufacturing semiconductor device and semiconductor device |
US11/844,811 US7713872B2 (en) | 2004-05-25 | 2007-08-24 | Method of manufacturing semiconductor device and semiconductor device |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004154836 | 2004-05-25 | ||
JP2004154836 | 2004-05-25 | ||
JP2005141086A JP4955935B2 (ja) | 2004-05-25 | 2005-05-13 | 貫通孔形成方法および半導体装置の製造方法 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2006013454A JP2006013454A (ja) | 2006-01-12 |
JP2006013454A5 JP2006013454A5 (ja) | 2008-06-26 |
JP4955935B2 true JP4955935B2 (ja) | 2012-06-20 |
Family
ID=35425939
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005141086A Expired - Fee Related JP4955935B2 (ja) | 2004-05-25 | 2005-05-13 | 貫通孔形成方法および半導体装置の製造方法 |
Country Status (2)
Country | Link |
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US (3) | US7279776B2 (ja) |
JP (1) | JP4955935B2 (ja) |
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US8084866B2 (en) | 2003-12-10 | 2011-12-27 | Micron Technology, Inc. | Microelectronic devices and methods for filling vias in microelectronic devices |
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US7767493B2 (en) * | 2005-06-14 | 2010-08-03 | John Trezza | Post & penetration interconnection |
US8456015B2 (en) * | 2005-06-14 | 2013-06-04 | Cufer Asset Ltd. L.L.C. | Triaxial through-chip connection |
US7786592B2 (en) * | 2005-06-14 | 2010-08-31 | John Trezza | Chip capacitive coupling |
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US20060278996A1 (en) * | 2005-06-14 | 2006-12-14 | John Trezza | Active packaging |
US7838997B2 (en) * | 2005-06-14 | 2010-11-23 | John Trezza | Remote chip attachment |
US7687400B2 (en) * | 2005-06-14 | 2010-03-30 | John Trezza | Side stacking apparatus and method |
US7795134B2 (en) | 2005-06-28 | 2010-09-14 | Micron Technology, Inc. | Conductive interconnect structures and formation methods using supercritical fluids |
US7262134B2 (en) | 2005-09-01 | 2007-08-28 | Micron Technology, Inc. | Microfeature workpieces and methods for forming interconnects in microfeature workpieces |
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US20070045120A1 (en) * | 2005-09-01 | 2007-03-01 | Micron Technology, Inc. | Methods and apparatus for filling features in microfeature workpieces |
US8154105B2 (en) * | 2005-09-22 | 2012-04-10 | International Rectifier Corporation | Flip chip semiconductor device and process of its manufacture |
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JP2007258233A (ja) * | 2006-03-20 | 2007-10-04 | Oki Electric Ind Co Ltd | 半導体装置の製造方法、半導体装置および回路基板 |
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-
2005
- 2005-05-13 JP JP2005141086A patent/JP4955935B2/ja not_active Expired - Fee Related
- 2005-05-23 US US11/134,427 patent/US7279776B2/en not_active Expired - Fee Related
-
2007
- 2007-08-24 US US11/844,811 patent/US7713872B2/en not_active Expired - Fee Related
- 2007-08-24 US US11/844,822 patent/US7821105B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US7821105B2 (en) | 2010-10-26 |
US7713872B2 (en) | 2010-05-11 |
US7279776B2 (en) | 2007-10-09 |
JP2006013454A (ja) | 2006-01-12 |
US20050266687A1 (en) | 2005-12-01 |
US20080003817A1 (en) | 2008-01-03 |
US20080001299A1 (en) | 2008-01-03 |
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