JP5330863B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5330863B2 JP5330863B2 JP2009050758A JP2009050758A JP5330863B2 JP 5330863 B2 JP5330863 B2 JP 5330863B2 JP 2009050758 A JP2009050758 A JP 2009050758A JP 2009050758 A JP2009050758 A JP 2009050758A JP 5330863 B2 JP5330863 B2 JP 5330863B2
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Description
Deniz Sabuncuoglu Tezcan、Fabrice Duval、Ole Luhn、Philippe Soussan、Bart Swinnen、"A New Scaled Through Si Via with Polymer Fill for 3D Wafer Level Packaging"、Extended Abstracts of the 2008 International Conference on Solid State Devices and Materials、筑波(日本)、2008年、pp.52-53
以下、本発明の第1の実施形態に係る半導体装置の製造方法について、図1(a)〜図1(h)を参照しながら説明する。尚、本実施形態で使用している、材料、数値等は例示であって、それらに本発明が限定されることはない。また、本発明の技術的思想の範囲を逸脱しない範囲で本実施形態を適宜変更することは可能であり、さらに、本実施形態と他の実施形態との組み合わせなども可能である。
以下、本発明の第1の実施形態の第1変形例に係る半導体装置の製造方法について、図3(a)〜図3(h)を参照しながら説明する。尚、本変形例で使用している、材料、数値等は例示であって、それらに本発明が限定されることはない。また、本発明の技術的思想の範囲を逸脱しない範囲で本変形例を適宜変更することは可能であり、さらに、本変形例と他の実施形態や変形例との組み合わせなども可能である。また、本変形例の図3(a)、図3(b)、図3(g)及び図3(h)に示す工程はそれぞれ、第1の実施形態の図1(a)、図1(b)、図1(g)及び図1(h)に示す工程と同様であるので、説明を省略する。
以下、本発明の第1の実施形態の第2変形例に係る半導体装置の製造方法について、図5(a)〜図5(h)を参照しながら説明する。尚、本変形例で使用している、材料、数値等は例示であって、それらに本発明が限定されることはない。また、本発明の技術的思想の範囲を逸脱しない範囲で本変形例を適宜変更することは可能であり、さらに、本変形例と他の実施形態や変形例との組み合わせなども可能である。また、本変形例の図5(a)、図5(b)及び図5(d)〜図5(h)に示す工程はそれぞれ、第1の実施形態の第1変形例の図3(a)、図3(b)及び図3(d)〜図3(h)に示す工程と同様であるので、説明を省略する。
以下、本発明の第1の実施形態の第3変形例に係る半導体装置の製造方法について、図7(a)〜図7(g)を参照しながら説明する。尚、本変形例で使用している、材料、数値等は例示であって、それらに本発明が限定されることはない。また、本発明の技術的思想の範囲を逸脱しない範囲で本変形例を適宜変更することは可能であり、さらに、本変形例と他の実施形態や変形例との組み合わせなども可能である。また、本変形例の図7(b)〜図7(g)に示す工程はそれぞれ、第1の実施形態の第2変形例の図5(c)〜図5(h)に示す工程と同様であるので、説明を省略する。
以下、本発明の第2の実施形態に係る半導体装置、具体的には、前述の第1の実施形態(各変形例を含む:以下同じ)に係る半導体装置を複数積層した構造体について、図面を参照しながら説明する。
2 ワックス
3 金属膜
4 第1絶縁膜
5 シリコンデバイスウェハ
6 第2絶縁膜
7a 第3絶縁膜
7b ダミープラグ
7c ビア被覆膜
8a 第4絶縁膜
8b サイドウォール
9 バリアメタル膜
10 導電膜
21 ビアホール
22 貫通ビア
23 配線
31 レジスト膜
31A レジストパターン
51 半導体基板
52a 第1面
52b 第2面
53 不純物領域
54 ゲート絶縁膜
55 ゲート電極
56 素子分離
57 コンタクト
58a 第1配線
58b 第2配線
59a 第1ビア
59b 第2ビア
60a 第1層間絶縁膜
60b 第2層間絶縁膜
60c 第3層間絶縁膜
61 電極パッド
62 接着層
63 ビア被覆膜
64 貫通ビア
65 絶縁性保護膜
71A、71B、71C、71D 半導体基板
72A、72B、72C、72D ビア被覆膜となる絶縁膜
73A、73B、73C、73D 電極パッド
74A、74B、74C、74D 貫通ビア
75A、75B、75C、75D 配線
76A、76B、76C、76D バンプ
77 半導体チップ
78 バンプ
79 封止樹脂
81 ロジック回路を有する半導体チップ
82 メモリ素子を有する半導体チップ
83 撮像素子を有する半導体チップ
91 プリント配線基板
92 配線構造
Claims (7)
- 素子形成面となる第1面及び前記第1面とは反対側の第2面を有する半導体基板の前記第2面上に絶縁性の保護膜を形成する工程(a)と、
前記保護膜及び前記半導体基板を貫通するようにビアホールを形成する工程(b)と、
前記ビアホール内に絶縁性のビア被覆材料を埋め込む工程(c)と、
前記保護膜中に位置する部分の前記ビアホール内に埋め込まれている前記ビア被覆材料を除去する工程(d)と、
前記ビアホール内に残存する前記ビア被覆材料の上に絶縁膜を形成する工程(e)と、
前記保護膜中に位置する部分の前記ビアホールの内壁を覆う部分の前記絶縁膜を残して前記絶縁膜を除去する工程(f)と、
前記保護膜中に位置する部分の前記ビアホールの内壁上に残存する前記絶縁膜をマスクとして、前記ビアホールの内壁を覆う部分の前記ビア被覆材料をビア被覆膜として残して前記ビア被覆材料を除去する工程(g)と、
前記ビア被覆膜が残存する前記ビアホール内に導電膜を埋め込むことにより、前記半導体基板を貫通する貫通ビアを形成する工程(h)とを備えていることを特徴とする半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記工程(d)において、前記ビア被覆材料の前記第2面側の端が、前記半導体基板の前記第2面と同じ平面内に位置するまで、前記ビア被覆材料を除去することを特徴とする半導体装置の製造方法。 - 請求項1又は2に記載の半導体装置の製造方法において、
前記工程(e)において、前記絶縁膜をCVD法により形成することを特徴とする半導体装置の製造方法。 - 請求項1〜3のいずれか1項に記載の半導体装置の製造方法において、
前記絶縁膜は、窒化シリコン膜、炭化シリコン膜又はシリコン酸化膜からなることを特徴とする半導体装置の製造方法。 - 請求項1〜4のいずれか1項に記載の半導体装置の製造方法において、
前記保護膜は窒化シリコンからなることを特徴とする半導体装置の製造方法。 - 請求項1〜5のいずれか1項に記載の半導体装置の製造方法において、
前記ビア被覆膜は絶縁性ポリマーからなることを特徴とする半導体装置の製造方法。 - 請求項1〜6のいずれか1項に記載の半導体装置の製造方法において、
前記ビア被覆材料を除去する工程(g)では、前記ビア被覆材料をエッチングで除去し、
前記エッチングにおいて、前記ビア被覆材料に対して前記絶縁膜のエッチング選択比が高いことを特徴とする半導体装置の製造方法。
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Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7626269B2 (en) * | 2006-07-06 | 2009-12-01 | Micron Technology, Inc. | Semiconductor constructions and assemblies, and electronic systems |
US8569876B2 (en) | 2006-11-22 | 2013-10-29 | Tessera, Inc. | Packaged semiconductor chips with array |
US9640437B2 (en) | 2010-07-23 | 2017-05-02 | Tessera, Inc. | Methods of forming semiconductor elements using micro-abrasive particle stream |
US8598695B2 (en) | 2010-07-23 | 2013-12-03 | Tessera, Inc. | Active chip on carrier or laminated chip having microelectronic element embedded therein |
US8847380B2 (en) | 2010-09-17 | 2014-09-30 | Tessera, Inc. | Staged via formation from both sides of chip |
US8587126B2 (en) * | 2010-12-02 | 2013-11-19 | Tessera, Inc. | Stacked microelectronic assembly with TSVs formed in stages with plural active chips |
US8736066B2 (en) | 2010-12-02 | 2014-05-27 | Tessera, Inc. | Stacked microelectronic assemby with TSVS formed in stages and carrier above chip |
WO2012077280A1 (ja) * | 2010-12-09 | 2012-06-14 | パナソニック株式会社 | 三次元集積回路の設計支援装置及び設計支援方法 |
US8742564B2 (en) * | 2011-01-17 | 2014-06-03 | Bai-Yao Lou | Chip package and method for forming the same |
JP5958732B2 (ja) * | 2011-03-11 | 2016-08-02 | ソニー株式会社 | 半導体装置、製造方法、および電子機器 |
JP2012195514A (ja) | 2011-03-17 | 2012-10-11 | Seiko Epson Corp | 素子付き基板、赤外線センサー、および貫通電極形成方法 |
WO2012142592A1 (en) * | 2011-04-14 | 2012-10-18 | Georgia Tech Research Corporation | Through package via structures in panel-based silicon substrates and methods of making the same |
KR101828490B1 (ko) | 2011-08-30 | 2018-02-12 | 삼성전자주식회사 | 관통전극을 갖는 반도체 소자 및 그 제조방법 |
US20130134600A1 (en) * | 2011-11-28 | 2013-05-30 | Advanced Semiconductor Engineering, Inc. | Semiconductor device and method for manufacturing the same |
CN103219302B (zh) * | 2012-01-19 | 2016-01-20 | 欣兴电子股份有限公司 | 穿孔中介板 |
KR101845529B1 (ko) | 2012-02-02 | 2018-04-05 | 삼성전자주식회사 | 관통전극을 갖는 반도체 소자 및 그 제조방법 |
US10020244B2 (en) * | 2012-03-27 | 2018-07-10 | Cree, Inc. | Polymer via plugs with high thermal integrity |
US8629524B2 (en) * | 2012-04-27 | 2014-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Apparatus for vertically integrated backside illuminated image sensors |
KR101934864B1 (ko) * | 2012-05-30 | 2019-03-18 | 삼성전자주식회사 | 관통 실리콘 비아 구조물 및 그 제조 방법, 이를 포함하는 이미지 센서 및 그 제조 방법 |
US9257384B2 (en) * | 2012-06-05 | 2016-02-09 | Stats Chippac Ltd. | Integrated circuit packaging system with substrate and method of manufacture thereof |
KR101932660B1 (ko) | 2012-09-12 | 2018-12-26 | 삼성전자 주식회사 | Tsv 구조를 구비한 집적회로 소자 및 그 제조 방법 |
JP2014107304A (ja) | 2012-11-22 | 2014-06-09 | Renesas Electronics Corp | 半導体装置およびその製造方法 |
KR102299781B1 (ko) | 2014-07-21 | 2021-09-08 | 삼성전자주식회사 | 반도체 장치 및 이의 제조 방법 |
CN104201115A (zh) * | 2014-09-12 | 2014-12-10 | 苏州晶方半导体科技股份有限公司 | 晶圆级指纹识别芯片封装结构及封装方法 |
US9633930B2 (en) * | 2014-11-26 | 2017-04-25 | Kookmin University Industry Academy Cooperation Foundation | Method of forming through-hole in silicon substrate, method of forming electrical connection element penetrating silicon substrate and semiconductor device manufactured thereby |
US11329077B2 (en) | 2017-03-31 | 2022-05-10 | Sony Semiconductor Solutions Corporation | Semiconductor device with a through electrode reception part wider than a through electrode, solid-state imaging device, and electronic equipment |
JP6994257B2 (ja) * | 2018-10-31 | 2022-02-21 | 国立大学法人茨城大学 | 配線構造 |
JP7193731B2 (ja) * | 2019-03-29 | 2022-12-21 | 東京エレクトロン株式会社 | エッチング方法及びエッチング装置 |
US11031348B2 (en) * | 2019-07-24 | 2021-06-08 | Nanya Technology Corporation | Semiconductor structure |
CN111081632A (zh) * | 2019-12-12 | 2020-04-28 | 联合微电子中心有限责任公司 | 一种减小热应力的硅通孔结构及其制造方法 |
WO2023166843A1 (ja) * | 2022-03-01 | 2023-09-07 | ソニーセミコンダクタソリューションズ株式会社 | 半導体装置及び電子機器 |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5493096A (en) * | 1994-05-10 | 1996-02-20 | Grumman Aerospace Corporation | Thin substrate micro-via interconnect |
JP2570617B2 (ja) * | 1994-05-13 | 1997-01-08 | 日本電気株式会社 | 多層配線セラミック基板のビア構造及びその製造方法 |
JPH09184080A (ja) * | 1995-12-27 | 1997-07-15 | Vacuum Metallurgical Co Ltd | 超微粒子による薄膜形成方法、およびその薄膜形成装置 |
JPH09205144A (ja) * | 1996-01-25 | 1997-08-05 | Sony Corp | 多層配線構造を有する半導体装置及びその製造方法 |
JP2000195861A (ja) * | 1998-12-25 | 2000-07-14 | Texas Instr Japan Ltd | 半導体装置およびその製造方法 |
JP2002094082A (ja) * | 2000-07-11 | 2002-03-29 | Seiko Epson Corp | 光素子及びその製造方法並びに電子機器 |
JP4053257B2 (ja) * | 2001-06-14 | 2008-02-27 | 新光電気工業株式会社 | 半導体装置の製造方法 |
JP2003289073A (ja) * | 2002-01-22 | 2003-10-10 | Canon Inc | 半導体装置および半導体装置の製造方法 |
US6826830B2 (en) * | 2002-02-05 | 2004-12-07 | International Business Machines Corporation | Multi-layered interconnect structure using liquid crystalline polymer dielectric |
US6790775B2 (en) * | 2002-10-31 | 2004-09-14 | Hewlett-Packard Development Company, L.P. | Method of forming a through-substrate interconnect |
JP4072677B2 (ja) * | 2003-01-15 | 2008-04-09 | セイコーエプソン株式会社 | 半導体チップ、半導体ウエハ、半導体装置及びその製造方法、回路基板並びに電子機器 |
US6937120B2 (en) * | 2003-04-02 | 2005-08-30 | Harris Corporation | Conductor-within-a-via microwave launch |
KR100651414B1 (ko) * | 2004-02-13 | 2006-11-29 | 삼성전기주식회사 | 동축 비아홀을 구비한 인쇄회로기판 |
JP4955935B2 (ja) * | 2004-05-25 | 2012-06-20 | キヤノン株式会社 | 貫通孔形成方法および半導体装置の製造方法 |
JP4365750B2 (ja) | 2004-08-20 | 2009-11-18 | ローム株式会社 | 半導体チップの製造方法、および半導体装置の製造方法 |
US7491582B2 (en) * | 2004-08-31 | 2009-02-17 | Seiko Epson Corporation | Method for manufacturing semiconductor device and semiconductor device |
US7300857B2 (en) * | 2004-09-02 | 2007-11-27 | Micron Technology, Inc. | Through-wafer interconnects for photoimager and memory wafers |
JP2006253631A (ja) | 2005-02-14 | 2006-09-21 | Fujitsu Ltd | 半導体装置及びその製造方法、キャパシタ構造体及びその製造方法 |
JP2007281289A (ja) * | 2006-04-10 | 2007-10-25 | Fujikura Ltd | 電子部品及びその製造方法 |
US7629541B2 (en) * | 2006-06-19 | 2009-12-08 | Endicott Interconnect Technologies, Inc. | High speed interposer |
JP2007005838A (ja) | 2006-10-12 | 2007-01-11 | Fujitsu Ltd | 半導体装置の支持体 |
US20080136038A1 (en) * | 2006-12-06 | 2008-06-12 | Sergey Savastiouk | Integrated circuits with conductive features in through holes passing through other conductive features and through a semiconductor substrate |
JP2008300718A (ja) * | 2007-06-01 | 2008-12-11 | Toshiba Corp | 半導体装置および半導体装置の製造方法 |
US7863180B2 (en) * | 2008-05-06 | 2011-01-04 | International Business Machines Corporation | Through substrate via including variable sidewall profile |
US7973416B2 (en) * | 2008-05-12 | 2011-07-05 | Texas Instruments Incorporated | Thru silicon enabled die stacking scheme |
US7968460B2 (en) * | 2008-06-19 | 2011-06-28 | Micron Technology, Inc. | Semiconductor with through-substrate interconnect |
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- 2009-03-04 JP JP2009050758A patent/JP5330863B2/ja active Active
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