CN107026090A - 半导体器件的制造方法 - Google Patents

半导体器件的制造方法 Download PDF

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Publication number
CN107026090A
CN107026090A CN201611195926.6A CN201611195926A CN107026090A CN 107026090 A CN107026090 A CN 107026090A CN 201611195926 A CN201611195926 A CN 201611195926A CN 107026090 A CN107026090 A CN 107026090A
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China
Prior art keywords
contact pad
semiconductor devices
passivating
passivating material
certain embodiments
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CN201611195926.6A
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English (en)
Inventor
张贵松
蔡念宗
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN107026090A publication Critical patent/CN107026090A/zh
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Abstract

本发明公开了半导体器件及其制造方法。在一些实施例中，该方法包括在半导体器件上方形成接触焊盘。在接触焊盘上方形成钝化材料。所述钝化材料的材料类型和厚度允许穿过所述钝化材料与所述接触焊盘建立电连接。

Description

半导体器件的制造方法
技术领域
本发明的实施例涉及半导体器件的制造方法。
背景技术
半导体器件用于诸如个人电脑、手机、数码相机和其它电子设备的各种电子应用中。通常通过在半导体衬底上方依次沉积绝缘或介电层、导电层和半导体材料层以及使用光刻图案化各个材料层以在各个材料层上形成电路组件和元件来制造半导体器件。
通常在单个半导体晶圆上制造数十个或数百个集成电路管芯。通过沿着划线锯切集成电路管芯来分割单独的集成电路管芯。之后，以多管芯模块或其它类型的封装分别封装单独的管芯。
在一些应用中，接触焊盘用于制成至集成电路管芯的电连接。接触焊盘形成在集成电路管芯上并且连接至下面的电路。可以通过布线接合、连接器或其它类型的器件制成至集成电路管芯的接触焊盘的电连接。在一些应用中，用于集成电路管芯的封装件也可以包括用于制成至封装的集成电路管芯的电连接的接触焊盘。
发明内容
本发明的实施例提供了.一种制造半导体器件的方法，包括：在半导体器件上方形成接触焊盘；以及在所述接触焊盘上方形成钝化材料，其中，所述钝化材料包括材料的厚度和类型，从而使得制成穿过所述钝化材料至所述接触焊盘的电连接。
本发明的另一实施例提供了一种制造半导体器件的方法，所述方法包括：在衬底上方形成导电材料；在所述导电材料上方形成钝化材料，其中，所述钝化材料包括材料的厚度和类型，从而使得制成穿过所述钝化材料至所述导电材料的电连接；以及图案化所述钝化材料和所述导电材料以由所述导电材料形成接触焊盘。
本发明的又一实施例提供了一种半导体器件，包括：衬底；接触焊盘，设置在所述衬底上方；钝化材料，设置在所述接触焊盘上方；以及布线、连接器或接触件，穿过所述钝化材料耦合至所述接触焊盘。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图8是根据本发明的一些实施例的示出形成接触焊盘的方法的处于制造的各个阶段的半导体器件的截面图。
图9是根据一些实施例的示出穿过设置在接触焊盘上的钝化材料耦合至接触焊盘的布线的图8中所示的半导体器件的截面图。
图10是图9中示出的一些实施例的顶视图。
图11至图13是根据一些实施例的示出包括具有设置在其上的钝化材料的接触焊盘的半导体器件的截面图。
图14示出了包括具有设置在其上的钝化材料的接触焊盘的封装的半导体器件的截面图，其中，在一些实施例中，连接器或接触件耦合至接触焊盘。
图15至图21是根据本发明的一些实施例的示出形成接触焊盘的方法的处于制造的各个阶段的半导体器件的截面图。
图22是根据本发明的一些实施例的示出制造半导体器件的方法的流程图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
本发明公开了半导体器件及其制造方法。在半导体器件的接触焊盘上方形成钝化材料，这有利地防止或减少了接触焊盘的侵蚀，并且保持了接触焊盘的粘合性。钝化材料应足够薄，使得可以制成穿过钝化材料至接触焊盘的电连接。公开了利用接触焊盘(可以用于将一个衬底附接至另一衬底的目的)的一些实施例，其中，该衬底可以包括管芯、印刷电路板(PCB)、封装衬底等，从而允许管芯至管芯、管芯至PCB、管芯至衬底、管芯至封装衬底等类型的电连接。贯穿各个视图和示出的实施例，相同的参考标号用于指定相同的元件。
图1至图8是根据本发明的一些实施例的示出形成接触焊盘120(见图4)的方法的处于制造的各个阶段的半导体器件100的截面图。在一些附图中示出了一个接触焊盘120；然而，根据一些实施例，在半导体器件100的表面上方形成多个接触焊盘120。
首先参照图1，在一些实施例中，提供了衬底102。在一些实施例中，衬底102包括具有在其内或其上形成的电路的集成电路管芯(未在图1中示出：见图11、图12和图14中示出的集成电路管芯130)。在一些实施例中，如其它实例，衬底102包括封装的集成电路管芯、用于集成电路管芯的封装件、封装衬底或PCB。例如，在一些实施例中，衬底102也可以包括微传感器、微致动器或微电子机械系统(MEMS)器件。例如，在一些实施例中，衬底102可以包括两个或更多晶圆的堆叠件(诸如接合的晶圆堆叠件)。例如，衬底102也可以包括其它类型的器件，其中，将在衬底102上方形成接触焊盘以制成至部分衬底102的电连接。
在一些实施例中，其中，衬底102包括集成电路管芯，例如，衬底102可以包括掺杂或未掺杂的块状硅或绝缘体上半导体(SOI)衬底的有源层。集成电路管芯的衬底102的电路可以是适用于特定应用的任何类型的电路。集成电路管芯可以包括逻辑、存储器、处理器或其它类型的器件。如其它实例，在集成电路管芯的衬底内或上形成的电路可以包括互连的各个N-型金属氧化物半导体(NMOS)和/或P-型金属氧化物半导体(PMOS)器件(诸如晶体管、电容器、电阻器、二极管、光电二极管、保险丝等)以实施一个或多个功能。该功能可以包括存储器结构、逻辑结构、处理结构、传感器、放大器、功率分配、输入/输出电路等。本领域普通技术人员将明白，以上提供的实施例用于说明的目的以进一步解释一些示出的实施例的应用并且不意味着以任何方式限制本发明。可以使用适用于给定应用的其它电路。例如，通常通过在半导体晶圆上形成多个集成电路管芯、并且之后沿着划线(未示出)分割单独的集成电路管芯来制造在衬底102内或上形成的集成电路管芯。
在一些实施例中，衬底102包括接近其顶面设置的互连结构(未在图1中示出：见图11、图12和图14中示出的互连结构132)。该互连结构可以包括形成在一个或多个绝缘材料层中的多个导线、导电通孔和其它导电部件。根据一些实施例，在接近衬底102的顶面设置的互连结构上方形成包括多个接触焊盘的顶金属层(见图4中所示的接触焊盘120)。互连结构可以包括设置在衬底102的最上绝缘材料层中的通孔、导线或导电部件(未示出)(适应于制成至接触焊盘120的电接触和电连接)。例如，通孔、导线或导电部件通过互连结构的其它部分耦合至衬底102内的电路。
同样如图1中示出的，在衬底102上方形成绝缘材料104。在一些实施例中，绝缘材料104包括金属间钝化层。在一些实施例中，绝缘材料104包括具有约0.1μm至约10μm的厚度的SiO2。例如，可以通过使用化学汽相沉积(CVD)或物理汽相沉积(PVD)形成绝缘材料104。绝缘材料104也可以包括其它材料、尺寸和形成方法。
在位于衬底102上方的绝缘材料104上方形成导电材料106。例如，在一些实施例中，导电材料106包括半导体器件100的顶金属层。例如，导电材料106可以包括在图1中所示的视图中的半导体器件100的最上导电材料层。在一些实施例中，导电材料106包括通过诸如PVD的方法形成的AlCu、AlSi、Al、Cu或它们的组合或多层。在一些实施例中，导电材料106包括约0.1μm至约10μm的厚度。在一些实施例中，其中，导电材料106包括AlCu或AlSi，例如，导电材料106分别可以包括约5％或更少的Cu或Si。导电材料106也可以包括其它材料、材料的其它百分比、尺寸和形成方法。
在一些实施例中，首先，图案化导电材料106，并且其次，在图案化的导电材料106上方形成钝化材料110(这将参照图15至图21中示出的一些实施例在此处进一步描述)。在一些实施例中，如图1至图4示出的，首先在导电材料上方形成钝化材料110，并且其次，同时图案化钝化材料110和导电材料106。
再次参照图1，在位于衬底102上方的导电材料106上方形成钝化材料110。例如，在一些实施例中，钝化材料110包括设置在导电材料106(包括顶金属层)上方的金属钝化层。在一些实施例中，钝化材料110包括材料的厚度和类型，从而使得可以制成穿过钝化材料110至由导电材料106形成的接触焊盘120(见图4和图9)的电连接。例如，在一些实施例中，钝化材料110包括适应于防止或减少由导电材料106形成的接触焊盘120的侵蚀的材料。
在一些实施例中，钝化层110包括Ti、TiN、TaN、Al2O3、Ta2O3、HfO2、TiO2、和/或它们的组合或多层。在一些实施例中，使用PVD或CVD形成钝化材料110。在一些实施例中，钝化材料110包括约1400埃或更小的厚度。例如，在一些实施例中，钝化材料110可以包括约10埃至约1400埃的厚度。例如，在一些实施例中，钝化材料110可以包括约50埃至约1400埃的厚度。例如，在一些实施例中，钝化材料110可以包括约200埃至约300埃的厚度。钝化材料110也可以包括其它材料、形成方法和尺寸。
之后，使用光刻工艺图案化钝化材料110和导电材料106。例如，如图2中示出的，可以在钝化材料110上方沉积光刻胶层112。之后，如图3示出的，用用于多个接触焊盘的期望的图案图案化光刻胶层112。例如，光刻胶层112可以暴露于光或能量(通过其上具有期望的图案的光刻掩模传送的或从其上具有期望的图案的光刻掩模反射的)。显影光刻胶层112并且使用灰化和/或蚀刻工艺去除光刻胶层112的曝光的(或未曝光的，根据光刻胶层112是包括正性感光材料还是包括负性感光材料)部分。
之后，如图4所示，在用于钝化材料110和导电材料106的蚀刻工艺期间，光刻胶层112用作蚀刻掩模。该蚀刻工艺包括适用于蚀刻钝化材料110和导电材料106的材料的化学物质。例如，该蚀刻工艺可以包括使用Cl2、BCl3、SiCl4、或HBr的干等离子蚀刻工艺或使用HNO3、HCl、NaOH或KOH的湿化学蚀刻工艺。该蚀刻工艺也可以包括其它方法和其它化学物质和/或化学化合物。之后，同样如图4所示，使用合适的蚀刻工艺和/或清洗工艺去除光刻胶层112。
由图案化的导电材料106形成接触焊盘120。例如，在一些实施例中，接触焊盘120包括约30μm至约10μm的宽度。接触焊盘120也可以包括其它尺寸。在一些实施例的顶视图中，接触焊盘120可以包括正方形或矩形形状(例如，见图10的顶视图中所示的接触焊盘120)。在顶视图中，接触焊盘120也可以包括圆形、椭圆形、多边形或其他形状。在一些实施例中，接触焊盘120包括布线接合焊盘。例如，在一些实施例中，接触焊盘120包括顶金属布线接合焊盘。在一些实施例中，接触焊盘120也可以包括半导体器件100的其它类型的焊盘或导电定位区域。
钝化材料110设置在接触焊盘120的顶面上方。在一些实施例中，钝化材料110包括与接触焊盘120基本相同的形状(例如，长度和宽度)。
如图5所示，在接触焊盘120、钝化材料110和绝缘材料104的暴露部分上方形成绝缘材料122。在一些实施例中，绝缘材料122包括顶金属钝化层。绝缘材料122包括通过PVD或CVD沉积的氧化硅或氮化硅。在一些实施例中，绝缘材料122可以具有约0.1μm至约10μm的厚度。绝缘材料122也可以包括其它材料、形成方法和尺寸。例如，在一些实施例中，绝缘材料122可以基本共形于半导体器件100的形貌。在一些实施例中，绝缘材料122可以不共形于半导体器件100的形貌。
如图6所示，在绝缘材料122上方形成光刻胶层112’。使用具有用于接触焊盘120上方的绝缘材料122中的开口的图案的光刻图案化光刻胶层112’。例如，光刻胶层112’的图案化可以包括与此处描述的用于图2和图3所示的光刻胶层112的图案化类似的工艺。图7中示出了图案化的光刻胶层112’。
之后，如图8所示，将图案化的光刻胶层112’用作蚀刻掩模以图案化绝缘材料122。例如，在一些实施例中，用于绝缘材料122的蚀刻工艺可以包括使用CF4、C2F6或CCl2F2的干等离子体蚀刻工艺或使用稀释的HF或缓冲的HF的湿化学蚀刻工艺。在一些实施例中，用于绝缘材料122的蚀刻工艺也可以包括其它化学物质和/或化学化合物。之后，同样如图8所示，使用合适的蚀刻工艺和/或清洗工艺去除图案化的光刻胶层112’。
绝缘材料122的蚀刻工艺在部分接触焊盘120上方的绝缘材料122中形成了开口。在一些实施例中，绝缘材料122中的开口可以包括与接触焊盘120基本相同的形状(诸如正方形、矩形或其它的形状)。绝缘材料122中的开口也可以包括与接触焊盘120不同的形状。在一些实施例中，绝缘材料122中的开口小于接触焊盘120的宽度。例如，在一些实施例中，绝缘材料122中的开口(位于接触焊盘120的边缘上方并且沿着接触焊盘120的边缘)可以小于接触焊盘120的宽度至少几μm。
因此，在一些实施例中，如图8示出的，绝缘材料122设置在接近接触焊盘120的衬底102上方。在一些实施例中，部分绝缘材料122设置在接触焊盘120的边缘上方。在一些实施例中，接触焊盘120包括第一宽度，并且接近接触焊盘120的绝缘材料122中的开口包括第二宽度，其中，第二宽度小于第一宽度。
在设置在接触焊盘120上方的钝化材料110上方的绝缘材料122中制成开口之后，可以实施半导体器件的进一步处理。例如，可以实施后段制程(BEOL)工艺(诸如形成、图案化以及处理额外的材料层(未示出))。也可以实施应力测试和其它的测试。如另一实例，半导体器件100可以分割成单独的集成电路管芯或封装件并且运至终端用户。在半导体器件100的随后的处理期间，留下的钝化材料110保持在接触焊盘120的表面上，有利地防止和/或减少了接触焊盘120的侵蚀，并且也保存了接触焊盘120的粘合性。
在一些实施例中，在完成半导体器件100的制造工艺(没有从半导体器件100去除钝化材料110或它们的部分并且没有从接触焊盘120上方去除钝化材料110或它们的部分)之后，制成穿过钝化材料110至接触焊盘120的电连接。可以制成的电连接的一些实例为在接触焊盘120上布线接合布线124(见图9)或形成连接器150或接触件150’(见图21)。例如，根据一些实施例，实现根据参照图1至图8的此处描述的方法制造的半导体器件100的方法包括制成穿过钝化材料110至接触焊盘120的电连接而没有从接触焊盘120上方去除钝化材料110或它们的部分。
例如，图9是根据一些实施例的示出穿过钝化材料110耦合至接触焊盘120的布线124的图8中所示的半导体器件100的截面图。布线124耦合至接触焊盘120(包括接合区域126中的导电材料106)的顶面。在一些实施例中，接合区域126的宽度小于绝缘材料122中的开口的宽度。在一些实施例中，接合区域126的宽度也可以与绝缘材料122中的开口的宽度基本相同。在一些实施例中，布线124可以包括导电材料(诸如Au、Cu、Al、Ag、其它金属或它们的合金或它们的组合)。例如，布线124可以包括约15μm至约几百μm的直径。布线124也可以包括其它材料和尺寸。
钝化材料110有利地包括用于布线124的材料的类型和足够的厚度以穿过钝化材料110电耦合和机械耦合至接触焊盘120。例如，在一些实施例中，在处理期间保留在半导体器件100上的钝化材料110保护接触焊盘120免受各个制造和封装工艺步骤以及运输期间的损坏和侵蚀。此外，在布线接合工艺之后，设置在接合区域126周围的部分钝化材料110持续地保护接触焊盘120免受侵蚀。
使用布线接合工艺将布线124穿过钝化材料110布线接合至接触焊盘120。在一些实施例中，布线接合工艺可以包括球接合工艺、楔形接合工艺或兼容接合工艺。在一些实施例中，热超声球接合工艺可以用于布线接合工艺，该工艺利用了同时具有热和超声能量的法向接合力以形成布线124至接触焊盘120的接合。例如，法向力和超声能功率引起了钝化材料110中的破裂和/或布线124的材料穿过钝化材料110扩散至接触焊盘120。可以选择布线接合工艺的其它因素和参数以获得钝化材料110中的破裂并且形成布线接合。
图9也示出了设置在接触焊盘120下面的绝缘材料104中的导电部件128。在图9中，导电部件128以虚位(例如，虚线)示出。导电部件128可以包括穿过绝缘材料104的通孔或导电材料的其它部分(适应于提供和/或制成从接触焊盘120至在衬底102内或上方形成的电路的电连接)。例如，导电部件128可以电耦合至衬底102内的下面的互连结构，并且互连结构可以耦合至在衬底102内或上方形成的电路。
在如图1所示的绝缘材料104上方形成导电材料106之前，在绝缘材料104中形成导电部件128。可以通过在衬底102上方形成导电材料层并且使用光刻图案化导电材料层，使用消减蚀刻工艺形成导电部件128来形成导电部件128。之后，在导电部件128周围形成绝缘材料104。也可以通过在衬底102上方形成绝缘材料104，并且使用光刻工艺图案化绝缘材料104，使用镶嵌工艺形成导电部件128。之后，在绝缘材料104内形成导电材料，形成导电部件128。例如，镀工艺也可以用于在绝缘材料104中形成导电部件128。也可以使用其它方法形成导电部件128。
图10是图9中示出的一些实施例的顶视图。所示为设置在衬底102上方的多个接触焊盘120。钝化材料110设置在多个接触焊盘120的每个上方。布线124穿过钝化材料110布线接合至每个接触焊盘120。同样地，连接器150或接触件150’(见图21)可以穿过钝化材料110耦合至多个接触焊盘120的每个。例如，根据半导体器件100的输入/输出信号和/或功率和接地信号的应用和数量，可以有形成在半导体器件100的表面上的若干接触焊盘120(例如，十个或更少、十个或更多、数十个或数百个接触焊盘120)。图10中示出了沿着半导体器件100的一个边缘或侧设置的一列接触焊盘120。例如，在一些实施例中，多个接触焊盘120也可以沿着半导体器件100的一个或多个边缘布置为单列或多列。
图1至图10所示的一些实施例的额外优势在于，钝化材料110在用于形成接触焊盘120的蚀刻工艺期间设置在导电材料106的顶面上。因此，钝化材料110防止了接触焊盘120的顶面暴露于蚀刻化学物质(用于接触焊盘120的蚀刻工艺中)，并且因此防止了蚀刻工艺期间的接触焊盘120的侵蚀。例如，在一些实施例中，在用于半导体器件100的其它工艺期间，钝化材料110也保护了接触焊盘120以免接触其它化学化学品或蚀刻化学物质。
在一些实施例中，其中，使用布线接合制成穿过钝化材料110至接触焊盘120的电连接，可以制成至另一半导体器件134或物体的布线124的相对端。例如，如图11至图13所示，图9中示出的半导体器件100可以包括第一半导体器件100，并且图9中所示的布线124的相对端可以耦合至设置在第二半导体器件134上的接触焊盘。注意，为了简化附图，未在图11至图14中示出钝化材料110。
第二半导体器件134可以包括集成电路管芯、封装的集成电路管芯、用于集成电路管芯的封装件、封装衬底、PCB或其它类型的器件。例如，在一些实施例中，其中，制成至接触焊盘120的电连接包括将布线124穿过钝化材料110布线接合至第一半导体器件100的接触焊盘120，制成电连接可以包括将布线124的第一端耦合至接触焊盘120，并且布线124的第二端可以耦合至第二半导体器件134的接触焊盘。
在一些实施例中，第二半导体器件134也可以具有接触焊盘120(具有在其上形成的此处描述的钝化材料110)，并且可以制成穿过钝化材料110至接触焊盘120的电连接而不需要额外的工艺步骤去除钝化材料110。在一些实施例中，第二半导体器件134可以不具有接触焊盘120(具有在其上形成的此处描述的钝化材料110)。在一些实施例中，图11至图13中示出的第二半导体器件134可以具有接触焊盘120(具有在其上形成的此处描述的钝化材料110)，并且如另一实例，第一半导体器件100可以不具有接触焊盘120(具有在其上形成的此处描述的钝化材料110)。
在图11中，第一半导体器件100包括集成电路管芯130(包括在其上形成的互连结构132)。互连结构132包括在一个或多个绝缘材料层中形成的多个导线和通孔。此处描述的接触焊盘120(具有设置在其上的钝化材料110)形成在互连结构132上方。第一半导体器件100(包括集成电路管芯130)耦合至第二半导体器件134(包括封装衬底、用于集成电路管芯的封装件或PCB)。第一半导体器件100耦合至第二半导体器件134的表面，并且布线124的一端布线接合至第一半导体器件100的接触焊盘120并且相对端接合至第二半导体器件134的接触焊盘120。
图12示出了本发明的一些实施例，其中，多个半导体器件垂直堆叠或封装。堆叠两个第一半导体器件100(包括集成电路管芯)并且之后耦合至第二半导体器件134的表面。布线124的一端布线接合至第一半导体器件100的接触焊盘120并且相对端接合至第二半导体器件134的接触焊盘120。
图13示出了一些实施例，其中，多个半导体器件100水平堆叠或封装。两个第一半导体器件100(包括集成电路管芯或其它类型的器件)耦合至第二半导体器件134的表面。布线124的一端可以布线接合至第一半导体器件100的接触焊盘120并且相对端接合至第二半导体器件134的接触焊盘120。布线124的一端也可以布线接合至一个第一半导体器件100的接触焊盘120并且相对端接合至另一个第一半导体器件100的接触焊盘120。
图14示出了包括接触焊盘120(具有设置在其上的钝化材料110)的封装的半导体器件140的截面图，其中，在一些实施例中，连接器150或接触件150’穿过钝化材料110耦合至接触焊盘120。连接器150或接触件150’的材料和形成方法将在此处参照图21进一步描述。布线124也可以穿过钝化材料110布线接合至封装的半导体器件140的接触焊盘120(未示出)。
封装的半导体器件140包括半导体器件100(包括具有在其上形成的互连结构132的集成电路管芯130)。接触焊盘120(包括设置在其上的钝化材料110)设置在互连结构132的表面上。接触件150’穿过钝化材料110形成在接触焊盘120上。
半导体器件100包封在模塑材料148中。在模塑材料148中也可以形成多个通孔146。例如，多个通孔146包括导电材料并且可以提供用于封装的半导体器件140的垂直连接。在一些实施例中，多个通孔146没有包括在封装的半导体器件140中。
模塑材料148设置在通孔146和半导体器件100周围。例如，在一些实施例中，模塑材料148包封通孔146和半导体器件100。例如，模塑材料148可以包括由绝缘材料(诸如，环氧树脂、填料、应力释放剂(SRA)、粘合促进剂、其他材料或它们的组合)组成的模塑料。在一些实施例中，当施加时，模塑材料148可以包括液体或凝胶，从而使得模塑材料在通孔146和半导体器件100之间和周围流动。之后，固化或允许干燥模塑材料148，从而使得模塑材料形成固体。在一些实施例中，在模塑材料148的固化工艺和等离子体处理工艺期间，可以施加模塑料夹。在一些实施例中，在沉积时，模塑材料148在通孔146和半导体器件100的表面上方延伸。例如，在施加模塑材料148之后，使用平坦化工艺(诸如化学机械抛光(CMP)工艺、研磨工艺、蚀刻工艺或它们的组合)去除模塑材料148的过量部分。其它方法也可以用于平坦化模塑材料148。在用于模塑材料148的平坦化工艺期间，也可以去除通孔146和半导体器件100的部分。在一些实施例中，可以控制施加的模塑材料148的量，从而暴露通孔146和半导体器件100的表面。其它方法也可以用于形成模塑材料148。
可以在半导体器件100、通孔146和模塑材料148的一侧或两侧上形成互连结构132’(包括在一种或多种绝缘材料中形成的多个导线和通孔)。在图14中所示的一些实施例中，例如，在半导体器件100、通孔146和模塑材料148的两侧上形成互连结构132’。在一些实施例中，互连结构132’提供了用于封装的半导体器件140的水平连接。
在一些实施例中，可以在互连结构132’上形成接触焊盘120，其中，接触焊盘120包括设置在其上的钝化材料110。可以在互连结构132’的接触焊盘120上形成穿过钝化材料110的连接器150和/或接触件150’。在一些实施例中，在所示的一个、两个或全部的互连结构132和132’上形成连接器150和/或接触件150’。在一些实施例中，布线124(未示出，见图11至图13)可以用于制成穿过钝化材料110至接触焊盘120的电连接。
载体(未示出)可以用于封装半导体器件100。例如，可以在载体上方形成多个通孔146，并且在一些实施例中，集成电路管芯130(包括其上形成的接触件120)可以使用管芯附接膜(DAF)或胶142耦合至载体。例如，在通孔146和集成电路管芯130周围形成模塑材料148并且在模塑材料148、通孔146和接触件150’(穿过钝化材料110形成在接触件120上)上方形成互连结构132’(例如，图14中所示的视图中的底部互连结构132’)。在一些实施例中，在互连结构132’的接触件120上形成连接器150，并且去除载体。第二载体可以耦合至连接器150(耦合至互连结构132’)，并且可以在封装的半导体器件140的相对侧上形成或不形成顶互连结构132’。工艺步骤和方法的其它顺序也可以用于封装半导体器件100。
例如，接触焊盘120(包括设置在其上的钝化材料110)也可以以其它类型的器件和封装件实现(诸如堆叠式封装(PoP)器件、芯片上系统(SOC)器件、衬底上晶圆上芯片(CoWoS)器件)。
图15至图21是根据本发明的一些实施例的示出形成接触焊盘120的方法的处于制造的各个阶段的半导体器件100的截面图。在这些实施例的一些中，在形成钝化材料110之前，图案化导电材料106以形成接触焊盘120。
在图15中，在绝缘材料104(在衬底102上方形成的)上方形成如图1所示的导电材料106。直接在导电材料106上方形成图2描述的光刻胶层112。如图16所示并且如图3描述的，图案化光刻胶层112。如图17所示，光刻胶层112用作导电材料106的蚀刻掩模，从而由导电材料106形成接触焊盘120。
如图18所示，在接触焊盘120上方和绝缘材料104的暴露部分上方形成钝化材料110。在接触焊盘120的顶面和侧壁上形成钝化材料110。
在一些实施例中，之后，图案化钝化材料110(未示出)。例如，在一些实施例中，其中，钝化材料110包括导电材料(诸如TiN)，可以使用光刻图案化钝化材料110以防止邻近的接触焊盘120之间短路(未在附图中示出)。在用于钝化材料110的蚀刻工艺期间，可以通过如图2所示的在钝化材料110上方形成光刻胶层112，如图3所示图案化光刻胶层112并且之后使用光刻胶层112作为蚀刻掩模来图案化钝化材料110。之后，去除光刻胶层112。
可以留下残留在接触焊盘106的顶面上或接触焊盘106的顶面和侧壁上的钝化材料110。在一些实施例中，钝化材料110的图案可以大于接触焊盘106的图案。如另一实例，在一些实施例中，可以留下残留在接近接触焊盘106的绝缘材料104的表面上方的部分钝化材料110。
在其它实施例中，如图19、图20和图21所示，没有图案化钝化材料110，例如，在一些实施例中，其中，钝化材料110是不导电的。
之后，实施图5和图8描述的制造工艺步骤。例如，在图19中，在钝化材料110上方形成绝缘材料122。如图20所示，图案化绝缘材料122以在钝化材料110(设置在接触焊盘120上方)上方的绝缘材料122中形成开口。
可以制成穿过钝化材料110至半导体器件100的接触焊盘120的电连接。如图9描述的和图9所示的，布线124可以穿过钝化材料110布线接合至接触焊盘120。图21示出了本发明的一些实施例，其中，通过将连接器150或接触件150’穿过接合区域126’中的钝化材料110耦合至接触焊盘120来制成至接触焊盘120的电连接。在一些实施例中，选择形成连接器150或接触件150’的方法，从而不需要去除钝化材料110或它们的部分。例如，当连接器150或接触件150’耦合至接触焊盘120时，例如，可以施加法向力、摩擦力或热量。例如，可以选择钝化材料110的材料和厚度，从而使得连接器150或接触件150’的材料适应于扩散穿过或打破钝化材料110并且形成机械和电连接。连接器150或接触件150’可以包括微凸块、可控塌陷芯片连接(C4)凸块、焊料凸块、焊料球或其它类型的连接器150或接触件150’。在一些实施例中，连接器150或接触件150’可以包括由导电材料组成的柱形凸块或金属(诸如金或其它材料)，其中，如另一实例，施加超声力、法向力和/或热量以打破钝化材料110。
在一些实施例中，连接器150或接触件150’可以包括诸如焊料的共晶材料。此处单词“焊料”的使用包括铅基或无铅焊料(诸如铅基焊料的Pb-Sn组分；无铅焊料包括InSb；锡、银和铜(“SAC”)组分；和其它共晶材料(在电子应用中具有共熔点并且形成导电焊料连接))。例如，对于无铅焊料，可以使用不同组分的SAC焊料，诸如SAC 105(Sn 98.5％、Ag1.0％、Cu 0.5％)、SAC 305和SAC 405。无铅导电材料可以由SnCu化合物形成并且没有使用银(Ag)。无铅焊料连接器也可以包括锡和银、Sn-Ag，而没有使用铜。例如，可以通过沉积工艺(诸如利用压力和/或热量的焊料球落以打破钝化材料110和/或引起连接器150或接触件150’材料的扩散)形成连接器150或接触件150’。连接器150或接触件150’也可以通过其它方法形成并且也可以包括其它材料。
例如，对于图1至图8示出的实施例，连接器150或接触件150’也可以穿过钝化材料110电连接至接触焊盘120。
图22是根据本发明的一些实施例的示出制造半导体器件100的方法的流程图170。在步骤172中，在衬底102上方形成导电材料106。在步骤174中，在导电材料106上方形成钝化材料110，其中，钝化材料110包括材料的类型和厚度，从而使得可以制成穿过钝化材料110至导电材料106的电连接。在步骤176中，图案化导电材料106和钝化材料110以由导电材料106形成接触焊盘120。
本发明的一些实施例包括半导体器件100(包括设置在接触焊盘120上方的钝化材料110)。本发明的一些实施例包括布线124、连接器150或接触件150’(穿过钝化材料110耦合至接触焊盘120)。一些实施例包括制造半导体器件100(包括设置在接触焊盘120上方的钝化材料110)的方法。
本发明的一些实施例的优势包括提供具有改进的接触焊盘的半导体器件，例如，由于在接触焊盘上方的结构中包含钝化材料，因此在各个工艺步骤期间(例如，从湿度、水、清洗工艺、化学工艺、曝光于其他物质，切割和/或热循环)防止或减少了接触焊盘的侵蚀。钝化材料包括足以制成穿过钝化材料至接触焊盘的电和机械连接的材料的类型和厚度。有利地避免了去除钝化材料从而可以制成至接触焊盘的连接的额外的工艺步骤。在制成至接触焊盘的电连接之后，没有用于制成至接触焊盘的电和机械连接的部分钝化材料提供了进一步侵蚀的防止和/或减少。用于钝化材料的材料和应用方法在半导体制造和工艺条件下是廉价和可用的。此外，此处描述的方法、结构和器件较易实现为现有的半导体器件制造和封装工艺流程和结构。
在一些实施例中，该方法包括在半导体器件上方形成接触焊盘，并且在接触焊盘上方形成钝化材料。所述钝化材料的材料类型和厚度允许穿过所述钝化材料与所述接触焊盘建立电连接。
在上述方法中，其中，形成所述钝化材料包括形成选自由Ti、TiN、TaN、Al2O3、Ta2O3、HfO2、TiO2以及它们的组合组成的组中的材料。
在上述方法中，其中，形成所述钝化材料包括形成包括10埃至1400埃的厚度的材料。
在上述方法中，其中，形成钝化材料包括使用物理汽相沉积(PVD)或化学汽相沉积(CVD)形成所述钝化材料。
在上述方法中，其中，所述半导体器件包括集成电路管芯、封装的集成电路管芯、用于集成电路管芯的封装件、封装衬底或印刷电路板(PCB)。
在上述方法中，其中，形成所述钝化材料包括在所述接触焊盘的顶面上方形成所述钝化材料，或其中，形成所述钝化材料包括在所述接触焊盘的顶面和侧壁上形成所述钝化材料。
在一些实施例中，制造半导体器件的方法包括在衬底上方形成导电材料，并且在导电材料上方形成钝化材料。该钝化材料包括材料的厚度和类型，从而使得可以制成穿过钝化材料至导电材料的电连接。该方法包括图案化钝化材料和导电材料以由导电材料形成接触焊盘。
在上述方法中，其中，形成所述导电材料包括形成选自由AlCu、AlSi、Al、Cu以及它们的组合组成的组中的材料。
在上述方法中，其中，图案化所述钝化材料和所述导电材料包括使用光刻工艺。
在上述方法中，其中，所述衬底包括在所述衬底内或上方形成的电路，并且其中，所述方法还包括在形成所述导电材料之前，在所述衬底上方形成绝缘材料，并且制成从所述导电材料穿过所述绝缘材料至所述电路的电连接。
本发明的实施例还提供了一种实现根据权利要求7所述的方法制造的半导体器件的方法，所述方法包括：没有从所述接触焊盘上方去除所述钝化材料或所述钝化材料的部分，制成穿过所述钝化材料至所述接触焊盘的电连接。
在上述方法中，其中，制成至所述接触焊盘的所述电连接包括将布线穿过所述钝化材料布线接合至所述接触焊盘。
在上述方法中，其中，制成至所述接触焊盘的所述电连接包括将布线穿过所述钝化材料布线接合至所述接触焊盘，所述半导体器件包括第一半导体器件，其中，制成所述电连接包括将所述布线的第一端耦合至所述第一半导体器件的接触焊盘，其中，所述方法还包括将所述布线的第二端耦合至第二半导体器件的接触焊盘，并且其中，所述布线的所述第二端与所述布线的所述第一端相对。
在上述方法中，其中，制成至所述接触焊盘的所述电连接包括将连接器或接触件穿过所述钝化材料耦合至所述接触焊盘。
在一些实施例中，半导体器件包括衬底、设置在衬底上方的接触焊盘和设置在接触焊盘上方的钝化材料。布线、连接器或接触件穿过钝化材料耦合至接触焊盘。
在上述半导体器件中，其中，所述钝化材料包括适应于防止或减少所述接触焊盘的侵蚀的材料。
在上述半导体器件中，还包括设置在接近所述接触焊盘的所述衬底上方的绝缘材料。
在上述半导体器件中，还包括设置在接近所述接触焊盘的所述衬底上方的绝缘材料，其中，所述绝缘材料的部分设置在所述接触焊盘的边缘上方。
在上述半导体器件中，还包括设置在接近所述接触焊盘的所述衬底上方的绝缘材料，其中，所述绝缘材料的部分设置在所述接触焊盘的边缘上方，所述接触焊盘包括第一宽度，其中，接近所述接触焊盘的所述绝缘材料中的开口包括第二宽度，并且其中，所述第二宽度小于所述第一宽度。
在上述半导体器件中，还包括设置在所述衬底上方的多个所述接触焊盘，其中，所述钝化材料设置在所述多个接触焊盘的每个上方，并且其中，布线、连接器或接触件穿过所述钝化材料耦合至所述多个接触焊盘的每个。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。

Claims (1)

1.一种制造半导体器件的方法，包括：
在半导体器件上方形成接触焊盘；以及
在所述接触焊盘上方形成钝化材料，其中，所述钝化材料的材料类型和厚度允许穿过所述钝化材料与所述接触焊盘建立电连接。
CN201611195926.6A 2016-01-29 2016-12-22 半导体器件的制造方法 Pending CN107026090A (zh)

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