CN103119702A - 具有聚合物填料沟槽的半导体芯片装置 - Google Patents

具有聚合物填料沟槽的半导体芯片装置 Download PDF

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Publication number
CN103119702A
CN103119702A CN2011800431134A CN201180043113A CN103119702A CN 103119702 A CN103119702 A CN 103119702A CN 2011800431134 A CN2011800431134 A CN 2011800431134A CN 201180043113 A CN201180043113 A CN 201180043113A CN 103119702 A CN103119702 A CN 103119702A
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CN
China
Prior art keywords
semiconductor chip
groove
insulating barrier
polymer filler
semiconductor
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CN2011800431134A
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English (en)
Inventor
迈克尔·Z·苏
贾迈尔·里法伊-艾哈迈德
布莱恩·布莱克
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ATI Technologies ULC
Advanced Micro Devices Inc
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ATI Technologies ULC
Advanced Micro Devices Inc
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Publication of CN103119702A publication Critical patent/CN103119702A/zh
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Abstract

提供一种制造方法，其包括提供具有绝缘层（185）的半导体芯片（105）。所述绝缘层包括沟槽（190）。第二半导体芯片（110）堆叠在所述第一半导体芯片上以留出间隙。聚合物填料（187）放置于所述间隙中，其中所述聚合物填料的一部分被牵引到所述沟槽中。

Description

具有聚合物填料沟槽的半导体芯片装置
技术领域
本发明大致涉及半导体处理，且更具体地涉及具有聚合物填料的堆叠半导体芯片装置及其组装方法。
发明背景
堆叠半导体芯片装置提出针对封装集成的一系列挑战。许多这些技术挑战与基底芯片与堆叠其上的一个或多个芯片之间形貌上的差异相关。与堆叠芯片装置相关的一个特定技术挑战是热管理。许多传统单芯片半导体芯片封装并入散热片或盖，其经由热界面材料而放置于与半导体芯片的背侧热接触。一些传统热界面材料包括聚合物，诸如热油脂。对于更高热消散的装置，封装设计者已经运用焊料型热界面材料，诸如铟。
如果将铟用作热界面材料，那么需要确保在堆叠半导体芯片具有比基底半导体芯片更小的占据面积的这些设计中确保铟冶金接合到基底半导体芯片和覆盖的散热片两者。然而，铟并不容易湿润许多类型的材料。因而，通常在需要与铟冶金接合的表面上形成湿润膜。
为了让传统湿润膜成功与铟接合，在热回流过程期间不得有可能干扰接合的污染物。作为许多半导体芯片封装设计的重要特征的一个潜在污染物是底部填料，其被放置于两个基板之间以减轻两个基板之间热膨胀系数差异的影响。因此需要使底部填料不污染将用于冶金接合的湿润膜的一部分。
本发明涉及克服或减小一个或多个上述缺点的影响。
发明概要
根据本发明的实施方案的一个方面，提供一种制造方法，其包括提供具有绝缘层的半导体芯片。所述绝缘层包括沟槽。第二半导体芯片堆叠在第一半导体芯片上以留出间隙。聚合物填料被放置于所述间隙中，其中聚合物填料的一部分被牵引到沟槽中。
根据本发明的实施方案的另一个方面，提供一种制造方法，其包括将绝缘层施加到第一半导体芯片并且在所述绝缘层中形成沟槽。所述沟槽被调适来接收聚合物填料。第一半导体芯片被调适来使第二半导体芯片堆叠在其上，以留出间隙，聚合物填料的一部分定位在所述间隙中。
根据本发明的实施方案的另一个方面，提供一种设备，其包括第一半导体芯片和在第一半导体芯片上的绝缘层。绝缘层包括沟槽。第二半导体芯片堆叠在第一半导体芯片上以留出间隙。聚合物填料定位在间隙中，其中聚合物填料的一部分在沟槽中。
附图简述
在阅读下文详细的描述和参考附图时将了解本发明的上述和其它优点，其中：
图1是半导体芯片装置的示例性实施方案的截面图，其包括半导体芯片和堆叠在其上的三个半导体芯片的配置；
图2是半导体芯片的堆叠配置的图示；
图3是描绘绝缘层施加的一个半导体芯片的截面图；
图4是描绘绝缘层中沟槽形成的半导体芯片的截面图；
图5是描绘堆叠一个或多个附加半导体芯片的半导体芯片的截面图；
图6是描绘聚合物填料的施加的半导体芯片的堆叠配置的截面图；
图7是描绘聚合物填料的替代示例性施加的半导体芯片的堆叠配置的截面图；
图8是描绘聚合物填料的替代示例性第二施加的半导体芯片的堆叠配置的截面图；
图9是描绘绝缘层中替代示例性沟槽形成的半导体芯片的截面图；和
图10是描绘替代示例性聚合物填料沉积和处理的半导体芯片的截面图。
具体实施方式
公开各种堆叠半导体芯片配置。所公开的实施方案并入绝缘膜，其可用作钝化结构，其包括沟槽。所述沟槽被设计来在聚合物填料施加和固化期间牵引聚合物填料，从而避免了焊料湿润膜的污染。本质上，沟槽抑制了聚合物填料的横向移动，其原本可能涂布湿润膜。现在将描述附加细节。
在下述附图中，参考数字通常在相同元件出现在多个附图中的情况下重复。现参考附图且特别参考图1，其中示出半导体芯片装置100的示例性实施方案的截面图，所述半导体芯片装置100包括半导体芯片105和其上堆叠的三个半导体芯片110、115和120的配置。半导体芯片105可包括将在下文中更详细描述的多层。应了解，半导体芯片105和芯片110、115和120可根据需要安装到无数不同类型的电路板或载体基板的任意一种。本文所述的安装结构和技术不限于任何特定类型的半导体装置。因此，半导体芯片105、110、115和120可以是电子装置中使用的无数不同类型的电路装置的任意一种，诸如，例如微处理器、图形处理器、组合的微处理器/图形处理器、专用集成电路、存储器装置、主动光学装置、如激光器或类似物，并且可以是单核或多核或甚至侧向堆叠有附加晶粒。此外，半导体芯片105、110、115和120的一个或多个可被构造为具有或不具有一些逻辑电路的中介层。因此术语“芯片”包括中介层，且反之亦然。半导体芯片105、110、115和120可由块状半导体构成，诸如硅或锗，或绝缘体材料上的半导体，诸如绝缘体上硅材料，或甚至其它类型的材料，甚至绝缘材料，如二氧化硅、四乙基正硅酸盐或其它。应了解芯片数量可以改变。
在这个说明性实施方案中，半导体芯片105、110、115和120可安装到电路板125。电路板125可采用多种构造。实例包括半导体芯片封装基板、电路板，或实际上任何其它类型的印刷电路板。虽然电路板125可使用单片结构，但是更典型的构造将利用积层设计。在这方面，电路板125可由中心层组成，其上形成一个或多个积层，且其下方形成附加的一个或多个积层。所述中心层本身可由一个或多个层的堆叠组成。如果实施为半导体芯片封装基板，那么电路板125中的层数可从四个改变到十六个或更多，但是也可以使用少于四个。也可以使用所谓的“无中心层”设计。电路板125层可由绝缘材料组成，如各种已知的环氧树脂，散布有金属互连。可使用除积层以外的多层构造。任选地，电路板125可由已知的陶瓷或适于封装基板或其它印刷电路板的其它材料组成。电路板125设有许多导体迹线和通孔和其它结构（不可见）以提供半导体芯片105、110、115和120与另一个装置（如另一个电路板，例如）之间的电源、接地和信号传送。输入/输出结构，诸如这个说明性实施方案中的焊球127可用于将电路板125与另一个装置介接。当然，可使用除球栅阵列以外的系统，如引脚栅格阵列、接点栅格阵列或其它。
为促进从半导体芯片105、110、115和120的热传递，半导体芯片装置100可设有散热片或盖130，其可仅由粘合胶珠135而固定到电路板125。粘合剂135可以是已知的触变粘合剂、环氧树脂、另一类型的聚合物或甚至焊料。盖130根据需要可以是多种不同构造的任意一种，如图1中描绘的顶帽构造、浴缸设计或其它构造。盖130可根据需要使用许多不同类型的材料，如已知的塑料、陶瓷或金属材料。一些示例性材料包括镀镍的铜、阳极化的铝、铝-硅-碳化物、氮化铝、氮化硼或类似物。
半导体芯片105覆晶安装到电路板125并且经由多个互连结构140而电连接其上。互连结构140例如可例如是导电凸块、具有或不具有焊料增强的导体柱或其它类型的互连结构。虽然仅可见少数互连结构140，但是取决于半导体芯片105的大小和复杂性，可具有几十个、几百个或甚至几千个这种导体结构。可在半导体芯片105与电路板125之间插入底部填充材料层145，以帮助减轻与差异CTE相关的问题。底部填充材料层145可由已知的环氧树脂材料组成，如具有或不具有硅石填料的环氧树脂和酚醛树脂或类似物。两个实例是可从Namics获得的119和2BD型。现在将描述半导体芯片105的附加细节。
如上文所述，半导体芯片105可由多层组成。在这个说明性实施方案中，半导体芯片105可由块状半导体层150、装置层155、接触绝缘层160和金属化层165组成。块状半导体层155可由硅、锗或适于集成电路制造的其它材料组成。装置层155可由无数个电路结构组成，包括晶体管、电容器或类似物。接触绝缘层160可由二氧化硅或适于接触绝缘层的其它已知绝缘材料组成，并且可以是单片或叠层。金属化层165可由金属化和层间介电膜的多个交替层组成，且可包括数个这种膜。金属化层165的两个部分由线167和169示意地表示。在块状半导体层150的相对侧上提供再分布层170。RDL层170可由提供RDL功能的金属化和层间介电膜的一或多层组成。描绘两个RDL导体结构，并且由线175和180示意地表示。然而，熟练技工应了解，组成RDL层170和金属化层165两者的金属化结构的实际数量可能相当多。多个穿硅通孔（TSV）（其两个示出并且标注为177和179）可伸展通过半导体层150、装置层155和接触绝缘层160。虽然示出两个，但是TSV177和179数量可能是数十个或更多。
仍然参考图1，钝化层185定位在RDL层170上。钝化层185可以是由已知钝化层材料组成的单片层，诸如，例如二氧化硅、氮化硅、聚酰亚胺或类似物。任选地，钝化层185根据需要可以是多层绝缘材料的叠层，诸如二氧化硅和氮化硅的交替层。聚合物填料187安置在钝化层185与半导体芯片110之间并用于减轻半导体芯片105、110、115和120之间差异CTE的影响。聚合物填料187可由与针对底部填料145所述的相同类型的材料组成，或甚至由不导电粘合剂组成，如压接粘合剂。钝化层185设有沟槽190，其有利地定位为接近半导体芯片110、115和120的至少一个（且优选地是最底下一个）的外壁189。沟槽190功能是向下牵引聚合物填料187的一部分，且含有聚合物填料187的一部分。将聚合物填料187的一部分牵引到沟槽190中的一个技术目的是防止聚合物填料187跨湿润膜205的上表面散布并在其上固化。如果聚合物填料187的部分在湿润膜205的上表面上涂布并固化，那么焊料型热界面材料195可能在这些涂布区中无法湿润所述湿润膜205，并产生将大大增加半导体芯片105与热界面材料195之间的路径的热阻抗的气囊或其它类型的脱层区域。另一有关技术目的是使聚合物填料187的部分能至少聚集在半导体芯片110的壁189附近。靠近壁189的积层聚合物填料187作用像弹簧，以缓冲热应变。
为帮助热从半导体芯片105和半导体芯片110、115和120两者传递到盖130，可在半导体芯片105与盖130之间和半导体芯片110、115和120周围安置热界面材料195。热界面材料195可使用多种材料，诸如，例如各种焊料或有机热界面材料。示例性金属材料包括例如铟、铟焊料、锡-银、铋-锡、其它锡焊料、镓加上聚合物或类似物。各种非金属材料包括适于热界面材料的多种聚合物材料，如，例如与氧化锌混合的硅酮橡胶。任选地，可使用除硅酮橡胶以外的顺从基材，和导热但不导电的粒子。
需要焊料型热界面材料195容易地湿润半导体芯片105的上表面和盖130的下表面200。因为钝化层185可能不容易湿润焊料型材料，所以湿润膜205有利地形成或另外定位在钝化结构185上。类似地，湿润膜210可形成或另外施加到盖130的下表面200。湿润膜205和210的组成可被定制来有利地提供焊料型热界面材料195的有利湿润。例如，在热界面材料195由铟或其合金组成的情况下，金或铂可以是湿润膜205和210的适当材料。
可以经由多个导体柱215、焊点或类似物提供半导体芯片105与半导体芯片110、115和120之间的电界面。导体柱215可由各种导体组成，如铜、银、镍、铂、金、铝、钯、这些材料的合金或叠层或类似物，且可盖上焊料。半导体芯片110、115和120可经由多个穿硅通孔220而与支柱215电连接。因此，从所述的半导体芯片120到一个互连结构140的典型示例性电路径可包括一个穿硅通孔220、一个导电柱215、由线175示意地表示的RDL结构、穿硅通孔177、由线167示意地表示的金属化结构和一个互连结构140。然而，熟练技工应了解，可使用很多种不同类型的导体结构和电互连方案，以连接各种半导体芯片105、110、115和120和电路板125。
现也注意图2，其是从半导体芯片装置100移除且其上没有堆叠半导体芯片110、115和120的半导体芯片105的图示。注意，块状半导体层150、装置层155、接触绝缘层160、金属化叠层165、RDL层170、钝化层185和湿润膜205是可见的。可见多个导体柱215从钝化层185的中心部分225向上突出。中心部分225的占据面积由沟槽190的形状和大小界定。在这个说明性实施方案中，钝化层185中的沟槽190根据需要可与半导体芯片105具有相同的总占据面积，即，矩形、正方形等等，或具有不同占据面积。
现可通过参考图3、图4、图5和图6且首先参考图3了解用于制造钝化层185、其中的沟槽190和定制聚合物填料187的示例性方法。图3是在制造块状半导体层150上的装置层155、接触绝缘层160和金属化叠层165之后的半导体芯片105的截面图。此外，已使用已知技术构成RDL层170和TSV177和179。可通过已知材料沉积和图案化技术形成钝化层185。在示例性实施方案中，可交替施加多层二氧化硅和氮化硅以建立叠层结构。交替层的数量可例如是三层二氧化硅和三层氮化硅。可使用已知的化学气相沉积技术来施加钝化层185。类似地，导电柱215可在钝化层185形成之前或之后制造于半导体芯片105上。
在这阶段，钝化层185设定用来形成沟槽。现注意图4，其示出沟槽190的形成。可使用多种技术制造沟槽190，诸如已知的光刻技术和化学蚀刻界定、激光烧蚀或甚至机械切割。如果使用光刻，那么可应用已知的抗蚀剂掩膜施加和图案化技术。任选地，可使用非接触式掩膜（未示出）以覆盖钝化膜185的所需部分，同时使其将形成沟槽190的部分暴露。可如图4中所示在下至RDL层170处建立沟槽190。任选地，沟槽190可形成到并不完全延伸到RDL层170的某一较小深度。在沟槽190形成的情况下，半导体芯片110、115和120的上述堆叠可覆晶或另外安装到导体柱215。如果需要热步骤来建立TSV220与导体柱215之间的冶金接合，诸如经由回流焊或另外，那么半导体芯片105和半导体芯片110、115和120可能在这个阶段经受一些加热过程。应了解，半导体芯片110、115和120可在半导体芯片105是晶圆级时或在切割后堆叠在半导体芯片105上。
接着且如图6中所示，其是半导体芯片105和半导体芯片110、115和120的截面图，可通过适当施加器230沉积聚合物填料187。当聚合物填料187分配时，毛细管作用将使其部分在半导体芯片110与钝化层185的中央部分225之间被牵引。聚合物填料187的一部分将通过重力和表面张力两者的组合而被向下牵引到沟槽190中，且因此远离湿润膜205的上表面。以此方式，湿润膜205将不被聚合物填料187的部分污染。沉积之后，适当的固化过程可用于设定聚合物填料187。这可能根据需要要求加热步骤、施加适当辐射或两者的组合。一个示例性固化过程涉及加热到约240℃至260℃达30分钟，接着逐渐下降。
在图3、图4、图5和图6中描绘的示例性方法中，聚合物填料187作为单片层分配。然而，熟练技工应了解，也可以使用多阶段沉积和固化过程。在此方面，现注意图7和图8，其是如图6但描绘正在经历多阶段填料沉积和固化过程的半导体芯片105的截面图。首先参考图7，可从施加器230分配聚合物填料187’，使得其至少一部分流动到沟槽190中，且如所示可能一些在半导体芯片110与钝化层185的中央部分225之间。聚合物填料187’可以是与本文中其它部分所述相同或不同类型的填料。在这阶段，聚合物填料187’可经受部分或完全固化过程。接着，且如图8中所示，本文中其它部分所公开的类型的附加聚合物填料187’’可分配在聚合物填料187’上，并经受第二固化过程。可执行多次这种沉积和固化过程，同时仍然实现在接近半导体芯片110的壁189处提供像弹簧的填料界面的技术目的。
在上述说明性实施方案中，沟槽190具有相对垂直的侧壁。然而，熟练技工应了解，可使用除完全垂直以外的轮廓。在此方面，现注意图9，其是如图4但半导体芯片105装配有替代的示例性钝化层185’的截面图。在此，沟槽190’（其可提供与本文中其它部分所述的沟槽190相同的功能）可如所示形成有倾斜侧壁。沟槽190’的倾斜侧壁轮廓具有建立稍微较大填料体积的优点，其可提供稍微较大的弹簧作用，且因此提供针对与差异CTE相关的有害应力和应变的更好保护。如果使用具有或不具有等离子增强的化学蚀刻，那么可通过改变蚀刻化学物质和/或压力和功率而提供沟槽190的倾斜侧壁轮廓。任选地，如果使用激光烧蚀，那么可通过精确控制激光光点大小、停留时间和功率设定来提供倾斜侧壁。本文中公开的任何沟槽190和190’的尺寸可取决于装置几何形状和可用的材料图案化技术而改变。在示例性实施方案中，沟槽190和190’的宽和深可为约1μm至5μm。
在另一个示例性实施方案中，聚合物填料187’’’如图10中所示可在放置最底下的芯片110之前定位在半导体芯片105上，且使用压接。在此，聚合物填料187’’’可由与本文中其它部分公开的相同类型的材料组成，且分配在邻近导体柱215的钝化层185上。随后，可在聚合物填料187’’’上压缩最底下的半导体芯片110（或甚至这种芯片的堆叠）。沟槽190将在压缩步骤期间牵引聚合物填料187’’’的一部分。
本文中公开的任何示例性实施方案可具体体现为安置在计算机可读介质（如，例如半导体、磁盘、光盘或其它存储介质）中的指令，或计算机数据信号。所述指令或软件可能能够合成和/或模拟本文中公开的电路结构。在示例性实施方案中，电子设计自动化程序，如Cadence APD、Cadence Spectra、Encore或类似物可用于合成所公开的电路结构。所得代码可用于制造所公开的电路结构。
虽然本发明可能具有各种修改和替代形式，但是特定实施方案已在附图中经由举例而示出并且已在其中详细描述。但是，应了解本发明并非旨在受限于所公开的特定形式。而是，本发明覆盖属于如下文附属权利要求定义的本发明的精神和范围内的所有修改例、等效例和替代例。

Claims (21)

1.一种制造方法，其包括：
提供包括绝缘层（185）的半导体芯片（105），所述绝缘层包括沟槽（190）；
将第二半导体芯片（110）堆叠在所述第一半导体芯片上以留出间隙；和
将聚合物填料（187）放置于所述间隙中，其中所述聚合物填料的一部分被牵引到所述沟槽中。
2.根据权利要求1所述的方法，其包括将第三半导体芯片（115）堆叠在所述第二半导体芯片上。
3.根据权利要求1所述的方法，其包括通过从所述绝缘层移除材料而形成所述沟槽。
4.根据权利要求1所述的方法，其包括将焊料湿润膜（205）施加到所述沟槽外的所述绝缘层。
5.根据权利要求4所述的方法，其包括将焊料热界面材料（195）施加到所述焊料湿润膜。
6.根据权利要求1所述的方法，其包括将所述第一半导体芯片安装到电路板（125）。
7.根据权利要求6所述的方法，其包括将散热片（130）放置于与所述焊料热界面材料热接触。
8.根据权利要求1所述的方法，其中所述沟槽包括倾斜侧壁。
9.一种制造方法，其包括：
将绝缘层（185）施加到第一半导体芯片（105）；
在所述绝缘层中形成沟槽（190），所述沟槽被调适来接收聚合物填料（187）；和
其中所述第一半导体芯片被调适来使第二半导体芯片（110）堆叠在其上以留出间隙，所述聚合物填料的一部分定位在所述间隙中。
10.根据权利要求9所述的方法，其包括通过从所述绝缘层移除材料而形成所述沟槽。
11.根据权利要求9所述的方法，其包括将焊料湿润膜（205）施加到所述沟槽外的所述绝缘层。
12.根据权利要求11所述的方法，其包括将焊料热界面材料（195）施加到所述焊料湿润膜。
13.根据权利要求9所述的方法，其包括将所述第一半导体芯片安装到电路板（125）。
14.根据权利要求13所述的方法，其包括将散热片（130）放置于与所述焊料热界面材料热接触。
15.一种设备，其包括：
第一半导体芯片（105）；
所述第一半导体芯片上的绝缘层（185），所述绝缘层包括沟槽（190）；
堆叠在所述第一半导体芯片上的第二半导体芯片（110），以留出间隙；和
定位在所述间隙中的聚合物填料（187），其中所述聚合物填料的一部分在所述沟槽中。
16.根据权利要求15所述的设备，其中所述聚合物填料在所述绝缘层上不延伸超过所述沟槽。
17.根据权利要求15所述的设备，其包括堆叠在所述第一半导体芯片上的多个半导体芯片（110、115、120）。
18.根据权利要求15所述的设备，其包括所述沟槽外的所述绝缘层上的焊料湿润膜（205），和所述焊料湿润膜上的焊料热界面材料（195）。
19.根据权利要求18所述的设备，其包括与所述焊料热界面材料热接触的散热片（130）。
20.根据权利要求15所述的设备，其中所述沟槽包括倾斜侧壁。
21.一种设备，其包括：
第一半导体芯片（105）；
所述第一半导体芯片上的绝缘层（185），所述绝缘层包括沟槽（190）；和
其中所述设备具体体现为存储在计算机可读介质中的指令。
CN2011800431134A 2010-09-09 2011-09-09 具有聚合物填料沟槽的半导体芯片装置 Pending CN103119702A (zh)

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