CN105280579A - 半导体封装件和方法 - Google Patents
半导体封装件和方法 Download PDFInfo
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- CN105280579A CN105280579A CN201410767804.4A CN201410767804A CN105280579A CN 105280579 A CN105280579 A CN 105280579A CN 201410767804 A CN201410767804 A CN 201410767804A CN 105280579 A CN105280579 A CN 105280579A
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Classifications
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Abstract
本发明提供了半导体封装件和方法。第一封装件利用第一外部连接件和第二外部连接件接合至第一衬底。使用不同于第一外部连接件的材料形成第二外部连接件,以提供来自第一封装件的热路径。在一个特定实施例中,第一外部连接件是焊料球并且第二外部连接件是铜块。
Description
技术领域
本发明涉及半导体封装件和方法。
背景技术
自发明集成电路(IC)以来,由于各种电子组件(即,晶体管、二极管、电阻器、电容器等)的集成密度的不断提高使得半导体行业已经历了快速发展。在极大程度上,集成密度的提高源自于最小部件尺寸的不断减小,这就允许在给定区域内集成更多的组件。
这些集成提高实际上是二维(2D)的,原因是集成组件所占用的体积基本上位于半导体晶圆的表面上。尽管光刻工艺的明显提高已相当大地改善了2DIC的形成,但是,存在对可在二维中实现的密度的限制。这些限制之一是需要制造这些组件的最小尺寸。并且,当将更多个器件放置在一个芯片中时,要利用更为复杂的设计。
试图进一步增加电路密度,已经研究了三维(3D)IC。在典型的3DIC形成过程中,两个管芯接合在一起并且在衬底上的每个管芯和接触焊盘之间形成电连接件。例如,一种尝试方法包括将两个管芯互为顶部地接合在一起。然后堆叠的管芯接合至载体衬底并且焊线将每个管芯上的接触焊盘电连接至载体衬底上的接触焊盘。
发明内容
针对现有技术中存在的问题,根据本发明的一个方面,提供了一种半导体器件,其包括:
第一封装件,包括:
第一半导体管芯,被密封剂包围;以及
通孔,穿过密封剂并且横向远离第一半导体管芯;以及
第一衬底,利用第一外部连接件和第二外部连接件接合至第一封装件,其中,第二外部连接件包括不同于第一外部连接件的材料。
根据本发明的一个实施例,第一外部连接件是焊料球并且第二外部连接件是铜块。
根据本发明的一个实施例,第一外部连接件是焊料球并且第二外部连接件是铜球。
根据本发明的一个实施例,第一外部连接件是焊料球并且第二外部连接件是铜箔。
根据本发明的一个实施例,第二外部连接件完全位于第一半导体管芯的下方。
根据本发明的一个实施例,第二外部连接件部分地位于第一半导体管芯的下方。
根据本发明的一个实施例,第二外部连接件设置为在从上向下看时横向远离第一半导体管芯。
根据本发明的一个实施例,第一封装件是集成扇出封装件。
根据本发明的另一方面,提供了一种半导体器件,包括:
集成扇出封装件;
第一组外部连接件,接合至集成扇出封装件的第一侧;以及
第二组外部连接件,接合至集成扇出封装件的第一侧,其中,第二组外部连接件具有高于第一组外部连接件的导热率。
根据本发明的一个实施例,还包括第一衬底,第一衬底接合至第一组外部连接件和第二组外部连接件。
根据本发明的一个实施例,还包括第二衬底,第二衬底在集成扇出封装件的与第一衬底相反的一侧接合至集成扇出封装件。
根据本发明的一个实施例,第一组外部连接件包括焊料球并且第二组外部连接件包括铜块。
根据本发明的一个实施例,第一组外部连接件包括焊料球且第二组外部连接件包括铜箔。
根据本发明的一个实施例,第一组外部连接件包括焊料球并且第二组外部连接件包括铜浆。
根据本发明的一个实施例,还包括位于第二组外部连接件内的沟槽。
根据本发明的又一方面,提供了一种制造半导体器件的方法,所述方法包括:
将第一组外部连接件设置在集成扇出封装件的第一侧;
将第二组外部连接件设置在集成扇出封装件的第一侧,其中,第二组外部连接件具有高于第一组外部连接件的导热率;以及
将集成扇出封装件接合至第二组外部连接件和第一组外部连接件。
根据本发明的一个实施例,设置第二组外部连接件还包括将铜块设置在集成扇出封装件的第一侧。
根据本发明的一个实施例,设置第二组外部连接件还包括将铜箔设置在集成扇出封装件的第一侧。
根据本发明的一个实施例,设置第二组外部连接件还包括将铜浆设置在集成扇出封装件的第一侧。
根据本发明的一个实施例,还包括将第一封装件接合至不同于集成扇出封装件的第一侧的集成扇出封装件的第二侧。
附图说明
当结合附图进行阅读时,根据下面详细的描述可以更好地理解本发明。应该强调的是,根据工业中的标准实践,没有按比例绘制各种部件。实际上,为了清楚地讨论,可以任意地增加或减少各种部件的尺寸。
图1示出了根据一些实施例的第一封装件。
图2A至图2B示出了根据一些实施例的第二封装件。
图3示出了根据一些实施例的第一封装件接合至第二封装件。
图4A至图4C示出了根据一些实施例的使用外部连接件将第二封装件接合至衬底。
图5示出了根据一些实施例的热流。
图6示出了根据一些实施例的位于外部连接件内的沟槽。
图7示出了根据一些实施例的使用球用作外部连接件的一个实施例。
图8示出了根据一些实施例的外部连接件的布置。
具体实施方式
以下公开提供了多种不同实施例或实例,用于实现本发明的不同特征。以下将描述组件和布置的特定实例以简化本发明。当然,这些仅是实例并且不旨在限制本发明。例如,在以下描述中,在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例,也可以包括其他部件可以形成在第一部件和第二部件之间使得第一部件和第二部件不直接接触的实施例。另外,本发明可以在多个实例中重复参考符号和/或字符。这种重复用于简化和清楚,并且其本身不表示所述多个实施例和/或配置之间的关系。
现参照图1,示出了第一封装件100。第一封装件100可包括第一衬底103、第一半导体器件101、第一接触焊盘109、第一密封剂111、和第一外部连接件113。在一个实施例中,例如,第一衬底103可以是封装衬底,其包括将第一半导体器件101连接至诸如第二封装件200(未在图1中示出,但在参照图2A至图2B的下文中给出示出和描述)的其他外部器件的内部连接件。
可选地,第一衬底103可以是插件,其用作将第一半导体器件101连接至其他外部器件的中间衬底。在该实施例中,例如,第一衬底103可以是硅衬底(掺杂或未掺杂)、或绝缘体上硅(SOI)衬底的有源层。然而,第一衬底103可选地可为玻璃衬底、陶瓷衬底、聚合物衬底、或任何其他可提供合适的保护和/或互连功能的衬底。这些和任意其他合适的材料可选地可用于第一衬底103。
第一半导体器件101可以是为特定目的而设计的半导体器件,诸如逻辑管芯、中央处理单元(CPU)管芯、存储管芯、它们的组合等。在一个实施例中,第一半导体器件101包括特定功能所期望的位于其内的诸如晶体管、电容器、感应器、电阻器、第一金属化层(未示出)等的集成电路器件。在一个实施例中,设计和制造第一半导体器件101以与第二半导体器件211(未在图1中示出,但在参照图2A至图2B的下文中给出示出和描述)协作工作或同时工作。
第一接触焊盘109可形成在第一衬底103上以在第一半导体器件101和(例如)第一外部连接件113之间形成电连接。在一个实施例中,第一接触焊盘109可形成在第一衬底103内的电布线(未在图1中单独示出)的上方且与其电连接。第一接触焊盘109可包括铝,但是可选地可以使用诸如铜的其他材料。使用诸如溅射的沉积工艺可形成第一接触焊盘109,从而形成一层材料(未示出),并且然后通过合适的工艺(诸如光刻掩模和蚀刻)可去除该层材料的部分,从而形成第一接触焊盘109。然而,可利用任何其他合适的工艺来形成第一接触焊盘109。可形成厚度介于约0.5μm至约4μm之间(如,约1.45μm)的第一接触焊盘109。
第一密封剂111可用于密封和保护第一半导体器件101和第一衬底103。在一个实施例中,第一密封剂111可以为模塑料且可使用模制器件(未在图1中示出)进行放置。例如,第一衬底103和第一半导体器件101可放置在模制器件的空腔内,并且该空腔可以为气密密封。第一密封剂111可在空腔气密密封之前放置在空腔内或通过喷射口将第一密封剂111喷入空腔内。在一个实施例中,第一密封剂111可以为模塑料树脂,如聚酰亚胺、PPS、PEEK、PES、耐热性水晶树脂、它们的组合等。
一旦已将第一密封剂111放置在空腔内使得第一密封剂111密封第一衬底103和第一半导体器件101周围的区域,那么,第一密封剂111可固化以硬化第一密封剂111实现最佳保护。尽管准确的固化工艺至少部分地取决于为第一密封剂111选择的特定材料,但是,在选择模塑料用作第一密封剂111的实施例中,通过诸如将第一密封剂111加热到约100℃至约130℃之间的温度(诸如,约125℃)持续约60秒至约3000秒(诸如,600秒)的工艺可发生固化。此外,引发剂和/或催化剂可包含在第一密封剂111内以更好地控制固化工艺。
然而,作为本领域的技术人员会认识到,上述的固化工艺仅为示例性工艺且并不意味限制当前实施例。可选地可以使用诸如辐射或甚至允许第一密封剂111在环境温度下硬化的其他固化工艺。可使用任何合适的固化工艺,并且所有这样的工艺完全旨在包含于本文所讨论的实施例的范围内。
在一个实施例中,可形成第一外部连接件113以在第一衬底103和(例如)第二外部连接件203(未在图1中示出,但在参照图2A至图2B的下文中给出示出和描述)之间提供外部连接。第一外部连接件113可以为诸如微凸块或可控塌陷芯片连接(C4)凸块的接触凸块并且可包括诸如锡的材料、或诸如银或铜的其它合适材料。在第一外部连接件113是锡焊料凸块的实施例中,通过诸如蒸发、电镀、印刷、焊料转移、球置放等的任何合适方法先形成厚度例如约为100μm的锡层,从而可形成第一外部连接件113。一旦在该结构上已形成锡层,实施回流工艺以将材料成型为期望的凸块形状。
图2A示出了在形成(例如)第二封装件200(诸如,集成扇出(InFO)封装件)的工艺中的中间产品。如图2A所示,中间结构包括载体衬底201、粘合层202、聚合物层205、晶种层207、通孔209、第二半导体器件211、第二密封剂213、第一重布层215、第二接触焊盘217、第一钝化层219、和第二外部连接件203。载体衬底201例如包括诸如玻璃或氧化硅的硅基材料、或诸如氧化铝的其他材料、这些材料中的任意组合等。载体衬底201是平面的,以适应诸如第二半导体器件211的半导体器件的接合。
粘合层202放置在载体衬底201上以辅助上覆结构(例如,聚合物层205)的粘合。在一个实施例中,粘合层202可包括紫外线光胶,在其暴露给紫外光时会失去其粘合性。然而,还可使用诸如压敏粘合剂、辐射固化粘合剂、环氧树脂、它们的组合等的其他类型的粘合剂。粘合层202可以半液体或胶的方式放置在载体衬底201上,这样在压力下很容易变形。
聚合物层205放置在粘合层202上方并且用于一旦已接合(例如)第二半导体器件211时为第二半导体器件211提供保护。在一个实施例中,聚合物层205可以是聚苯并恶唑(PBO),但是,可选地可以使用诸如聚酰亚胺或聚酰亚胺衍生物的任何合适材料。使用例如旋转涂覆工艺可将聚合物层205设置为厚度介于约2μm至约15μm之间(诸如,约5μm),但是,可选地可以使用任何合适的方法和厚度。
晶种层207是导电材料薄层,其有助于在后续处理步骤中形成更厚的层。晶种层207可包括厚度约为的钛层,然后是厚度约为的铜层。根据所期望的材料,使用诸如溅射、蒸发或PECVD工艺的工艺可产生晶种层207。可形成厚度为约0.3μm至约1μm之间(诸如,约0.5μm)的晶种层207。
一旦已形成晶种层207,在晶种层207上方可设置和图案化光刻胶(未在图2A中示出)。在一个实施例中,使用例如旋转涂覆技术可在晶种层207上设置高度介于约50μm至约250μm之间(诸如,约120μm)的光刻胶。一旦处于合适位置,然后通过将光刻胶暴露给图案化能量源(例如,图案化光源)以诱导化学反应,从而诱导暴露给图案化光源的光刻胶的部分发生物理变化,以此可图案化光刻胶。然后,根据期望的图案,将显影剂应用于曝光的光刻胶以利用物理变化且选择性地去除光刻胶的曝光部分或光刻胶的未曝光部分。
在一个实施例中,形成在光刻胶中的图案是用于通孔209的图案。形成的通孔209位于诸如第二半导体器件211的后续接合的器件的不同侧。然而,可以可选地使用用于通孔209的图案的任意合适布置。
一旦已图案化光刻胶,通孔209就形成在光刻胶中。在一个实施例中,通孔209包括诸如铜、钨、其他导电金属等的一种或多种导电材料,并且可例如通过电镀、无电镀等形成通孔209。在一个实施例中,使用电镀工艺,其中,晶种层207和光刻胶沉浸或浸入电镀溶液中。晶种层207的表面电连接至外部DC电源的负极,使得晶种层207用作电镀工艺中的阴极。诸如铜阳极的固体导电阳极也浸入溶液中并且接合至电源的正极。阳极的原子溶解在溶液中,阴极,例如,晶种层207,可从其中获取溶解的原子,从而电镀光刻胶的开口内的晶种层207的暴露导电区。
一旦使用光刻胶和晶种层207形成通孔209,就可以使用合适的去除工艺去除光刻胶。在一个实施例中,可使用等离子体灰化工艺去除光刻胶,由此,可增加光刻胶的温度直至光刻胶经历热分解且可被去除。然而,可以可选地使用诸如湿剥离的任意其他合适的工艺。去除光刻胶可暴露出晶种层207的下面部分。
去除光刻胶暴露出下面的晶种层207之后,这些部分被去除。在一个实施例中,通过例如湿蚀刻或干蚀刻工艺可去除晶种层207的暴露部分(例如,没有被通孔209覆盖的部分)。例如,在干蚀刻工艺中,使用通孔209作为掩模,可将反应剂引向晶种层207。可选地,蚀刻剂可被喷射或以其他方式与晶种层207接触从而去除晶种层207的暴露部分。蚀刻掉晶种层207的暴露部分之后,聚合物层205的一部分暴露在通孔209之间。
已形成通孔209之后,第二半导体器件211可放置在暴露的聚合物层205上。在一个实施例中,第二半导体器件211可类似于第一半导体器件101,诸如为逻辑管芯、存储管芯、CPU管芯、它们的组合等。在一个实施例中,设计和制造第二半导体器件211以与第一半导体器件101工作或同时工作。使用例如粘合材料可将第二半导体器件211接合至聚合物层205,但是,可以可选地使用任何合适的接合方法。
在一个实施例中,第二半导体器件211包括第二衬底221、有源器件(未单独示出)、第二金属化层223、第二钝化层225、和第二接触焊盘227。第二衬底221可包括块体硅(掺杂或未掺杂)、或绝缘体上硅(SOI)衬底的有源层。通常,SOI衬底包括诸如硅、锗、硅锗、SOI、绝缘体上硅锗(SGOI)、或它们组合的半导体材料的层。可使用的其他衬底包括多层衬底、梯度衬底、或混合取向衬底。
位于第二半导体器件211内的有源器件包括可用于产生满足第二半导体器件211设计的结构性和功能性需要的多种有源器件和无源器件,诸如,电容器、电阻器、感应器等。使用任意合适的方法可在第二衬底221内或第二衬底221上形成位于第二半导体器件211内的有源器件。
第二金属化层223形成在第二衬底221以及第二半导体器件211内的有源器件的上方并且设计为连接第二半导体器件211内的多种有源器件以形成功能性电路。在一个实施例中,第二金属层223由电介质和导电材料的交替层形成并且可通过任意合适的工艺(诸如,沉积、镶嵌、双镶嵌等)形成。在一个实施例中,虽然可具有通过至少一个层间介电层(ILD)与第二衬底221分隔开的四层金属化层,但是第二金属化层223的准确数量取决于第二半导体器件211的设计。
第二接触焊盘227可形成在第二金属化层223上方且与第二金属化层223电接触。第二接触焊盘227可包括铝,但是,可以可选地使用诸如铜的其他材料。使用诸如溅射的沉积工艺可形成第二接触焊盘227从而形成材料层(未示出),并且然后通过合适的工艺(诸如,光刻掩模和蚀刻)可去除材料层的部分,从而形成第二接触焊盘227。然而,可使用任意其他合适的工艺形成第二接触焊盘227。可形成厚度介于约0.5μm至约4μm之间(诸如,约1.45μm)的第二接触焊盘227。
第二钝化层225可在第二金属化层223和第二接触焊盘227上方形成在第二衬底221上。第二钝化层225可由诸如氧化硅、氮化硅、低k电介质(诸如碳掺杂氧化物)、极低k电介质(诸如多孔碳掺杂二氧化硅)的一种或多种合适的介电材料、它们的组合等制成。可通过诸如化学气相沉积(CVD)的工艺形成第二钝化层225(但是可使用任意合适的工艺),并且可具有介于约0.5μm至约5μm之间的厚度,诸如,约一旦处于合适位置,就可以通过诸如化学机械抛光(CMP)的工艺(但是也可使用任意合适的去除工艺)去除第二钝化层225的一部分,以暴露出第二接触焊盘227。
一旦第二半导体器件211已放置在通孔209之间,第二半导体器件211和通孔209就可由第二密封剂213密封。可在模制器件(未在图2A中单独示出)中实施密封。例如,第二半导体器件211和通孔209可放置在模制器件的空腔内,并且该空腔可气密密封。第二密封剂213可在空腔气密密封之前放置在空腔内或通过喷射口将第二密封剂213喷射到空腔内。在一个实施例中,第二密封剂213可以为模塑料树脂,如聚酰亚胺、PPS、PEEK、PES、耐热性水晶树脂、它们的组合等。
一旦已将第二密封剂213放置在模制空腔内使得第二密封剂213密封载体衬底201、通孔209、和第二半导体器件211,那么,第二密封剂213可固化以使第二密封剂213硬化来实现最佳保护。尽管准确的固化工艺至少部分地取决于为第二密封剂213选择的特定材料,但是,在选择模塑料用作第二密封剂213的实施例中,通过诸如将第二密封剂213加热到约100℃至约130℃之间的温度(诸如,约125℃)持续约60秒至约3000秒(诸如,600秒)的工艺可发生固化。此外,引发剂和/或催化剂可包含在第二密封剂213内以更好地控制固化工艺。
然而,作为本领域的技术人员会认识到,上述的固化工艺仅为示例性工艺且并不意味限制当前实施例。可以可选地使用诸如辐射或甚至允许第二密封剂213在环境温度下硬化的其他固化工艺。可使用任意合适的固化工艺,并且所有这样的工艺完全旨在包含于本文所讨论的实施例的范围内。
一旦已放置第二密封剂213,使第二密封剂213变薄以暴露出通孔209和,可选地,第二半导体器件211,以进行进一步的处理。例如使用机械研磨或化学机械抛光(CMP)工艺可实施变薄处理,在化学机械抛光中,使用化学蚀刻剂和研磨剂来反应且研磨掉第二密封剂213和第二半导体器件211,直至已经暴露出通孔209和第二半导体器件211。这样,第二半导体器件211和通孔209可具有与第二密封剂213同平面的平坦表面。
然而,尽管上述的CMP工艺表现为一个说明性实施例,但是,不应限制于这些实施例。可以可选地使用任意其他合适的去除工艺以使第二密封剂213和第二半导体器件211变薄和暴露出通孔209。例如,可以可选地使用一系列化学蚀刻。可以可选地使用该工艺和任意其他合适的工艺来使第二密封剂213和第二半导体器件211变薄,并且所有这样的工艺完全旨在包含于实施例的范围内。
使用第一重布层215来互连第二半导体器件211、通孔209和第一封装件100(参见图1)。在一个实施例中,通过诸如CVD或溅射的合适的形成工艺先由例如钛铜合金形成晶种层(未示出)从而形成第一重布层215。然后可形成光刻胶(也未示出)来覆盖晶种层,并且然后可图案化光刻胶以暴露出位于第一重布层215的期望所处位置的晶种层的部分。
一旦光刻胶已形成且被图案化,诸如铜的导电材料就可通过诸如电镀的沉积工艺形成在晶种层上。可形成厚度介于约1μm至约10μm之间(诸如约5μm)且宽度介于约5μm至约300μm之间(诸如约5μm)的导电材料。然而,虽然所讨论的材料和方法适用于形成导电材料,但是,这些材料仅为示例性的。可以可选地使用诸如AlCu或Au的任意其他合适的材料,以及诸如CVD或PVD的任意其他合适的形成工艺,并随后进行图案化工艺来形成第一重布层215。
一旦已形成导电材料,通过诸如灰化的合适去除工艺可去除光刻胶。此外,去除光刻胶之后,通过(例如)使用导电材料作为掩模的合适蚀刻工艺可去除晶种层的被光刻胶覆盖的部分。
一旦已形成第一重布层215,则形成第二接触焊盘217以将第一重布层215电互连接至例如第二外部连接件203。在一个实施例中,第二接触焊盘217类似于第一接触焊盘109(参照图1所述),诸如作为通过使用沉积工艺(诸如,溅射)形成、然后被图案化的铝接触焊盘。然而,可由任意合适的材料且使用任意合适的工艺形成第二接触焊盘217。
可在第一重布层215和第二接触焊盘217上方形成第一钝化层219,以便为第一重布层215和其他上覆结构提供保护和隔离。在一个实施例中,第一钝化层219可以为聚苯并恶唑(PBO),但是,可以可选地使用诸如聚酰亚胺或聚酰亚胺衍生物的任意合适的材料。使用例如旋转涂覆工艺可将第一钝化层219设置成厚度介于约5μm至约25μm之间(诸如约7μm),但是,可以可选地使用任意合适的方法和厚度。一旦设置在合适位置,通过诸如化学机械抛光(CMP)的工艺去除第一钝化层219的一部分可通过第一钝化层219暴露出第二接触焊盘217,但是,可以可选地使用任意合适的去除工艺。
形成与第二接触焊盘217连接的第二外部连接件203。在一个实施例中,第二外部连接件203类似于第一外部连接件113(参照图1所述),诸如作为接触凸块(诸如,微凸块或可控塌陷芯片连接(C4)凸块)。然而,任意其他合适类型的电连接件可以可选地用于第二外部连接件203。
图2B示出了形成第二封装件200的进一步处理。在一个实施例中,使用例如热工艺改变粘合层202的粘合属性来使载体衬底201和粘合层202与结构的剩余部分脱离粘合。在一个特定实施例中,使用诸如紫外线(UV)激光、二氧化碳(CO2)激光、或红外线(IR)激光的能量源辐射并加热粘合层202,直至粘合层202失去其至少一些的粘合属性。一旦实施,载体衬底201和粘合层202可物理分离且从结构上去除。
此外,一旦已经去除载体衬底201和粘合层202,可图案化聚合物层205以暴露出通孔209和第二接触焊盘227。在一个实施例中,通过先将光刻胶(未在图2B中单独示出)应用于聚合物层205,然后将光刻胶暴露于图案化能量源(例如,图案化光源)以诱导化学反应从而诱导暴露于图案化光源的光刻胶的部分的物理变化,以此来图案化聚合物层205。然后,根据期望的图案,将显影剂应用于曝光的光刻胶以利用物理变化且选择性地去除光刻胶的曝光部分或光刻胶的未曝光部分,并且使用例如干蚀刻工艺去除聚合物层205的下面的暴露部分。然而,可以可选地使用用于图案化聚合物层205的任意其他合适的方法。
图2B还示出了与通孔209和第二接触焊盘227电连接的第三金属化层233的形成,以将通孔209和第二接触焊盘227与例如诸如第二衬底401(未在图2B中示出,但在参照图4的下文中给出示出和描述)的外部器件互连。第三金属化层233由介电材料235和导电材料237的交替层形成,其中,导电材料237与通孔垂直互连且可通过任意合适的工艺(诸如,沉积、镶嵌、双镶嵌等)形成。在一个实施例中,可具有四层金属化层,但是,第三金属化层233的准确数量取决于第二封装件200的设计。
在一个实施例中,第二金属化层223被划分为三个不同区:信号区243、功率区245、和接地区247。信号区243,正如其名,包括用于携带信号至通孔209和第二半导体器件211以及携带来自通孔209和第二半导体器件211的信号的金属和通孔。在一个实施例中,设计和设定信号区243内的通孔和金属的尺寸以便为提供至通孔209和第二半导体器件211以及来自通孔209和第二半导体器件211的信号提供布线。例如,信号区243内的通孔可具有介于约5μm至约20μm之间(诸如,约20μm)的第一直径,而金属可具有介于约1.5μm至约5.0μm之间(诸如,2.0μm)的第一厚度。然而,可以可选地使用任意其他合适的尺寸。
功率区245,正如其名,包括用于将功率分布给第二半导体器件211的金属和通孔。此外,功率区245内的通孔和金属也将用作热导管以去除第二半导体器件211的热量。这样,可将功率区245内的通孔和金属的尺寸设定为不同于信号区243内的通孔和金属的尺寸,以适应额外的热传递。在一个实施例中,功率区245内的通孔可具有介于约5μm至约75μm之间(诸如,约60μm)的第二直径,而金属可具有介于约1.5μm至约5μm之间(诸如,约2μm)的第二厚度。然而,可以可选地使用任意其他合适的尺寸。
接地区247,正如其名,为第二半导体器件211提供接地电位。此外,在一个实施例中,接地区247还与功率区245协作使用以去除来自第二半导体器件211的热量。这样,可将接地区247内的通孔和金属的尺寸设定为与功率区245内的通孔和金属相似的尺寸,但是,根据需要,可以不同地设定它们的尺寸。
一旦已形成第二金属化层223,可形成第三接触焊盘249以在第三金属化层233和例如第二衬底401之间提供电连接。在一个实施例中,第三接触焊盘249与第一接触焊盘109(参见图1所述)相似。例如,第三接触焊盘249可以为使用沉积和图案化工艺形成的铝接触焊盘,但是可以可选地使用任意其他合适的工艺。
图3示出了第一封装件100和第二封装件200的粘合。在一个实施例中,通过先对准第一外部连接件113和第二外部连接件203可将第一封装件100接合至第二封装件200。一旦接触,可实施回流以回流第一外部连接件113和第二外部连接件203的材料,从而将第一封装件100物理和电接合至第二封装件200。然而,根据所选择的第一外部连接件113和第二外部连接件203的结构,可以可选地使用诸如铜-铜接合的任意其他合适的接合方法,并且所有这样的接合方法完全旨在包含于实施例的范围内。
图3还示出了连接于第三接触焊盘249的第三外部连接件301的形成。第三外部连接件301可以为诸如球栅阵列的接触凸块,但是,可以可选地使用诸如微凸块、C4凸块等的任意合适的形状和尺寸。在一个实施例中,第三外部连接件301包括诸如锡、银、或铜的材料,但是,可以可选地使用任意合适的材料。在第三外部连接件301是锡焊料凸块的实施例中,通过诸如蒸发、电镀、印刷、焊料转移、球置放等的任意合适的方法先形成厚度例如约为100μm的锡层,从而可形成第三外部连接件301。一旦在结构上已形成锡层,实施回流,以将材料成型为期望的凸块形状。
图4A示出了同时使用第四外部连接件405和第五外部连接件403(如图4A所示,已与第三外部连接件301接合)实现第二封装件200和第二衬底401的接合。在一个实施例中,第二衬底401可以例如为用于互连多种电组件以便为用户提供期望功能的印刷电路板。可选地,第二衬底401可以为另一个衬底且包括多个导电层(未单独示出),这些多个导电层中的一些为位于第二衬底401中的夹层。这些层可被蚀刻成各种宽度和长度的迹线并且通过夹层通孔连接。同时,线和通孔可形成电网以将来自第二衬底401的一侧的DC功率、接地和信号按线路发送至第二衬底401的另一侧。本领域的技术人员会认识到,第二衬底401可以由诸如双马来酰亚胺三嗪(BT)的有机(层压)材料、诸如液晶聚合物(LCP)的聚合物基材料、诸如低温共烧陶瓷(LTCC)的陶瓷材料、硅或玻璃插件等制造而成。本领域的技术人员还会认识到,导电层和通孔可以由诸如铜、铝、银、金、其他金属、合金的任意其他合适的导电材料、它们的组合等形成,并且通过任意合适的技术(诸如电化学镀(ECP)、无电镀)、其他沉积方法(诸如溅射、印刷、和化学气相沉积(CVD)方法)等形成。
在一些实施例中,第二衬底401可包括电元件,如电阻器、电容器、信号分布电路、它们的组合等。这些电元件可以是有源的、无源的、或它们的组合。在其他实施例中,第二衬底401的内部不具有有源和无源电元件。所有这样的组合完全旨在包含于实施例的范围内。
第二衬底401可包括第四接触焊盘407,以将第二衬底401电连接至例如第二封装件200。在一个实施例中,第四接触焊盘407可与第一接触焊盘109相似(参照图1所述)。例如,第四接触焊盘407可以为通过沉积和图案化工艺形成的铝接触焊盘。然而,第四接触焊盘407可以可选地与第一接触焊盘109不同。
在一个实施例中,可形成第五外部连接件403以在第四接触焊盘407和第三接触焊盘249之间提供外部连接。第五外部连接件403可以为诸如球栅阵列的接触凸块,但是,可以可选地使用诸如微凸块、C4凸块等的任意合适的形状和尺寸。在一个实施例中,第五外部连接件403包括诸如锡、银、或铜的材料,但是,可以可选地使用任意其他合适的材料。在第五外部连接件403是锡焊料凸块的实施例中,通过诸如蒸发、电镀、印刷、焊料转移、球置放等的任意合适的方法先形成厚度为(例如)约100μm的锡层,从而可形成第五外部连接件403。一旦在结构上形成锡层,实施回流,以使材料成型为期望的凸块形状。
第四外部连接件405用于电连接性和导热率。这样,第四外部连接件405具有不同于第五外部连接件403的物理属性。在一个实施例中,第四外部连接件405是一种导热率高于第五外部连接件403的材料,其允许热量从第二半导体器件211流经功率区245和接地区247以及第四外部连接件405。这样可以更好地去除第二半导体器件211的热量。
在一个特定实施例中,第四外部连接件405包括铜,但是,可以可选地使用诸如铝或金的任意其他合适的导电(电或热)材料。此外,在图4A公开的实施例中,由铜制成的第四外部连接件405成型为铜块,其具有介于约0.2mm至约50.0mm之间(诸如,约1.0mm)的第三宽度W3以及介于约0.2mm至约50.0mm之间(诸如,约1.0mm)的第一深度D1(未在图4A的截面图中示出,但被定位为进出图4A的页面,如图4B所示)。第四外部连接件405具有足以将第四接触焊盘407电且热连接至第三接触焊盘249的第一高度H1。这样,尽管第一高度H1的准确高度尺寸至少部分地取决于器件的整体设计,但是,在一个实施例中,第一高度H1可介于约0.1mm至约0.3mm之间,如,约0.16mm。
可选地,除了简单的导电块以外,第四外部连接件405可由其他材料形成。但是,可以可选地使用诸如导电箔(例如,铜箔)或导电浆(例如,铜浆)的任意合适的传导(电和热)型材料。所有这样的材料可完全旨在包含于实施例的范围内。
此外,第四外部连接件405不受限于上述和附图所示的块形状。但是,还可使用诸如圆形和多边形的任意合适形状、以及诸如星形、十字形或U形的其他不规则形状。所有这样的形成完全旨在包含于实施例的范围内。
在第四外部连接件405是铜块的实施例中,通过先将焊剂409放置在第四接触焊盘407上可将第四外部连接件405放置在第四接触焊盘407上。例如,通过刷涂、喷射、模板印刷(stencil)、或其他方法可应用焊剂409。焊剂409通常具有去除氧化阻挡物的酸性成分和有助于防止集成电路在工艺过程中移动的粘合性。焊剂409可同时放置在连接至第四接触焊盘407的第四外部连接件405以及第五外部连接件403上(为了清楚,未在图4A中示出),但是,根据需要,焊剂409可仅放置在连接至第四接触焊盘407的第四外部连接件405上、或它们的任意组合。
然而,尽管在该实施例中描述使用焊剂409,但是,也可以使用其他类型的材料来辅助第四外部连接件405和第四接触焊盘407之间的连接。可以可选地使用诸如焊料浆的任意其他合适的材料。所有这样的材料完全旨在包含于实施例的范围内。
一旦焊剂409设置在适当位置,使用(例如)拾放操作可物理放置第四外部连接件405以与焊剂409接触,但是,可以可选地使用任意合适的放置方法。一旦第四外部连接件405处于适当的位置,可将额外的焊剂409放置在第三接触焊盘249上并且可实施热工艺以接合第四外部连接件405与功率区245和接地区247内的第四接触焊盘407和第三接触焊盘249。在一个特定实施例中,热工艺可以是上述的回流工艺,以回流第五外部连接件403,但是,可以可选地使用单独的热工艺。这样,回流工艺将回流第五外部连接件403以及接合第四外部连接件405、第四接触焊盘407和第三接触焊盘249。
可选地,除了放置在第四接触焊盘407上外,第四外部连接件405可放置在第三接触焊盘249上,然后接合至第四接触焊盘407。可使用第四外部连接件405在第四接触焊盘407和第三接触焊盘249之间的任意合适的放置,并且所有这样的放置完全旨在包含于实施例的范围内。
图4B示出了第二衬底401、第五外部连接件403和第四外部连接件405的自上而下的展开图(具有附加的所示第五外部连接件403),为了方便用虚线框表示第二半导体衬底211。从该实施例可以看出,第四外部连接件405位于第二半导体衬底器件211的中心位置(当从该角度看时),而第五外部连接件403围绕第四外部连接件405以向第二半导体器件211提供信号连接性。
图4C示出了另一个实施例,其中,第四外部连接件405不是功率区245内的单独信号块和接地区247内的单独信号块,而是相反地被分成多个块,从而允许额外的设计灵活性。可以使用任意合适数量的第四外部连接件405,并且所有这样数量和组合完全旨在包含于实施例的范围内。
图5示出了在例如操作第二半导体器件211期间来自第二半导体器件211的热流501。在该实施例中,热量先产生在第二半导体器件211内,然后穿过功率区245和接地区247内的第三金属化层233,穿过第四外部连接件405、和第四接触焊盘407到达第二衬底401,在第二衬底401中,热量很容易被分散。通过快速去除第二半导体器件211的热量,实现较少的可产生有害影响(诸如,降低器件的整体性能,导致第二半导体器件211的单个元件在不同速率下膨胀,通过热膨胀系数的不同导致的意外应力)的热积聚。
图6示出了另一个实施例,在该实施例中,沟槽601形成在第四外部连接件405中以有助于补偿第四外部连接件405内的将在去除第二半导体器件211的热量期间产生的应力。在一个实施例中,沟槽601是位于第四外部连接件405内的开口,并且使用诸如形成期间的掩模和电镀、光刻掩模、以及形成后蚀刻等的工艺可形成。在一个实施例中,可形成具有介于约0.1mm至约0.3mm之间(诸如约0.2mm)的第二深度D2和介于约0.1mm至约0.3mm之间(诸如约0.2mm)的第四宽度W4的单独沟槽601。
此外,尽管图6示出了每个第四外部连接件405内具有三个沟槽601,但是,这旨在示出且并不旨在局限于这些实施例。相反,可以可选地使用任意合适数量(诸如约1个至16个之间)的沟槽601。沟槽601的所有合适数量和放置完全旨在包含于实施例的范围内。
图7示出了另一个实施例,在该实施例中,第四外部连接件405是导电球而不是导电块。在该实施例中,第四外部连接件405仍具有不同于第五外部连接件403的属性,并且可为例如铜球。在这种实施例中,以类似于参照图4A所述的方式将第四外部连接件405放置在第四接触焊盘407上,并且使用诸如回流的热工艺将第四外部连接件405接合至第四接触焊盘407和第三接触焊盘249。
图8示出了又一个实施例,在该实施例中,第四外部连接件405的放置位置(以及因此热流501(参见图5)的放置位置)没有限制在直接位于第二半导体器件211下方的区域。但是,第四外部连接件405可部分地形成在第二半导体器件211的下方并且部分地延伸远离第二半导体器件211的下方。这种设计允许更大的设计灵活性,同时仍允许热流501去除第二半导体器件的热量。
图8还示出了另一个实施例(单独使用或结合上述实施例使用),在该实施例中,第四外部连接件405(以及因此热流501(参见图5))完全从第二半导体器件211的下方去除。这种实施例允许更大的设计灵活性,同时仍保留第四外部连接件405能够去除第二半导体器件的热量的优势。
通过使用第四外部连接件405以将第二半导体器件211电且热连接至第二衬底401,可在期望的位置形成热去除路径,而在不存在热问题的区域内可使用诸如第五外部连接件403的其他连接件。这种组合允许在第二半导体器件211在启动期间(当第四外部连接件405具有更高的导热率时)以及在持续产生热量的持续操作期间(当第四外部连接件405将具有更高的热密度时)更快地去除第二半导体器件211的热量。这种快速去除使得因较高温度引起的缺点更少。
根据一个实施例,提供了一种包括第一封装件的半导体器件,该第一封装件包括被密封剂包围的第一半导体管芯以及穿过密封剂并且横向远离第一半导体管芯的通孔。第一衬底通过第一外部连接件和第二外部连接件接合至第一封装件,其中,第二外部连接件包括不同于第一外部连接件的材料。
根据另一个实施例,提供了一种包括集成扇出封装件的半导体器件。第一组外部连接件接合至集成扇出封装件的第一侧,并且第二组外部连接件接合至集成扇出封装件的第一侧,其中,第二组外部连接件具有高于第一组外部连接件的导热率。
根据再一个实施例,提供了一种制造半导体器件的方法,包括将第一组外部连接件放置在集成扇出封装件的第一侧。第二组外部连接件放置在集成扇出封装件的第一侧,其中,第二组外部连接件具有高于第一组外部连接件的导热率。衬底接合至第二组外部连接件和第一组外部连接件。
上面论述了若干实施例的部件,使得本领域的技术人员可以更好地理解本发明的各个方面。本领域的技术人员应该理解,可以很容易地使用本发明作为基础来设计或更改其他用于达到与这里所介绍实施例相同的目的和/或实现相同优点的工艺和结构。本领域的技术人员也应该意识到,这种等效构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,可以进行多种变化、更换以及改变。
Claims (10)
1.一种半导体器件,包括:
第一封装件,包括:
第一半导体管芯,被密封剂包围;以及
通孔,穿过所述密封剂并且横向远离所述第一半导体管芯;以及
第一衬底,利用第一外部连接件和第二外部连接件接合至所述第一封装件,其中,所述第二外部连接件包括不同于所述第一外部连接件的材料。
2.根据权利要求1所述的半导体器件,其中,所述第一外部连接件是焊料球并且所述第二外部连接件是铜块。
3.根据权利要求1所述的半导体器件,其中,所述第一外部连接件是焊料球并且所述第二外部连接件是铜球。
4.根据权利要求1所述的半导体器件,其中,所述第一外部连接件是焊料球并且所述第二外部连接件是铜箔。
5.根据权利要求1所述的半导体器件,其中,所述第二外部连接件完全位于所述第一半导体管芯的下方。
6.根据权利要求1所述的半导体器件,其中,所述第二外部连接件部分地位于所述第一半导体管芯的下方。
7.一种半导体器件,包括:
集成扇出封装件;
第一组外部连接件,接合至所述集成扇出封装件的第一侧;以及
第二组外部连接件,接合至所述集成扇出封装件的所述第一侧,其中,所述第二组外部连接件具有高于所述第一组外部连接件的导热率。
8.根据权利要求7所述的半导体器件,还包括第一衬底,所述第一衬底接合至所述第一组外部连接件和所述第二组外部连接件。
9.一种制造半导体器件的方法,所述方法包括:
将第一组外部连接件设置在集成扇出封装件的第一侧;
将第二组外部连接件设置在所述集成扇出封装件的所述第一侧,其中,所述第二组外部连接件具有高于所述第一组外部连接件的导热率;以及
将所述集成扇出封装件接合至所述第二组外部连接件和所述第一组外部连接件。
10.根据权利要求9所述的方法,其中,设置所述第二组外部连接件还包括将铜块设置在所述集成扇出封装件的第一侧。
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US11804475B2 (en) | 2023-10-31 |
US10163861B2 (en) | 2018-12-25 |
CN105280579B (zh) | 2018-12-21 |
US20210057387A1 (en) | 2021-02-25 |
US20190131280A1 (en) | 2019-05-02 |
US20160005716A1 (en) | 2016-01-07 |
US9449947B2 (en) | 2016-09-20 |
US10811389B2 (en) | 2020-10-20 |
US11594520B2 (en) | 2023-02-28 |
US20230207531A1 (en) | 2023-06-29 |
US20160358894A1 (en) | 2016-12-08 |
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