KR101070814B1 - 반도체패키지 및 그 제조방법 - Google Patents
반도체패키지 및 그 제조방법 Download PDFInfo
- Publication number
- KR101070814B1 KR101070814B1 KR1020100052401A KR20100052401A KR101070814B1 KR 101070814 B1 KR101070814 B1 KR 101070814B1 KR 1020100052401 A KR1020100052401 A KR 1020100052401A KR 20100052401 A KR20100052401 A KR 20100052401A KR 101070814 B1 KR101070814 B1 KR 101070814B1
- Authority
- KR
- South Korea
- Prior art keywords
- ground
- semiconductor
- substrate
- layer
- shielding
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73257—Bump and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
도 2는 본 발명의 다른 실시예 따른 반도체패키지 제조방법을 나타낸 순서도.
도 3 내지 도 8은 본 발명의 다른 실시예 따른 반도체패키지 제조방법을 설명하는 단면도.
15, 115: 접지회로
20, 120: 반도체칩
25, 125: 반도체 차폐층
30, 130: 접지층
40, 140: 몰딩부
50, 150: 차폐부
60, 160: 접속부
65, 165: 접지패턴
70: 전자소자
Claims (15)
- 접지회로가 형성되어 있으며, 일면에 반도체칩이 실장된 기판;
상기 기판의 타면에 형성되어 있으며, 상기 접지회로와 연결된 도전성의 접지층;
상기 반도체칩이 실장된 기판 및 상기 접지층을 밀봉시키는 몰딩부; 및
상기 몰딩부을 커버하고 있으며, 상기 접지층과 연결된 도전성의 차폐부를 포함하는 반도체패키지.
- 제1항에 있어서,
상기 기판의 접지회로 및 상기 차폐부와 연결된 접지패턴을 구비하고 있으며, 상기 차폐부의 외부로 연결된 접속부를 더 포함하는 반도체패키지.
- 제1항에 있어서,
상기 반도체칩의 상면에 형성되어 있으며, 상기 접지회로와 연결된 반도체 차폐층을 더 포함하는 반도체패키지.
- 제3항에 있어서,
상기 반도체 차폐층은 상기 차폐부와 연결된 것을 특징으로 하는 반도체패키지.
- 제4항에 있어서,
상기 차폐부와 상기 반도체 차폐층을 연결하는 도전성의 포스트를 더 포함하는 반도체패키지.
- 제3항에 있어서,
상기 반도체 차폐층과 상기 접지회로는 와이어본딩으로 연결된 것을 특징으로 하는 반도체패키지.
- 제1항에 있어서,
상기 접지회로와 연결된 접지전극을 구비한 전자소자를 더 포함하고,
상기 접지전극은 상기 차폐부와 연결된 것을 특징으로 하는 반도체패키지.
- 접지회로가 형성되어 있으며, 일면에 반도체칩이 실장된 기판을 제공하는 단계;
상기 기판의 타면에 상기 접지회로와 연결된 도전성의 접지층을 형성하는 단계;
상기 반도체칩이 실장된 기판 및 상기 접지층이 밀봉되도록 몰딩부를 형성하는 단계; 및
상기 몰딩부를 커버하며, 상기 접지층과 연결된 도전성의 차폐부를 형성하는 단계를 포함하는 반도체패키지 제조방법.
- 제8항에 있어서,
상기 접지층을 형성하는 단계는,
상기 기판의 타면에 접지회로를 노출시키는 비아홀을 형성하는 단계; 및
상기 기판의 타면에 도전성 물질을 도포하여, 상기 접지회로와 연결된 도전성의 접지층을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체패키지 제조방법.
- 제8항에 있어서,
상기 차폐부 형성단계는,
상기 몰딩부에 상기 반도체 차폐층이 노출되는 관통홀을 형성하는 단계; 및
상기 몰딩부에 도전성 물질을 도포하여, 상기 접지층과 연결된 도전성의 차폐부를 형성하는 단계를 포함하는 것을 특징으로 하는 반도체패키지 제조방법.
- 제8항에 있어서,
상기 접지층에 도전성 포스트를 형성하는 단계를 더 포함하고,
상기 차폐부 형성단계는,
상기 도전성 포스트와 연결된 차폐부를 형성하는 단계를 포함하는 것을 특징으로 하는 반도체패키지 제조방법.
- 제8항에 있어서,
상기 반도체칩의 상면에 반도체 차폐층을 형성하는 단계; 및
상기 반도체 차폐층과 상기 접지회로를 연결하는 단계를 더 포함하는 반도체패키지 제조방법.
- 제12항에 있어서,
상기 차폐부 형성단계는,
상기 반도체 차폐층과 연결된 차폐부를 형성하는 것을 특징으로 하는 반도체패키지 제조방법.
- 제12항에 있어서,
상기 접지회로 연결단계는,
상기 반도체 차폐층과 상기 접지회로를 와이어 본딩으로 연결하는 단계를 포함하는 것을 특징으로 하는 반도체패키지 제조방법.
- 제8항에 있어서,
접속부의 접지패턴이 상기 접지회로와 연결되도록, 상기 기판에 상기 접속부를 결합시키는 단계를 더 포함하고,
상기 차폐부 형성단계는,
상기 접지패턴과 연결된 차폐부를 형성하는 것을 특징으로 하는 반도체패키지 제조방법.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020100052401A KR101070814B1 (ko) | 2010-06-03 | 2010-06-03 | 반도체패키지 및 그 제조방법 |
US12/892,032 US9209101B2 (en) | 2010-06-03 | 2010-09-28 | Semiconductor package with a conductive shielding member |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020100052401A KR101070814B1 (ko) | 2010-06-03 | 2010-06-03 | 반도체패키지 및 그 제조방법 |
Publications (1)
Publication Number | Publication Date |
---|---|
KR101070814B1 true KR101070814B1 (ko) | 2011-10-06 |
Family
ID=45032435
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020100052401A KR101070814B1 (ko) | 2010-06-03 | 2010-06-03 | 반도체패키지 및 그 제조방법 |
Country Status (2)
Country | Link |
---|---|
US (1) | US9209101B2 (ko) |
KR (1) | KR101070814B1 (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20190003293A (ko) * | 2017-06-30 | 2019-01-09 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | 전자기 간섭에 대한 차폐부를 갖는 반도체 디바이스 |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20120228751A1 (en) * | 2011-03-07 | 2012-09-13 | Samsung Electronics Co., Ltd. | Semiconductor package and method of manufacturing the same |
US9030841B2 (en) * | 2012-02-23 | 2015-05-12 | Apple Inc. | Low profile, space efficient circuit shields |
TWI446514B (zh) * | 2012-06-14 | 2014-07-21 | 矽品精密工業股份有限公司 | 半導體封裝件及其製法 |
CN104218030B (zh) * | 2013-05-31 | 2017-09-26 | 日月光半导体制造股份有限公司 | 堆叠式多封装模块及其制造方法 |
CN106816431B (zh) * | 2015-11-30 | 2019-08-30 | 讯芯电子科技(中山)有限公司 | 一种电磁屏蔽封装结构及其制造方法 |
US11018040B2 (en) * | 2019-06-19 | 2021-05-25 | Amkor Technology Singapore Holding Pte. Ltd. | Carrier assisted substrate method of manufacturing an electronic device and electronic device produced thereby |
CN114430937A (zh) * | 2019-09-27 | 2022-05-03 | 株式会社村田制作所 | 电子部件模块 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6144101A (en) | 1996-12-03 | 2000-11-07 | Micron Technology, Inc. | Flip chip down-bond: method and apparatus |
JP2005072207A (ja) | 2003-08-22 | 2005-03-17 | Mitsubishi Electric Corp | マイクロ波増幅回路 |
KR100703090B1 (ko) | 2005-08-30 | 2007-04-06 | 삼성전기주식회사 | 후면 접지형 플립칩 반도체 패키지 |
WO2009122835A1 (ja) | 2008-03-31 | 2009-10-08 | 株式会社村田製作所 | 電子部品モジュール及び該電子部品モジュールの製造方法 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200834830A (en) * | 2007-02-06 | 2008-08-16 | Advanced Semiconductor Eng | Microelectromechanical system package and the method for manufacturing the same |
CN101663926B (zh) * | 2007-05-02 | 2011-10-05 | 株式会社村田制作所 | 部件内置模块及其制造方法 |
-
2010
- 2010-06-03 KR KR1020100052401A patent/KR101070814B1/ko active IP Right Grant
- 2010-09-28 US US12/892,032 patent/US9209101B2/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6144101A (en) | 1996-12-03 | 2000-11-07 | Micron Technology, Inc. | Flip chip down-bond: method and apparatus |
JP2005072207A (ja) | 2003-08-22 | 2005-03-17 | Mitsubishi Electric Corp | マイクロ波増幅回路 |
KR100703090B1 (ko) | 2005-08-30 | 2007-04-06 | 삼성전기주식회사 | 후면 접지형 플립칩 반도체 패키지 |
WO2009122835A1 (ja) | 2008-03-31 | 2009-10-08 | 株式会社村田製作所 | 電子部品モジュール及び該電子部品モジュールの製造方法 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20190003293A (ko) * | 2017-06-30 | 2019-01-09 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | 전자기 간섭에 대한 차폐부를 갖는 반도체 디바이스 |
KR102102733B1 (ko) | 2017-06-30 | 2020-04-22 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | 전자기 간섭에 대한 차폐부를 갖는 반도체 디바이스 |
US10867936B2 (en) | 2017-06-30 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with shield for electromagnetic interference |
US11527486B2 (en) | 2017-06-30 | 2022-12-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with shield for electromagnetic interference |
Also Published As
Publication number | Publication date |
---|---|
US9209101B2 (en) | 2015-12-08 |
US20110298102A1 (en) | 2011-12-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR101070814B1 (ko) | 반도체패키지 및 그 제조방법 | |
KR101897520B1 (ko) | 신뢰성을 가지는 반도체 패키지 및 이의 제조방법 | |
US8264070B2 (en) | Package structure with ESD and EMI preventing functions | |
US5436203A (en) | Shielded liquid encapsulated semiconductor device and method for making the same | |
US9111945B2 (en) | Package having ESD and EMI preventing functions and fabrication method thereof | |
US8241966B2 (en) | Methods of making an electronic component package and semiconductor chip packages | |
KR100431180B1 (ko) | 표면 탄성파 필터 패키지 제조방법 | |
US20100207257A1 (en) | Semiconductor package and manufacturing method thereof | |
US7566962B2 (en) | Semiconductor package structure and method for manufacturing the same | |
KR20080023996A (ko) | 반도체 패키지 | |
JP2012253190A (ja) | 半導体パッケージ及びその実装方法 | |
JP2007281129A (ja) | 積層型半導体装置 | |
KR101563910B1 (ko) | 반도체 패키지 및 이의 제조 방법 | |
KR20110020548A (ko) | 반도체 패키지 및 그의 제조방법 | |
CN101971486A (zh) | 半导体器件和具备该半导体器件的通信设备以及电子设备 | |
TWI332275B (en) | Semiconductor package having electromagnetic interference shielding and fabricating method thereof | |
KR101070799B1 (ko) | 반도체패키지 및 그 제조방법 | |
KR101101550B1 (ko) | 솔더 볼 및 반도체 패키지 | |
WO2020238773A1 (zh) | 一种封装结构及移动终端 | |
KR20150050189A (ko) | 반도체 패키지 | |
JP2010263108A (ja) | 半導体装置及びその製造方法 | |
TW201432865A (zh) | 晶片封裝結構及其製作方法 | |
JPH05129476A (ja) | 半導体装置およびその製造方法 | |
TWI423405B (zh) | 具載板之封裝結構 | |
TW201330220A (zh) | 具凹槽之封裝結構及其製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20140701 Year of fee payment: 4 |
|
FPAY | Annual fee payment |
Payment date: 20150707 Year of fee payment: 5 |
|
FPAY | Annual fee payment |
Payment date: 20160701 Year of fee payment: 6 |
|
FPAY | Annual fee payment |
Payment date: 20170703 Year of fee payment: 7 |
|
FPAY | Annual fee payment |
Payment date: 20180702 Year of fee payment: 8 |
|
FPAY | Annual fee payment |
Payment date: 20190701 Year of fee payment: 9 |