TW201724387A - 元件封裝體 - Google Patents

元件封裝體 Download PDF

Info

Publication number
TW201724387A
TW201724387A TW105133840A TW105133840A TW201724387A TW 201724387 A TW201724387 A TW 201724387A TW 105133840 A TW105133840 A TW 105133840A TW 105133840 A TW105133840 A TW 105133840A TW 201724387 A TW201724387 A TW 201724387A
Authority
TW
Taiwan
Prior art keywords
package
electromagnetic interference
layer
molding compound
die
Prior art date
Application number
TW105133840A
Other languages
English (en)
Inventor
陳威宇
陳憲偉
蘇安治
王若梅
楊天中
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201724387A publication Critical patent/TW201724387A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68313—Auxiliary support including a cavity for storing a finished device, e.g. IC package, or a partly finished device, e.g. die, during manufacturing or mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H01L2221/68331—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding of passive members, e.g. die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H01L2224/301—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一種元件封裝體包括一元件晶粒、環繞元件晶粒的一模塑化合物、貫穿模塑化合物的一導電內穿孔以及配置在模塑化合物上並沿著模塑化合物的多個側壁延伸的一電磁干擾屏蔽物。電磁干擾屏蔽物接觸導電內穿孔，且導電內穿孔電性連接電磁干擾屏蔽物至一外部連接端子。外部連接端子及電磁干擾屏蔽物配置於元件晶粒的相對兩側上。

Description

元件封裝體
本發明的實施例是有關於一種元件封裝體。
在傳統封裝技術方面，例如多層堆疊的扇出型封裝體(multi-stacked fan-out packages)、重佈線層(redistribution layers, RDLs)可形成於晶粒上並電性連接至晶粒中的主動元件。形成外部輸入/輸出(I/O)墊如凸塊下金屬(under-bump metallurgy, UBMs)上的焊球則可用以透過重佈線層電性連接至晶粒。此封裝技術的一個有利特徵為形成扇出封裝體的可能性。這代表晶粒上的輸入/輸出焊墊能夠被重新分佈至大於晶粒的範圍，因此可增加封裝在晶粒表面上的輸入/輸出焊墊數量。
在這種封裝技術中，模塑化合物可形成於晶粒的周圍，用以提供表面區域以支撐扇出型內連線結構。舉例而言，重佈線層通常包括一個或多個形成於晶粒及模塑化合物上的聚合物層。導電構件(例如導線及/或導通孔)形成在聚合物層中並且電性連接晶粒上的輸入/輸出焊墊至重佈線層上的外部輸入/輸出焊墊。外部輸入/輸出焊墊可配置於晶粒及模塑化合物上。
依據本發明的一實施例，元件封裝體包括一元件晶粒、環繞元件晶粒的一模塑化合物、貫穿模塑化合物的一導電內穿孔(through inter-via, TIV)以及配置在模塑化合物上並沿著模塑化合物多個側壁延伸的一電磁干擾(electromagnetic interference, EMI)屏蔽物。其中，導電內穿孔接觸電磁干擾屏蔽物，並電性連接電磁干擾屏蔽物至一外部連接端子，且其中外部連接端子和電磁干擾屏蔽物配置於元件晶粒的相對兩側上。
以下揭露內容提供用於實施所提供的標的之不同特徵的許多不同實施例或實例。以下所描述的構件及配置的具體實例是為了以簡化的方式傳達本揭露為目的。當然，這些僅僅為實例而非用以限制。舉例來說，於以下描述中，在第一特徵上方或在第一特徵上形成第二特徵可包括第二特徵與第一特徵形成為直接接觸的實施例，且亦可包括第二特徵與第一特徵之間可形成有額外特徵使得第二特徵與第一特徵可不直接接觸的實施例。此外，本揭露在各種實例中可使用相同的元件符號及/或字母來指代相同或類似的部件。元件符號的重複使用是為了簡單及清楚起見，且並不表示所討論的各個實施例及/或配置本身之間的關係。
另外，為了易於描述附圖中所繪示的一個構件或特徵與另一組件或特徵的關係，本文中可使用例如「在...下」、「在...下方」、「下部」、「在…上」、「上部」及類似術語的空間相對術語。除了附圖中所繪示的定向之外，所述空間相對術語意欲涵蓋元件在使用或操作時的不同定向。設備可被另外定向（旋轉90度或在其他定向），而本文所用的空間相對術語相應地作出解釋。
各種實施例包括堆疊在不同封裝層的多個元件晶粒(如邏輯晶粒(logic dies)、記憶體晶粒(memory dies)等)的元件封裝體。多個扇出型重佈線層(redistribution layers, RDLs)配置於多個晶粒之間，並提供多個晶粒之間的電性連接。導電內穿孔(through inter-vias, TIVs)亦可配置在每個封裝層中，並且扇出型重佈線層與導電內穿孔的結合提供從元件封裝體的第一側(例如具有外部連接端子(如焊球)的一側)至元件封裝體相對的另一側的電性連接。當電磁干擾(electromagnetic interference, EMI)屏蔽物形成於元件封裝體相對的一側上時，在每一層中的多個導電內穿孔提供從外部連接端子經由元件封裝體至電磁干擾屏蔽物的電性接地連接（electrical ground connection）。因此，已接地的電磁干擾屏蔽物可形成於多層的元件封裝體中。
圖1至圖13A為依據一些實施例所繪示製造元件封裝體180(詳見圖13A)的各種中間階段的剖視圖。首先，請參照圖1，圖1繪示一載板102。一般而言，載板102提供在後續製程步驟中各種構件(例如元件晶粒，詳見圖4)暫時性的機械及結構支撐。以此方式，可減少或防止元件晶粒的損傷。舉例而言，載板102可包括玻璃、氧化矽、氧化鋁等。
各種層膜可形成於載板102上。舉例而言，聚合物層104可形成於載板102上。聚合物層104可例如包括聚苯并噁唑(polybenzoxazole, PBO)。再者，聚合物層104是利於在後續的製程步驟中從封裝晶圓100移除載板102(如見圖1)。種子層(seed layer)106形成於聚合物層104上，且種子層106可包括導電材料，如銅。在一實施例中，種子層106利用濺鍍(sputtering)而形成。
圖1進一步地繪示已圖案化的光阻(photoresist)108形成於種子層106上。光阻108可利用光罩(未繪示)將光阻108曝露於光線(如紫外線)下而進行圖案化，以使光阻108包括多個開口110。移除光阻108的已曝光部分或未曝光部分，則可取決於利用正光阻(positive resist)或負光阻(negative resist)來形成多個開口110。多個開口110貫穿光阻108並曝露種子層106的多個部分。如圖2所示，多個開口110則可以導電材料112來填滿(例如以電化學電鍍(electro-chemical plating)製程、無電電鍍(electroless plating)製程等方式)。 再者，如圖3所示，在灰化(ashing)及/或濕式剝除(wet strip)製程中可移除光阻108，以將多個內穿孔114留在載板102上。舉例而言，亦可利用微影(photolithograph)及蝕刻移除種子層106多餘的部分(例如未被多個內穿孔114覆蓋的種子層106的部分)。在所產生的結構中，多個內穿孔114的頂部表面可實質上地被整平（level）或未整平。在完整的元件封裝體180中(詳見圖13B)，多個內穿孔114是用以電性連接形成在接地的封裝體上的電磁干擾屏蔽物。在一些實施例中，多個內穿孔114可具有約60微米(μm)或更大的間距P1。應注意的是，藉由提供具有較大尺寸(例如在上述的範圍內)的多個內穿孔，可改善後續形成的電磁干擾屏蔽物(例如電磁干擾屏蔽物140，詳圖12)的接地連接。然而，在其他的實施例中(例如具有成型因子(form factor)較小的實施例)，亦可形成較小的內穿孔114。
其次，在圖4中，多個晶粒200貼合於載板102以便進一步的製程。在一實施例中，晶粒貼合膜(die attach film)202是用以貼合多個晶粒200至載板102。晶粒貼合膜202可以為任何適當的黏著劑，例如紫外光膠(ultraviolet glue)或其他類似物。晶粒200可為半導體晶粒且可為任何種類的積體電路，例如處理器(processor)、邏輯電路系統(logic circuitry)、記憶體(memory)、類比電路(analog circuit)、數位電路(digital circuit)、混合訊號(mixed signal)等。晶粒200可包括基板、多個主動元件以及內連線結構(未單獨繪示)。舉例來說，基板可包括可以是摻雜或未摻雜的塊狀矽(bulk silicon)或絕緣體上矽(semiconductor-on-insulator, SOI)基板的主動層(active layer)。一般來說，絕緣體上矽基板包括形成於絕緣層上的半導體材料層，例如矽。絕緣層可例如為埋設氧化物(buried oxide, BOX)層或矽氧化物層。在基板上提供一絕緣層，基板例如為矽或玻璃基板。另外，基板可包括其他的基本半導體，例如鍺(germanium)、化合物半導體(包括碳化矽(silicon carbide)、砷化鎵(gallium arsenic)、磷化鎵(gallium phosphide)、磷化銦(indium phosphide)、砷化銦(indium arsenide)、及/或銻化銦(indium antimonide))、合金半導體(包括SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP)或上述之組合。亦可使用其他基板，例如多層基板或梯度基板(gradient substrates)。
主動元件例如電晶體、電容器、電阻器、二極體、光二極體(photo-diodes)、熔絲(fuses)等，可形成於基板的頂部表面。內連線結構可形成於多個主動元件及基板上。內連線結構可包括利用任何適當的方法形成含有導電構件(例如包括銅、鋁、鎢及其組合等的導線及導通孔)的層間介電層(inter-layer dielectric, ILD)及/或金屬層間介電層(inter-metal dielectric, IMD)。層間介電層及金屬層間介電層可包含低介電常數(low-k)的介電材料，其介電常數例如為大約低於4.0或甚至2.0，且配置於此類導電構件之間。舉例來說，在一些實施例中，層間介電層及金屬層間介電層可以由磷矽玻璃(phosphosilicate glass, PSG)、硼磷矽玻璃(borophosphosilicate glass, BPSG)、氟化矽玻璃(fluorosilicate glass, FSG)、碳氧化矽(SiOxCy)、旋塗玻璃(Spin-On-Glass)、旋塗聚合物(Spin-On-Polymers)、矽碳材料、其化合物、其複合物、其組合等，並透過任何適合的方法形成，例如旋塗(spinning)、化學氣相沉積(chemical vapor deposition, CVD)和電漿增強化學氣相沉積(plasma-enhanced CVD, PECVD)。內連線結構電性連接各種主動元件以在晶粒200中形成功能性的電路。此類電路所提供的功能可包括記憶體結構、處理結構（processing structure）、感測器、放大器、配電、輸入/輸出電路系統或類似的功能等。本發明所屬技術領域中具有通常知識者應可瞭解以上提供的例子是為了例示的目的，僅為了進一步解釋本發明的應用範圍，而不是為了以任何形態限制本發明的範圍。其他電路系統可在特定的應用上作適當的使用。
輸入/輸出(I/O)及鈍化構件(passivation features)可形成於內連線結構上。舉例來說，多個接墊204可形成於內連接結構上，並可透過在內連接結構中的各種導電構件電性連接至多個主動元件。接墊204可包括導電材料，例如鋁、銅等。另外，鈍化層(passivation layer)206可形成於內連接結構及多個接墊上。在一些實施例中，鈍化層206可由無機材料如二氧化矽、未摻雜的矽酸玻璃(un-doped silicate glass)、氮氧化矽(silicon oxynitride)等所形成，亦可使用其他適合的鈍化材料。鈍化層的多個部分可覆蓋多個接墊204的邊緣部分。
額外的多個內連線構件，如額外的鈍化層、導電柱及/或凸塊下金屬(under-bump metallurgy, UBM)層亦可選擇性地形成於多個接墊204上。舉例而言，如圖4所示，多個導電柱(conductive pillars)210可形成於多個接墊204上，並且電性連接至多個接墊204。再者，介電層208可形成在這些導電柱210的周圍。多個晶粒200的各種構件可由任何適合的方法所形成，於此不再贅述。另外，上述晶粒200的一般構件及配置僅為其中一實施例，晶粒200可包括上述構件或其他構件的任意數量的任意組合。
如圖5所示，多個晶粒200貼合至載板102後，模塑化合物116可形成於多個晶粒200及多個內穿孔114的周圍。模塑化合物116可包括任何適合的材料，如環氧樹脂(epoxy resin)、酚樹脂(phenol resin)、熱固型樹脂(thermally-set resin)等。除這些材料之外，模塑化合物116可包括或不包括各種添加劑填料(additive filler)，例如二氧化矽(silicon oxide)，氧化鋁(aluminum oxide)，氮化硼(boron nitride)等。形成模塑化合物116的適當方法可包括壓模成型(compressive molding)、轉注成型(transfer molding)、液體密封成型(liquid encapsulent molding)等。舉例來說，模塑化合物116是利用模壓工具(未繪示)成型或模壓，模壓工具在塗佈時，可具有邊界(border)或其他構件以保留模塑化合物116。模壓工具可用來在多個晶粒200/多個內穿孔114周圍分佈模塑化合物116，以使得模塑化合物116進入多個開口或多個凹陷(recess)中，或減少氣泡(air pockets)等。模塑化合物116可以液態分佈在多個晶粒202及多個內穿孔114的周圍。之後，進行固化步驟(curing process)，以固化模塑化合物116。
可形成模塑化合物116以初步地延伸過並覆蓋多個晶粒200及多個內穿孔114的頂部表面。接著，平坦化製程(planarization process)如機械研磨(mechanical grinding)、化學機械研磨製程(chemical mechanical polish, CMP)或其他蝕刻回蝕技術(etch back technique)可用於移除模塑化合物116在多個晶粒200上多餘的部分。在平坦化之後，曝露多個晶粒200的多個連接端子(例如多個導電柱210)，且可實質上地整平模塑化合物116的頂部表面、多個內穿孔114及多個晶粒200。在所產生的結構的俯視圖(未繪示)中，模塑化合物116可環繞(encircle)多個晶粒200與多個內穿孔114。
圖6繪示多個重佈線層118形成在模塑化合物116、多個內穿孔114與多個晶粒200上。多個重佈線層118可側向地延伸過多個晶粒200的邊緣至模塑化合物116的頂部表面。重佈線層118可包括形成在一個或多個聚合物層122中的多個導電構件120。聚合物層122可由任何適合的材料形成，例如聚醯亞胺(polyimide, PI)、聚苯并噁唑(polybenzoxazole, PBO)、苯環丁烷(benzocyclobuten, BCB)、環氧樹脂(epoxy)、矽、丙烯酸酯(acrylates)、奈米填充的酚醛樹脂(nano-filled pheno resin)、矽氧烷(siloxane)、氟化聚合物(fluorinated polymer)、降冰片烯高分子(polynorbornene)等，利用任何適當的方法，如旋塗式塗佈技術(spin-on coating technique)、層壓(lamination)等。
多個導電構件120(例如多個導線120A及/或多個導通孔120B)可形成在聚合物層122中，並電性連接至多個晶粒200(例如透過多個導電柱210)及多個內穿孔114。多個導電構件120的形成可包括圖案化聚合物層122(例如利用結合微影及蝕刻製程)並在已圖案化的聚合物層122上形成多個導電構件以及在已圖案化的聚合物層122中。舉例而言，導電構件120可進一步地包括沉積一種子層(未繪示)，利用具有各種開口以定義導電構件120形狀的罩幕層(未繪示)，以及利用如電化學電鍍製程填滿罩幕層(mask layer)中的多個開口。罩幕層及種子層多餘的部分則可予以移除。因此，多個重佈線層118形成在多個晶粒200以及模塑化合物116上。聚合物層的數量及重佈線層118的導電構件並不以圖6所繪示的實施例為限。舉例而言，重佈線層118在多個聚合物層中可包括任意數量堆疊且電性連接的多個導電構件。因此，第一封裝層(package tier)100A形成於封裝晶圓(package wafer)100中。第一封裝層100A包括多個晶粒200、多個內穿孔114、模塑化合物116及多個扇出型重佈線層118。
其次，在圖7中，第二封裝層100B形成於封裝晶圓100中的第一封裝層100A上。第二封裝層100B包括多個晶粒220、鄰近於多個晶粒220的多個內穿孔124、環繞多個晶粒220及多個內穿孔124的模塑化合物126以及形成於多個晶粒220、多個內穿孔124與模塑化合物126的多個扇出型重佈線層128。晶粒220、內穿孔124、模塑化合物126及重佈線層128可分別基本上類似於晶粒200、內穿孔114、模塑化合物116及扇出型重佈線層118，且可如上述基本上類似的方式形成。舉例而言，多個內穿孔124形成於多個重佈線層118上，且重佈線層118利用已圖案化的光阻(未繪示)以定義多個內穿孔124的形狀。多個晶粒220則可利用黏著層221貼合至多個內穿孔124之間的多個扇出型重佈線層118的頂部表面。晶粒200與220可具有相同或相異的功能。在一實施例中，晶粒200為動態隨機存取記憶體(dynamic random access memory, DRAM)晶粒，而晶粒220為系統晶片(system on chip, SoC)晶粒，但在其他實施例中，晶粒200與220可提供不同的功能。接著，模塑化合物126形成在多個晶粒220以及多個內穿孔124的周圍。再者，多個重佈線層128形成於模塑化合物126、多個內穿孔124及多個晶粒220上。在一些實施例中，舉例來說，額外的元件層(未繪示)包括半導體晶粒、內穿孔、扇出型重佈線層，其可選擇地形成在第二封裝層100B上。
在圖8中，額外的多個封裝構件如外部連接端子132(例如球柵式陣列(ball grid array, BGA)、控制塌陷高度晶片連接(controlled collapse chip connection, C4)凸塊等)可形成在多個重佈線層128上。多個連接端子132可配置在多個凸塊下金屬130上，其亦可形成在多個重佈線層128上。多個連接端子132可藉由重佈線層118及/或128電性連接至晶粒200與220。多個連接端子132可用以電性連接多個封裝體180(詳見圖13A)至其他封裝元件，例如另一個元件晶粒、中介層(interposers)、封裝基板(package substrates)、印刷電路板(printed circuit boards)、母板(mother board)等，且至少一組子連接端子132可用以電性連接多個內穿孔114至接地。其他的連接端子132可用以提供接地、電源及/或訊號線至晶粒200與220。
之後，如圖9所示，可移除載板102。如圖9中進一步地繪示元件封裝體的方向可顛倒以曝露聚合物層104，以便於後續的製程。在顛倒的方向中，多個連接端子132可貼附於暫時的支撐框架134(例如包括支撐膠帶)，以便進一步的製程。如圖10所示，後續的製程可包括透過聚合物層104曝露出多個內穿孔114。在一實施例中，藉由在聚合物層104中雷射蝕刻多個開口136以曝露出多個內穿孔114。如上所述，多個內穿孔114藉由多個重佈線層118、多個內穿孔124與多個重佈線層128電性連接至多個連接端子132。因此，藉由曝露出多個內穿孔114可提供電性連接路徑貫穿封裝晶圓100。亦可使用其他曝露內穿孔114的方法，如蝕刻回蝕製程或在形成內穿孔114之前，圖案化聚合物層104，將於後續段落中進一步地說明。
圖11至圖13A繪示形成電磁干擾屏蔽物與封裝體單體化。首先，在圖11中，進行切割製程(step cut process)，舉例來說，利用機械刀具(mechanical saw)沿著切割線(未繪示)，以在封裝晶圓100中將多個個別的封裝體180(包括多個晶粒200/220、相應的重佈線層118/128的部分、多個凸塊下金屬130及多個連接端子132)之間局部切割。切割製程形成在每一封裝體180之間延伸多個開口138。在一些實施例中，多個開口138僅局部貫穿封裝晶圓約至60微米或更小的深度D1。
其次，在圖12中，電磁干擾屏蔽物140如利用共形沈積製程(conformal deposition process)形成於封裝晶圓100的頂部表面上。在一實施例中，電磁干擾屏蔽物140包括導電材料，如鋁、銅、鈦、氮化鈦(titanium nitride)、鉭(tantalum)、氮化鉭(tantalum nitride)、鎢、金屬合金(例如不銹鋼)、其合金或其組合，且可藉由任何適當的製程(如、無電電鍍、濺鍍、化學氣相沉積等)沉積。在一些實施例中，電磁干擾屏蔽物140的厚度T1約為3微米至約10微米，但在其他實施例中，電磁干擾屏蔽物140可具有不同的厚度。電磁干擾屏蔽物140可至少局部配置於多個開口136中，多個開口136貫穿聚合物層104並接觸多個內穿孔114。電磁干擾屏蔽物140更可在個別的多個元件封裝體180中局部填滿多個開口138。因此，當個別的多個封裝體180完全的單體化後(詳見圖13A)，電磁干擾屏蔽物140可配置於已單體化的封裝體180的外側壁上。在電磁干擾屏蔽物140形成時，多個分散的屏蔽物(scatter shields)142可配置於封裝晶圓100的多個外圍區域，以防止(或減少)對支撐框架134的損傷。因此，在一些實施例中，在單體化前，電磁干擾屏蔽物140可不沿著封裝晶圓100的外側壁100’形成。隨後，可丟棄這些在晶圓的邊緣不具有電磁干擾屏蔽物140的封裝體180(亦可稱為缺陷晶粒(ugly die))。
接著，在圖13A中，個別的多個封裝體180可利用適合的晶粒切割技術沿著切割道(未繪示)進行單體化。舉例而言，將被多個開口138所曝露的剩餘封裝晶圓100的部分，以晶粒切割(die saw)切開。在單體化之後，例如用托盤144將多個封裝體180分類並儲存直到進行進一步的製程(例如接合(bonding)封裝體180至另一個封裝元件)。在完整的封裝體100的封裝層(如第一封裝層100A與第二封裝層100B)中，各種的內穿孔及重佈線層(例如內穿孔114、重佈線層118、內穿孔124及重佈線層128)提供從多個外部連接端子132至電磁干擾屏蔽物140通過封裝體180的電性接地路徑。因此，藉由在每一個封裝層中配置多個內穿孔，電磁干擾屏蔽物140在封裝體180中可接地。
另外，在圖13A中的封裝體180是利用兩個獨立的切割製程進行單體化。舉例來說，第一晶粒切割將封裝晶圓100局部切開(詳見圖11)，電磁干擾屏蔽物140形成於封裝晶圓100上(詳見圖12)。再者，第二晶粒切割將封裝體180由晶圓中的其他封裝體分離(詳見圖13A)。在這些實施例中，由於至少一部份的局部切割製程僅曝露每一個單一封裝體100的側壁而未曝露連接端子132，可減少形成電磁干擾屏蔽物140(如背側式分離沉積(backside scatter deposition))時對外部連接端子132所產生的損傷。
在另一實施例中，利用單一的晶粒切割製程可將封裝體180單體化，其可有利地減少製造成本。在此類實施例中，多個開口138可貫穿封裝晶圓100，且在單體化後，接著形成電磁干擾屏蔽物140於多個封裝體180的頂部表面及多個側壁上。圖13B繪示所產生的封裝體180’。如圖13B所示，電磁干擾屏蔽物140包括底部表面140A，其延伸過模塑化合物116/126與多個重佈線層118/128。相反地，在圖13A的元件封裝體180中，模塑化合物116與多個重佈線層128在電磁干擾屏蔽物140的底部表面140A下延伸。
圖14至圖15為依據另一實施例繪示在封裝晶圓300中形成電磁干擾屏蔽物。封裝晶圓300基本上可類似於封裝晶圓100，其中類似的圖式標號表示類似的元件。圖14的封裝體先前的製程步驟大致上可類似於圖1至圖9相關的描述內容。然而，在所繪示的實施例中，相較於利用雷射蝕刻以曝露多個內穿孔114，適合的蝕刻回蝕技術可用來移除聚合物層104(詳見圖9)並曝露多個內穿孔114。再者，如圖15所示，舉例來說，晶粒切割製程可沿著多個切割道進行，且電磁干擾屏蔽物140可沉積於封裝晶圓300上。因移除聚合物層104，電磁干擾屏蔽物140可與多個內穿孔114及模塑化合物116的頂部表面接觸。在此類實施例中，可實質上地整平電磁干擾屏蔽物140的頂部表面。雖然圖15繪示兩段式(two-step)封裝切割製程(如類似於圖11至圖13A所繪式的製程)，但其他的實施例可包括一段式(one-step)封裝切割製程(如類似於圖13B)。
圖16至圖21為依據另一實施例所繪示在封裝體400中形成電磁干擾屏蔽物。圖16繪示在形成任何的內穿孔(如內穿孔114)之前，聚合物層104及載板102的剖視圖。在圖16中，利用任何適合的製程，如微影及/或蝕刻進行圖案化聚合物層104，以使聚合物層104包括多個開口150。在形成多個內穿孔114或封裝體100的其他部分(如貼合晶粒200/220、形成模塑化合物116/126、形成多個扇出型重佈線層118/128或形成多個連接端子132)之前，可先圖案化多個開口150。其次，在圖17中，舉例來說，藉由濺鍍將種子層106形成於聚合物層104上。種子層106可延伸入在聚合物層中的多個開口150。
接著，在圖18中，已圖案化的光阻108形成於種子層106上。光阻108可藉由如上所述的微影進行圖案化，以使其包括多個開口110。多個開口110可與在聚合物層104中的多個開口150對齊。其次，在圖19中，多個開口110與150可以導電材料112來填滿(例如電化學電鍍製程、無電電鍍製程等)。再者，如圖20所示，在灰化(ashing)及/或濕式剝除(wet strip)製程中，可移除光阻108。將內穿孔114留在載板102上。舉例而言，亦可利用微影(photolithograph)及蝕刻移除種子層106多餘的部分(例如未被多個內穿孔114覆蓋的種子層106的部分)。在所產生的結構中，多個內穿孔114貫穿聚合物層104。
在多個內穿孔114形成後，可進行如有關圖4至圖13所述額外的製程。舉例而言，可利用貼合各種元件晶粒至載板104、密封(encapsulating)在模塑化合物中的多個晶粒/多個內穿孔、形成多個扇出型重佈線層、形成多個外部連接端子、單體化各種封裝體以及形成電磁干擾屏蔽物於封裝體的頂部表面與至少部分地沿著封裝體的多個側壁延伸來形成多個封裝層(例如第一/第二封裝層100A/100B)。所產生的元件封裝體400繪示於圖21中。如其所示，多個內穿孔114貫穿聚合物層104以電性連接電磁干擾屏蔽物140。在所產生的封裝體中，電磁干擾屏蔽物140的頂部表面可實質上地予以整平，且電磁干擾屏蔽物14可經由多個內穿孔114、多個重佈線層118、多個內穿孔114、多個重佈線層128與多個連接端子132電性連接至接地。
圖22為依據一些實施例所繪示形成元件封裝體的流程500。在步驟502中，多個內穿孔(如多個內穿孔114)形成於載板上的聚合物層(如聚合物層104)上。在步驟504中，各種封裝構件(例如元件晶粒200/220、模塑化合物116/126、內穿孔114/124、重佈線層118/128、外部連接端子132)亦形成在元件封裝體中。在步驟506中，移除載板並反轉元件封裝體的方向而曝露聚合物層。在步驟508中，經由聚合物層曝露多個內穿孔。曝露多個內穿孔可包括利用雷射蝕刻聚合物層、移除聚合物層(如利用蝕刻回蝕製程)或類似的製程。在另一實施例中，在形成多個內穿孔之前可先圖案化聚合物層，並且形成多個內穿孔以貫穿聚合物層。在此類實施例中，在步驟506(例如移除載板)可曝露多個內穿孔。在步驟510中，單體化封裝體並形成電磁干擾屏蔽物(如電磁干擾屏蔽物140)於已單體化的封裝體(無論是例如完全地單體化封裝體或是局部地單體化封裝體)的頂部表面上。電磁干擾屏蔽物可利用在封裝體中的多個內穿孔、各種重佈線層及多個外部連接端子電性連接至電性接地。
各種實施例包括堆疊在不同封裝層的多個元件晶粒的封裝體。多個扇出型重佈線層配置於多個晶粒之間，並提供所述多個晶粒之間的電性連接。導電內穿孔亦可配置在每個封裝層中，並且扇出型重佈線層與導電內穿孔的結合提供從元件封裝體的第一側(例如具有外部連接端子(如焊球)的一側)至元件封裝體相對的另一側(例如具有形成電磁干擾屏蔽物的一側)的電性連接。因此，已接地的電磁干擾屏蔽物可形成於多層的元件封裝體中。
在一實施例中，外部連接端子電性連接電磁干擾屏蔽物至接地。
在一實施例中，元件封裝體更包括配置在電磁干擾屏蔽物與元件晶粒之間的一聚合物層，其中導電內穿孔貫穿聚合物層。
在一實施例中，元件封裝體更包括配置在電磁干擾屏蔽物與元件晶粒之間的一聚合物層，其中電磁干擾屏蔽物貫穿聚合物層。
在一實施例中，電磁干擾屏蔽物接觸模塑化合物的一頂部表面。
在一實施例中，電磁干擾屏蔽物側向延伸過模塑化合物。
在一實施例中，元件封裝體包括一第一封裝層、在多個第一扇出型重佈線層上的一第二封裝層以及配置在第二封裝層上並沿著第二封裝層的多個側壁延伸的一電磁干擾屏蔽物。第一封裝層包括一第一元件晶粒、沿著第一元件晶粒的多個側壁延伸的一第一模塑化合物，貫穿第一模塑化合物的多個第一導電內穿孔以及在第一封裝層上的多個第一扇出型重佈線層。第二封裝層包括一第二元件晶粒、沿著第二元件晶粒的多個側壁延伸的一第二模塑化合物，以及貫穿第二模塑化合物的多個第二導電內穿孔。電磁干擾屏蔽物接觸多個第二導電內穿孔，且其中多個第一導電內穿孔、多個第一扇出型重佈線層以及多個第二導電內穿孔電性連接電磁干擾屏蔽物至接地。
在一實施例中，電磁干擾屏蔽物還接觸第二模塑化合物的一頂部表面。
在一實施例中，元件封裝體更包括在第二封裝層上的一聚合物層，其中電磁干擾屏蔽物貫穿聚合物層。
在一實施例中，元件封裝體更包括在第二封裝層上的一聚合物層，其中多個第二導電內穿孔貫穿聚合物層。
在一實施例中，元件封裝體更包括在第一封裝層下的多個第二重佈線層，以及在多個第二重佈線層下的多個外部連接端子，其中多個第二重佈線層與多個外部連接端子電性連接電磁干擾屏蔽物至接地。
在一實施例中，一種形成元件封裝體的方法包括在一載板上形成多個第一導電內穿孔、貼合一第一元件晶粒至載板，其中第一元件晶粒配置在相鄰的多個第一導電內穿孔之間、在第一元件晶粒及多個第一導電通孔周圍形成第一模塑化合物、曝露多個第一導電內穿孔、在第一元件晶粒上及沿著第一模塑化合物的多個側壁延伸形成一電磁干擾屏蔽物，且其中多個第一導電內穿孔電性連接電磁干擾屏蔽物至多個外部連接端子，而多個外部連接端子形成在第一元件晶粒作為電磁干擾屏蔽物的相對一側上。
在一實施例中，形成多個第一導電內穿孔包括在配置於載板上的一聚合物層上形成多個第一導電內穿孔。其中曝露多個第一導電內穿孔包括雷射蝕刻在聚合物層中的多個開口，且其中形成電磁干擾屏蔽物包括在聚合物層中的至少部分的多個開口中形成電磁干擾屏蔽物。
在一實施例中，形成多個第一導電內穿孔包括在配置於載板上的一聚合物層上形成多個第一導電內穿孔。其中曝露多個第一導電內穿孔包括移除聚合物層。
在一實施例中，形成元件封裝體的方法更包括圖案化在一聚合物層中的多個開口，而聚合物層配置在載板上。其中形成多個第一導電內穿孔包括形成多個第一導電內穿孔貫穿在聚合物層中的多個開口，且其中曝露多個第一導電內穿孔包括移除載板。
在一實施例中，形成元件封裝體的方法更包括在第一模塑化合物、第一元件晶粒與多個第一導電內穿孔上形成多個扇出型重佈線層、在多個扇出型重佈線層上形成外部連接端子以及在曝露多個第一導電內穿孔之前，反轉元件封裝體的方向。
在一實施例中，形成元件封裝體的方法更包括在多個扇出型重佈線層上形成多個第二導電內穿孔、在多個扇出型重佈線層上配置一第二元件晶粒，其中第二元件晶粒配置在相鄰的多個第二導電內穿孔之間、在第二元件晶粒與多個第二導電內穿孔的周圍形成第二模塑化合物，以及在第二模塑化合物、第二元件晶粒與多個第二導電內穿孔上形成額外的多個扇出型重佈線層，其中額外的多個扇出型重佈線層、多個第二內穿孔與多個扇出型重佈線層電性連接電磁干擾屏蔽物至外部連接端子。
在一實施例中，形成元件封裝體的方法更包括電性連接外部連接端子至接地。
在一實施例中，形成元件封裝體的方法更包括在形成電磁干擾屏蔽物之前，圖案化局部貫穿一封裝晶圓的一開口，而封裝晶圓包括元件封裝體，其中形成電磁干擾屏蔽物包括在開口中形成電磁干擾屏蔽物的部分。再者，在形成電磁干擾屏蔽物之後，從封裝晶圓中單體化元件封裝體。
在一實施例中，形成元件封裝體的方法更包括在形成電磁干擾屏蔽物時，配置分散的屏蔽物在封裝晶圓的邊緣上。
以上概述了數個實施例的特徵，使本領域具有通常知識者可更佳了解本揭露的態樣。本領域具有通常知識者應理解，其可輕易地使用本揭露作為設計或修改其他製程與結構的依據，以實行本文所介紹的實施例的相同目的及/或達到相同優點。本領域具有通常知識者還應理解，這種等效的配置並不悖離本揭露的精神與範疇，且本領域具有通常知識者在不悖離本揭露的精神與範疇的情況下可對本文做出各種改變、置換以及變更。
100、300‧‧‧封裝晶圓
100’‧‧‧側壁
100A‧‧‧第一封裝層
100B‧‧‧第二封裝層
102‧‧‧載板
104‧‧‧聚合物層
106‧‧‧種子層
108‧‧‧光阻
110、136、138、150‧‧‧開口
112‧‧‧導電材料
114、124‧‧‧導電內穿孔(TIVs)
116、126‧‧‧模塑化合物
118、128‧‧‧重佈線層
120‧‧‧導電構件
120A‧‧‧導線
120B‧‧‧導通孔
122‧‧‧聚合物層
130‧‧‧凸塊下金屬(UBM)
132‧‧‧連接端子
134‧‧‧框架
140‧‧‧電磁干擾屏蔽物
140A‧‧‧底部表面
142‧‧‧分散的屏蔽物
144‧‧‧托盤
180、180’、400‧‧‧元件封裝體
200、220‧‧‧晶粒
202‧‧‧晶粒貼合膜
204‧‧‧接墊
206‧‧‧鈍化層
208‧‧‧介電層
210‧‧‧導電柱
221‧‧‧黏著層
500‧‧‧流程
502、504、506、508、510‧‧‧步驟
D1‧‧‧深度
P1‧‧‧間距
T1‧‧‧厚度
從以下詳細說明配合所附的圖式，可對本揭露內容的各種觀點有較佳的理解。惟需留意的是，按照業界標準的做法，各種的特徵並未依比例繪製。事實上，為了討論清楚的緣故，各種的特徵的尺寸可任意放大或縮小。 圖1至圖13B為依據一些實施例所繪示製造元件封裝體的各種中間階段的剖視圖。 圖14至圖15為依據一些實施例所繪示製造元件封裝體的各種中間階段的剖視圖。 圖16至圖21為依據一些實施例所繪示製造元件封裝體的各種中間階段的剖視圖。 圖22為依據一些實施例所繪示製造元件封裝體的流程。
104‧‧‧聚合物層
114、124‧‧‧導電內穿孔(TIVs)
116、126‧‧‧模塑化合物
118、128‧‧‧重佈線層
132‧‧‧連接端子
140‧‧‧電磁干擾屏蔽物
140A‧‧‧底部表面
180’‧‧‧元件封裝體
220‧‧‧晶粒

Claims (1)

  1. 一種元件封裝體，包括: 一元件晶粒； 一模塑化合物，環繞該元件晶粒； 一導電內穿孔，貫穿該模塑化合物； 一電磁干擾屏蔽物，配置在該模塑化合物上並沿著該模塑化合物的多個側壁延伸，其中該導電內穿孔接觸該電磁干擾屏蔽物，並電性連接該電磁干擾屏蔽物至一外部連接端子，且其中該外部連接端子和該電磁干擾屏蔽物配置於該元件晶粒的相對兩側上。
TW105133840A 2015-10-20 2016-10-20 元件封裝體 TW201724387A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14/918,311 US9659878B2 (en) 2015-10-20 2015-10-20 Wafer level shielding in multi-stacked fan out packages and methods of forming same

Publications (1)

Publication Number Publication Date
TW201724387A true TW201724387A (zh) 2017-07-01

Family

ID=58524172

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105133840A TW201724387A (zh) 2015-10-20 2016-10-20 元件封裝體

Country Status (3)

Country Link
US (2) US9659878B2 (zh)
CN (1) CN106601716A (zh)
TW (1) TW201724387A (zh)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI666711B (zh) * 2017-12-08 2019-07-21 台灣積體電路製造股份有限公司 封裝體及其形成方法
US10361122B1 (en) 2018-04-20 2019-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Processes for reducing leakage and improving adhesion
US10418317B2 (en) 2017-10-26 2019-09-17 Samsung Electronics Co., Ltd. Fan-out semiconductor package
TWI685925B (zh) * 2017-09-27 2020-02-21 南韓商三星電子股份有限公司 扇出型半導體封裝
TWI689051B (zh) * 2017-12-20 2020-03-21 南韓商三星電子股份有限公司 扇出型半導體封裝
US10978408B2 (en) 2018-06-07 2021-04-13 Powertech Technology Inc. Semiconductor package and manufacturing method thereof
TWI727483B (zh) * 2019-08-22 2021-05-11 台灣積體電路製造股份有限公司 封裝及其製造方法
TWI737215B (zh) * 2019-04-29 2021-08-21 大陸商深超光電（深圳）有限公司 重佈線路結構的製備方法
TWI763198B (zh) * 2019-12-26 2022-05-01 台灣積體電路製造股份有限公司 製造半導體封裝的方法以及半導體封裝

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10325853B2 (en) 2014-12-03 2019-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor packages having through package vias
US20170040266A1 (en) * 2015-05-05 2017-02-09 Mediatek Inc. Fan-out package structure including antenna
US10043761B2 (en) * 2015-10-19 2018-08-07 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
US9659878B2 (en) * 2015-10-20 2017-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level shielding in multi-stacked fan out packages and methods of forming same
US10535611B2 (en) 2015-11-20 2020-01-14 Apple Inc. Substrate-less integrated components
WO2017093281A1 (en) * 2015-11-30 2017-06-08 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Electronic component packaged in component carrier serving as shielding cage
US10204883B2 (en) * 2016-02-02 2019-02-12 Taiwan Semidonductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
KR20170092309A (ko) * 2016-02-03 2017-08-11 삼성전기주식회사 양면 패키지 모듈 및 기판 스트립
KR101858952B1 (ko) * 2016-05-13 2018-05-18 주식회사 네패스 반도체 패키지 및 이의 제조 방법
US10068855B2 (en) * 2016-09-12 2018-09-04 Samsung Electro-Mechanics Co., Ltd. Semiconductor package, method of manufacturing the same, and electronic device module
US20180122777A1 (en) * 2016-10-31 2018-05-03 Raytheon Company Hybrid micro-circuit device with stacked chip components
KR102004801B1 (ko) * 2016-11-17 2019-07-29 삼성전기주식회사 팬-아웃 반도체 패키지
JP6815880B2 (ja) * 2017-01-25 2021-01-20 株式会社ディスコ 半導体パッケージの製造方法
CN109103167B (zh) * 2017-06-20 2020-11-03 晟碟半导体（上海）有限公司 用于存储器装置的异构性扇出结构
US10211072B2 (en) * 2017-06-23 2019-02-19 Applied Materials, Inc. Method of reconstituted substrate formation for advanced packaging applications
US10957611B2 (en) * 2017-08-01 2021-03-23 Mediatek Inc. Semiconductor package including lid structure with opening and recess
KR102442623B1 (ko) 2017-08-08 2022-09-13 삼성전자주식회사 반도체 패키지
US10420211B2 (en) * 2017-08-09 2019-09-17 Advanced Semiconductor Engineering, Inc. Semiconductor package device
CN107622957B (zh) * 2017-09-25 2019-11-01 江苏长电科技股份有限公司 双面SiP的三维封装结构的制造方法
KR101973446B1 (ko) * 2017-11-28 2019-04-29 삼성전기주식회사 팬-아웃 반도체 패키지
DE102018125372B4 (de) 2017-12-08 2021-11-11 Taiwan Semiconductor Manufacturing Co., Ltd. Elektromagnetischer abschirmungsaufbau in einem info-package und verfahren zu dessen herstellung
KR102455427B1 (ko) 2017-12-20 2022-10-17 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
US20190214367A1 (en) * 2018-01-10 2019-07-11 Powertech Technology Inc. Stacked package and a manufacturing method of the same
US10354978B1 (en) * 2018-01-10 2019-07-16 Powertech Technology Inc. Stacked package including exterior conductive element and a manufacturing method of the same
DE102018123492A1 (de) * 2018-03-26 2019-09-26 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleiterbauelement und herstellungsverfahren
US10937743B2 (en) * 2018-04-30 2021-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Mixing organic materials into hybrid packages
EP3939080A4 (en) * 2019-03-11 2023-01-11 HRL Laboratories, LLC PROCESS FOR PROTECTING A DIE DURING A METAL-EMBEDDED CHIP ASSEMBLY PROCESS (MECA)
US11728278B2 (en) * 2019-03-25 2023-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Board substrates, three-dimensional integrated circuit structures and methods of forming the same
KR20220027537A (ko) * 2020-08-27 2022-03-08 삼성전자주식회사 팬-아웃 타입 반도체 패키지
TWI749860B (zh) * 2020-11-10 2021-12-11 菱生精密工業股份有限公司 晶片封裝方法
CN112908869A (zh) * 2021-01-19 2021-06-04 上海先方半导体有限公司 一种封装结构及其制备方法

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040222511A1 (en) * 2002-10-15 2004-11-11 Silicon Laboratories, Inc. Method and apparatus for electromagnetic shielding of a circuit element
US7564115B2 (en) 2007-05-16 2009-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Tapered through-silicon via structure
US7973413B2 (en) 2007-08-24 2011-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate via for semiconductor device
US8227902B2 (en) 2007-11-26 2012-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Structures for preventing cross-talk between through-silicon vias and integrated circuits
US7843064B2 (en) 2007-12-21 2010-11-30 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and process for the formation of TSVs
US8278152B2 (en) 2008-09-08 2012-10-02 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding process for CMOS image sensor
US8178953B2 (en) * 2008-09-30 2012-05-15 Infineon Technologies Ag On-chip RF shields with front side redistribution lines
US7825024B2 (en) 2008-11-25 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming through-silicon vias
US8158456B2 (en) 2008-12-05 2012-04-17 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming stacked dies
US8378466B2 (en) * 2009-11-19 2013-02-19 Advanced Semiconductor Engineering, Inc. Wafer-level semiconductor device packages with electromagnetic interference shielding
US8183578B2 (en) 2010-03-02 2012-05-22 Taiwan Semiconductor Manufacturing Company, Ltd. Double flip-chip LED package components
US8183579B2 (en) 2010-03-02 2012-05-22 Taiwan Semiconductor Manufacturing Company, Ltd. LED flip-chip package structure with dummy bumps
US8426961B2 (en) 2010-06-25 2013-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded 3D interposer structure
US8581418B2 (en) 2010-07-21 2013-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-die stacking using bumps with different sizes
US8105875B1 (en) 2010-10-14 2012-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Approach for bonding dies onto interposers
US8872312B2 (en) * 2011-09-30 2014-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. EMI package and method for making same
US8803316B2 (en) 2011-12-06 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. TSV structures and methods for forming the same
US8803292B2 (en) 2012-04-27 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate vias and methods for forming the same
US9443783B2 (en) 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
JP6120528B2 (ja) 2012-11-08 2017-04-26 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US8802504B1 (en) 2013-03-14 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US9299649B2 (en) 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US8993380B2 (en) 2013-03-08 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D IC package
US9368455B2 (en) * 2014-03-28 2016-06-14 Intel Corporation Electromagnetic interference shield for semiconductor chip packages
US9236355B2 (en) * 2014-04-17 2016-01-12 Apple Inc. EMI shielded wafer level fan-out pop package
US9718678B2 (en) * 2014-09-25 2017-08-01 Infineon Technologies Ag Package arrangement, a package, and a method of manufacturing a package arrangement
US9437576B1 (en) * 2015-03-23 2016-09-06 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US9653407B2 (en) * 2015-07-02 2017-05-16 Advanced Semiconductor Engineering, Inc. Semiconductor device packages
US9461001B1 (en) * 2015-07-22 2016-10-04 Advanced Semiconductor Engineering, Inc. Semiconductor device package integrated with coil for wireless charging and electromagnetic interference shielding, and method of manufacturing the same
US9659878B2 (en) * 2015-10-20 2017-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level shielding in multi-stacked fan out packages and methods of forming same

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10672719B2 (en) 2017-09-27 2020-06-02 Samsung Electronics Co., Ltd. Fan-out semiconductor package
TWI685925B (zh) * 2017-09-27 2020-02-21 南韓商三星電子股份有限公司 扇出型半導體封裝
US10418317B2 (en) 2017-10-26 2019-09-17 Samsung Electronics Co., Ltd. Fan-out semiconductor package
US10950556B2 (en) 2017-12-08 2021-03-16 Taiwan Semiconductor Manufacturing Company, Ltd. EMI shielding structure in InFO package
US10468355B2 (en) 2017-12-08 2019-11-05 Taiwan Semiconductor Manufacturing Company, Ltd. EMI Shielding structure in InFO package
TWI666711B (zh) * 2017-12-08 2019-07-21 台灣積體電路製造股份有限公司 封裝體及其形成方法
US10699996B2 (en) 2017-12-20 2020-06-30 Samsung Electronics Co., Ltd. Fan-out semiconductor package
TWI689051B (zh) * 2017-12-20 2020-03-21 南韓商三星電子股份有限公司 扇出型半導體封裝
TWI690000B (zh) * 2018-04-20 2020-04-01 台灣積體電路製造股份有限公司 形成封裝體的方法
US10361122B1 (en) 2018-04-20 2019-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Processes for reducing leakage and improving adhesion
US10964591B2 (en) 2018-04-20 2021-03-30 Taiwan Semiconductor Manufacturing Company, Ltd. Processes for reducing leakage and improving adhesion
US11651994B2 (en) 2018-04-20 2023-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Processes for reducing leakage and improving adhesion
US12020983B2 (en) 2018-04-20 2024-06-25 Taiwan Semiconductor Manufacturing Company, Ltd. Processes for reducing leakage and improving adhesion
US10978408B2 (en) 2018-06-07 2021-04-13 Powertech Technology Inc. Semiconductor package and manufacturing method thereof
TWI737215B (zh) * 2019-04-29 2021-08-21 大陸商深超光電（深圳）有限公司 重佈線路結構的製備方法
TWI727483B (zh) * 2019-08-22 2021-05-11 台灣積體電路製造股份有限公司 封裝及其製造方法
US11417619B2 (en) 2019-08-22 2022-08-16 Taiwan Semiconductor Manufacturing Company Ltd. Package and manufacturing method thereof
TWI763198B (zh) * 2019-12-26 2022-05-01 台灣積體電路製造股份有限公司 製造半導體封裝的方法以及半導體封裝

Also Published As

Publication number Publication date
US9922939B2 (en) 2018-03-20
CN106601716A (zh) 2017-04-26
US9659878B2 (en) 2017-05-23
US20170110413A1 (en) 2017-04-20
US20170256502A1 (en) 2017-09-07

Similar Documents

Publication Publication Date Title
US9922939B2 (en) Wafer level shielding in multi-stacked fan out packages and methods of forming same
US11742220B2 (en) Integrated passive device package and methods of forming same
US11855045B2 (en) Semiconductor device with discrete blocks
KR102103531B1 (ko) 패키지 구조와 그 형성 방법
KR101786217B1 (ko) 팬-아웃 패키지 및 그 형성 방법
KR102367630B1 (ko) 통합 회로 패키지 및 방법
US10468377B2 (en) Device package including molding compound having non-planar top surface around a die
US9786617B2 (en) Chip packages and methods of manufacture thereof
TWI557820B (zh) 元件封裝及其形成方法
TWI575664B (zh) 封裝結構及其形成方法
TWI730879B (zh) 封裝結構及其製作方法
TW201814858A (zh) 半導體封裝件及其形成方法
US9385073B2 (en) Packages having integrated devices and methods of forming same
US9899288B2 (en) Interconnect structures for wafer level package and methods of forming same
KR102501418B1 (ko) 패키지 및 이의 형성 방법
US20220359465A1 (en) Package structures and method for forming the same
TW202335202A (zh) 裝置封裝及其製造方法
TWI853533B (zh) 封裝結構及其製造方法
US11830859B2 (en) Package structures and method for forming the same
US20240030186A1 (en) Package and manufacturing method thereof
US20230420331A1 (en) Semiconductor package and method
TW202435409A (zh) 封裝結構及其製造方法
KR20230165146A (ko) 반도체 패키지 및 그 형성 방법