TWI737215B - 重佈線路結構的製備方法 - Google Patents

重佈線路結構的製備方法 Download PDF

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TWI737215B
TWI737215B TW109107910A TW109107910A TWI737215B TW I737215 B TWI737215 B TW I737215B TW 109107910 A TW109107910 A TW 109107910A TW 109107910 A TW109107910 A TW 109107910A TW I737215 B TWI737215 B TW I737215B
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substrate
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林永富
陳柏良
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大陸商深超光電(深圳)有限公司
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Abstract

一種重佈線路結構的製備方法,包括:提供基板;在基板一側形成金屬層,金屬層包括控制線路,其用於後續能夠分區塊在基板上進行多次電鍍;在基板的表面上形成第一光阻層,該第一光阻層形成在未被金屬層覆蓋的區域;在金屬層與第一光阻層上形成絕緣層;在絕緣層中開孔以局部露出金屬層;在絕緣層遠離基板的一側形成種子層;形成區塊層以將種子層分隔成相互獨立的多個區塊;以及選擇對至少一個區塊進行電鍍形成電鍍層,經至少兩次電鍍至到所有的區塊完成電鍍。藉由在基板上進行分區塊電鍍形成電鍍線路層,可有效改善電鍍膜層的膜厚均勻度。

Description

重佈線路結構的製備方法
本發明涉及一種半導體封裝中使用的重佈線路結構的製備方法。
隨著各種電子元件(例如電晶體、二極體、電阻、電容等)的集成度持續地增加,半導體工業經歷了快速成長。集成度的增加是來自於最小特徵尺寸(feature size)不斷地縮減,以允許更多的較小元件整合到一給定區域內。較小的電子元件需要面積比以往的封裝更小的封裝。
目前,整合扇出型封裝由於其緊密度而趨於熱門,在整合扇出型封裝中,重佈線路結構的形成在封裝過程(尤其是扇出型面板級封裝)中扮演著重要的角色。一種現有的重佈線路的製備方法為在基板上進行電鍍得到。
本發明提供一種重佈線路結構的製備方法,包括:提供一基板並在所述基板的一表面上形成可剝離層;形成局部覆蓋所述可剝離層遠離所述基板的表面的金屬層,金屬層包括控制線路,所述控制線路包括至少兩個相互斷開的線路單元; 在所述可剝離層具有所述控制線路的表面上形成第一光阻層,該第一光阻層形成在未被控制線路覆蓋的區域;在所述控制線路與所述第一光阻層上形成絕緣層,該絕緣層完全覆蓋第一光阻層和控制線路;在所述絕緣層中開設多個通孔以露出局部的控制線路;在所述絕緣層遠離基板的一側形成線路化的且導電的種子層;在所述種子層上形成絕緣的區塊層,所述區塊層局部覆蓋所述種子層且將所述種子層分隔成相互隔離的多個區塊;以及藉由導通所述線路單元中的至少一個以選擇對至少一個區塊進行電鍍使所述種子層上層疊形成電鍍層,經至少兩次電鍍,至到所有的區塊都完成電鍍。
本發明藉由將重佈線路結構的電鍍劃分為若干區塊,每一次選擇性的對至少一個區塊進行電鍍,經多次電鍍完成所有區塊的電鍍,如此,每一個區塊的電鍍的膜厚均勻度相對提升,使得最終得到的所有的電鍍層具有相對更加均勻的膜厚度。
10:基板
11:可剝離層
20:金屬層
30:第一光阻層
40:絕緣層
41:通孔
50:種子層
60:區塊層
51:區塊
70:電鍍層
81:溝槽
80:第二光阻層
S1、S2、S3、S4、S5、S6、S7、S8:步驟
圖1是本發明較佳實施例的重佈線路結構的製備方法的流程圖。
圖2是本發明較佳實施例的重佈線路結構的製備方法之步驟S1的示意圖。
圖3是本發明較佳實施例的重佈線路結構的製備方法之步驟S2的示意圖。
圖4A和圖4B是本發明較佳實施例的重佈線路結構的製備方法之步驟S3的示意圖。
圖5是本發明較佳實施例的重佈線路結構的製備方法之步驟S4的示意圖。
圖6是本發明較佳實施例的重佈線路結構的製備方法之步驟S5的示意圖。
圖7是本發明較佳實施例的重佈線路結構的製備方法之步驟S6的示意圖。
圖8A和圖8B是本發明較佳實施例的重佈線路結構的製備方法之步驟S7的示意圖。
圖9是本發明較佳實施例的重佈線路結構的製備方法之步驟S8的示意圖。
圖10是本發明較佳實施例的重佈線路結構的製備方法之步驟S9的示意圖。
圖11是本發明較佳實施例的重佈線路結構的製備方法之步驟S10的示意圖。
附圖中示出了本發明的實施例,本發明可以藉由多種不同形式實現,而並不應解釋為僅局限於這裡所闡述的實施例。相反,提供這些實施例是為了使本發明更為全面和完整的公開,並使本領域的技術人員更充分地瞭解本發明的範圍。
重佈線路結構為半導體封裝中重要的元件,可用於半導體封裝中(尤其是扇出型面板級封裝)電性連接晶片與電路板。圖1為本發明較佳實施方式的重佈線路結構的製備方法的流程圖,圖2-圖11為本發明較佳實施方式的重佈線路結構的製備方法中各步驟的結構示意圖。
請參閱圖1,本發明較佳實施方式的重佈線路結構的製備方法包括如下步驟。
步驟S1:提供一基板並在基板的一表面上形成一可剝離層。
步驟S2:在可剝離層遠離基板的表面上形成金屬層。
步驟S3:在可剝離層形成有金屬層的表面上形成第一光阻層。
步驟S4:在金屬層和第一光阻層上形成絕緣層。
步驟S5:在絕緣層中開設多個通孔以露出局部的金屬層。
步驟S6:在絕緣層遠離基板的一側形成導電的種子層。
步驟S7:形成區塊層將該種子層分隔成相互獨立的多個區塊。
步驟S8:每一次選擇對至少一個區塊進行電鍍使種子層上形成電鍍層,經至少兩次電鍍,至到所有的區塊都完成電鍍。
步驟S1請參圖2所示。所述基板10為本領域習知使用的各種基板,其材質可為玻璃或者塑膠等有機材質。所述基板10可為柔性的,此情況下,基板10的材質為塑膠。所述可剝離層11可為本領域常規使用的各種能夠在鐳射或紫外光照等光能輻射下自基板10剝離的材料。例如,本實施例中,所述可剝離層11為在鐳射照射下可自基板10剝離的聚醯亞胺樹脂材料。如此,可在後續步驟中在可剝離層11上形成電路佈線之後,將電路佈線自基板10剝離,而基板10可重複使用。
步驟S2請參圖3所示。圖3僅簡單示出金屬層20所在的層。金屬層20為經圖案化的金屬層,其局部覆蓋可剝離層11遠離基板10的表面。金屬層20的設置是為了後續能夠分區塊在基板10上進行多次電鍍。金屬層20形成預設的控制線路,參圖4A所示。所述控制線路包括至少兩個相互斷開的線路單元。在後述的電鍍過程中,電鍍電極(圖未示)將電性連通局部的金屬層20並使局部的區域能夠進行電鍍而其他區域不進行電鍍。金屬 層20的材料可選自本領域常規使用的各種導電金屬,如銅、銅合金。金屬層20形成的控制線路不限於圖4A所示的交叉的格線路,還可為其他的各種線路,其線路圖案可以是規則的或者不規則的,只要起到能夠分區塊在基板10上進行多次電鍍即可。
步驟S3請參圖4B所示。該第一光阻層30形成在可剝離層11具有金屬層20的表面上未被金屬層20覆蓋的區域。相對第一光阻層30露出的金屬層20為控制線路,控制線路可包括導電線路和連接線路以控制分區塊電鍍。步驟S3具體可為:在可剝離層11形成有金屬層20的表面形成完全覆蓋基板10的光阻層(圖未示),對光阻層進行曝光顯影,去除部分的光阻層,剩餘的光阻層形成為第一光阻層30。本實施例中,第一光阻層30的厚度稍大於金屬層20的厚度。
步驟S2-S3的注意事項為:設計控制線路時需注意各區塊每一平方單位內控制線路的電流密度與均勻度基本相當(需相同或僅有微小差異);因每一個區塊的電流密度與均勻度會影響後續電鍍膜層厚度、膜均勻度和電鍍時間。
步驟S4請參圖5所示。該絕緣層40完全覆蓋該金屬層20和第一光阻層30遠離基板10的一側。
步驟S5請參圖6所示。在絕緣層40中開設通孔41露出金屬層20是為了使後續電鍍過程中電鍍電極接觸金屬層20的位置露出,保證電鍍能夠進行。依需求的不同,開設通孔41的位置和大小均可調整。不同區塊中開孔的孔徑可不同以調整電鍍時區塊內的電流密度(電流密度大小與電流強度、導電層的截面積相關)。本實施例中,開設通孔41的位置可對準為圖4A中金屬層20的導電線路的交叉點。
步驟S6請參圖7所示。種子層50可採用本領域常規使用的各種方式形成的導電層,包括化學氣相沉積法和物理氣相沉積法,物理氣相沉積法例如濺鍍。種子層50相對後續將形成的電鍍層厚度較薄。圖中僅示意性示出種子層50的層,實際上種子層50為線路化的,其形成為初始金屬重佈線,所述初始金屬重佈線具有與所需的重佈線路一致的圖案。
步驟S7請參圖8A和圖8B所示。本實施例中,所述區塊層60將該種子層50分隔成相互獨立的12個區塊51,如圖8A所示。後續將在每一個區塊51中形成的重佈線路。重佈線路包括種子層50和後續將鍍在種子層50上的電鍍層70。其中,每一個區塊51中的重佈線路不限於一個,即對應一個IC單元,還可包括多個重佈線路對應多個IC單元。
步驟S8請參圖9所示。每一次藉由導通所述線路單元中的至少一個以選擇對至少一個區塊進行電鍍。電鍍層70層疊形成在種子層50上,且對應形成為金屬重佈線。可以理解的,每一次電鍍對幾個區塊51進行電鍍可根據需要進行調整和設計。例如,一實施例中,第一次可對如圖8A中第一橫排的三個區塊51進行電鍍,此時,對應該三個區塊51的金屬層20的部分需保持通電以使電鍍能夠進行,而其他區塊51對應的金屬層20的其他部分不通電;第二次對第二橫排的三個區塊51進行電鍍;第三次對第三橫排的三個區塊51進行電鍍;第四次對第四橫排的三個區塊51進行電鍍。區塊51的電鍍安排和次序可根據需要進行調整設計。在另一實施例中,也可每一次僅對一個區塊51進行電鍍。
常規的一次性形成較大面積的電鍍層,電鍍層往往會呈現膜厚不均的現象(中間厚而邊緣相對較薄),本實施例中藉由將電鍍劃分為若干區塊,每一次選擇性的對至少一個區塊51進行電鍍,經多次電鍍完成所有 區塊的電鍍,如此,每一個區塊51的電鍍的膜厚均勻度相對提升,使得最終得到的所有的電鍍層具有相對更加均勻的膜厚度。
所述重佈線路結構的製備方法還可包括步驟S9和步驟S10(未示於圖1)。
步驟S9:去除區塊層以及位於其下方被其覆蓋的其他層的部分直至露出可剝離層。
步驟S10:在相互獨立的多個區塊之間形成第二光阻層,第二光阻層填充區塊之間的區域。
步驟S9請參圖10所示。如圖10所示,該步驟S9將形成溝槽81貫穿絕緣層40和第一光阻層30,如此得到相互獨立的多個區塊51。步驟S10請參圖11所示。
所述方法還包括參照上述步驟在電鍍層70上形成其他的電鍍層的步驟。
所述方法還包括完成電鍍後使用鐳射或紫外光照可剝離層11使其自基板10剝離的步驟。
參上所述,由於每一個區塊51中可包括對應多個IC單元的多個重佈線路,因此所述方法還包括對每一個區塊51中的重佈線路進行分割的步驟。本發明的重佈線路結構的製備方法藉由在基板上進行分區塊電鍍形成電鍍層,可有效改善電鍍膜層的膜厚均勻度。
以上實施例僅用以說明本發明的技術方案而非限制,圖示中出現的上、下、左及右方向僅為了方便理解,儘管參照較佳實施例對本發明進行了詳細說明,本領域的普通技術人員應當理解,可以對本發明的技術方案進行修改或等同替換,而不脫離本發明技術方案的精神和範圍。
S1、S2、S3、S4、S5、S6、S7、S8:步驟

Claims (8)

  1. 一種重佈線路結構的製備方法,其改良在於:其包括:提供一基板並在所述基板的一表面上形成可剝離層;形成局部覆蓋所述可剝離層遠離所述基板的表面的金屬層,所述金屬層包括控制線路,所述控制線路包括至少兩個相互斷開的線路單元;在所述可剝離層具有所述控制線路的表面上形成第一光阻層,該第一光阻層形成在未被所述控制線路覆蓋的區域;在所述控制線路與所述第一光阻層上形成絕緣層,該絕緣層完全覆蓋所述第一光阻層和所述控制線路;在所述絕緣層中開設多個通孔以露出局部的所述控制線路;在所述絕緣層遠離所述基板的一側形成線路化的且導電的種子層;形成絕緣的區塊層以將所述種子層分隔成相互隔離的多個區塊;以及藉由導通所述線路單元中的至少一個以選擇對至少一個區塊進行電鍍使所述種子層上層疊形成電鍍層,經至少兩次電鍍,至到所有的區塊都完成電鍍。
  2. 如請求項1所述的製備方法,其中,在所述絕緣層中開孔露出局部的所述金屬層用於使後續電鍍電極接觸所述控制線路的位置露出。
  3. 如請求項1所述的製備方法,其中,所述種子層形成為初始金屬重佈線,該初始金屬重佈線具有與所需的重佈線路一致的圖案。
  4. 如請求項3所述的製備方法,其中,每一個區塊中的所述種子層和電鍍層構成重佈線路,每一個區塊中的重佈線路的數量為多個。
  5. 如請求項1所述的製備方法,其中,各區塊中,每一平方單位內所述控制線路的電流密度與均勻度基本相當。
  6. 如請求項1所述的製備方法,其中,所述方法還包括去除所述區塊層以及位於所述區塊層下方被其覆蓋的其他層的部分直至露出所述可剝離層。
  7. 如請求項6所述的製備方法,其中,所述方法還包括在相互獨立的多個區塊之間形成第二光阻層,所述第二光阻層填充區塊之間的區域。
  8. 如請求項1所述的製備方法,其中,所述可剝離層為在鐳射或紫外光照下從所述基板剝離的材料。
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