CN113330562A - 用于高级封装应用的精密再分配互连形成的方法 - Google Patents

用于高级封装应用的精密再分配互连形成的方法 Download PDF

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CN113330562A
CN113330562A CN201980089669.3A CN201980089669A CN113330562A CN 113330562 A CN113330562 A CN 113330562A CN 201980089669 A CN201980089669 A CN 201980089669A CN 113330562 A CN113330562 A CN 113330562A
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copper
layer
molybdenum
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陈翰文
S·文哈弗贝克
曹圭一
P·利安托
徐源辉
V·迪卡普里奥
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Abstract

公开了一种用于使用钼粘附层将聚酰亚胺基板连接至铜晶种层和镀铜附件来制造电气部件的方法。

Description

用于高级封装应用的精密再分配互连形成的方法
背景技术
技术领域
本公开内容的实施例总体上涉及电气部件的封装。更具体地，本公开内容的各方面涉及用于在封装应用中的电子部件之间建立互连的精密再分配技术。
相关技术说明
随着时间的进展，对电子部件的高级封装的需求增加。诸如微电子之类的领域中的技术增长用于各种应用中，从智能电话、可穿戴装置、计算机和其他消耗性电子产品到汽车、交通、能源、航空航天和国防。展望未来，随着大数据的指数增长、物联网(IoT)的进化以及人工智能(AI)的发展，对提供可产生所需结果同时是能源高效且成本有效的更高效的微电子件的需求与日俱增。
尽管封装电子部件的常规方法在一年内是可以接受的，但是连续几年要求效率的大幅提高。作为非限制性实施例，用于电子部件的管芯尺寸基于定义为线/空间(L/S)的分辨率。所需分辨率的路线图正从嵌入式管芯应用的25/25μm减小到面板级封装中的小得多的15/15μm。
嵌入式芯片构造以外的技术的分辨率更加受限。对于有机面板中介层(interposer)技术而言，在未来几年中所需的分辨率将从10/10μm进展到2/2μm。当前使用的基于分辨率的技术无法生产未来的电子部件。
当前，在封装行业中，没有用于亚微米线/空间分辨率的成本有效的高密度再分配线技术。尽管确实存在诸如硅中介层的再分配层技术和嵌入式铜迹线技术之类的技术，但是这些类型的技术极其成本低效，并且不适用于大规模制造。
参考图1，呈现了再分配线技术的比较。对于硅中介层技术而言，适用的平台是晶片平台且最大的布线/毫米为1300(L/S.4/.4μm)。这样的硅中介层技术的成本较高，并且高频下的RF插入损耗相对较高。
进一步参考图1，嵌入式铜迹线使用具有保形晶种材料的聚合物。像硅中介层技术一样，嵌入式铜迹线技术也可以在晶片上使用，并且可以实现300(LS 2/1μm)的最大的布线/毫米。尽管嵌入式铜迹线技术的成本可能相对较低，但由于基于双重镶嵌的工艺流程，因此需要包括附加的步骤来移除铜覆盖层和晶种层。这样的增加的步骤数妨碍了生产的总体时间范围。在封装行业中采用非标准设备(即化学机械抛光(CMP)工具)以用于去除铜覆盖层和晶种层的必要性也限制了此方法的总体经济可行性。
对于所示的半加成工艺(Semi-Additive Process；SAP)Cu迹线技术，此类方法适用于晶片技术，并且可以以低成本实现500(L/S 1/1μm)的最大的布线/毫米。然而，SAP Cu迹线技术在高频下具有高RF插入损耗的显著缺点。主要的高密度再分配线技术中的每一者都至少具有一个主要缺点，从而阻碍了它们在对高密度封装的日益增长的需求中的使用。
需要提供将提供未来所需的分辨率趋势(线/空间)的技术。
这些技术对于大规模生产设施应是高效的，并且对于未来的生产需求应是经济的。
发明内容
在一个示例实施例中，公开了一种用于制造电气部件的方法，包括：提供聚酰亚胺基板；用包含钼的粘附层涂覆聚酰亚胺基板的至少一侧；用铜晶种层涂覆粘附层；用光刻胶涂层覆盖铜晶种层的至少一部分；移除光刻胶涂层的一部分以产生表面特征；执行镀铜工艺，其中表面特征填充有铜；移除光刻胶以产生铜表面；在铜表面上执行铜晶种层蚀刻以产生铜蚀刻表面；以及在铜蚀刻表面上执行粘附层蚀刻。
在另一个示例实施例中，公开了一种用于制造电气部件的方法，包括：提供具有含钼的粘附层和铜晶种层的聚酰亚胺基板；用光刻胶涂层覆盖铜晶种层的至少一部分；通过掩模将光刻胶涂层暴露于辐射源；移除光刻胶涂层的一部分以产生从掩模转移的表面特征；执行镀铜工艺，其中表面特征填充有铜；移除光刻胶以产生铜表面；在铜表面上执行铜蚀刻以产生铜蚀刻表面；以及在铜蚀刻表面上执行粘附层蚀刻。
在另一个示例实施例中，公开了一种布置，包括：具有第一表面的聚酰亚胺基板；连接至第一表面的钼粘附层；连接至钼粘附层的铜晶种层；以及连接至铜晶种层的铜层。
附图说明
为了可以详细地理解本公开内容的上述特征的方式，可以通过参考实施例来对以上简要概述的本发明进行更具体的描述，所述实施例中的一些实施例在附图中示出。然而，应注意，附图仅示出了示例性实施例，并且因此不应视为对其范围的限制，并且可允许其他等效的实施例。
图1是现有技术的高密度再分配线技术以及此类技术的局限性的表格。
图2A、图2B、图2C、图2D、图2E与图2F为硅中介层技术的现有技术工艺。
图3A、图3B、图3C、图3D、图3E与图3F是嵌入式铜迹线技术的现有技术工艺。
图4提供了一种在粘附层中使用钼来创建镀铜和晶种层蚀刻的方法。
图5A、图5B、图5C、图5D、图5E与图5F描述钛和钼粘附层的优点和缺点。
为了便于理解，在可能的情况下使用相同的附图标记来表示附图中共有的相同元素。可以预期的是，一个实施例的元素和特征可以有益地并入其他实施例中，而无需进一步叙述。
具体实施方式
在下文中，参考本公开内容的实施例。然而，应当理解，本公开内容不限于具体描述的实施例。相反，考虑以下特征和元素的任何组合，而无论是否与不同的实施例相关，以实现和实践本公开内容。此外，尽管本公开内容的实施例可以实现优于其他可能的解决方案和/或优于现有技术，但是通过给定的实施例是否实现特定优点并不限制本公开内容。因此，以下方面、特征、实施例和优点仅是示例性的，并且不被认为是所附权利要求的要素或限制，除非在权利要求中明确叙述。同样，对“本公开内容”的引用不应被解释为本文所公开的发明主题的概括，并且除非在权利要求中明确叙述，否则不应被认为是所附权利要求的要素或限制。
现在将参考附图描述一些实施例。为了一致性，在各个附图中，相同的元素将用相同的数字表示。在以下描述中，阐述了许多细节以提供对各种实施例和/或特征的理解。然而，本领域技术人员将理解，可以在没有许多这些细节的情况下实践一些实施例，并且可以对所描述的实施例进行多种变化或修改。如本文中所使用的，指示在给定点或元素的上方或下方的相对位置的术语“上方”和“下方”、“上(up)”和“下(down)”、“上(upper)”和“下(lower)”、“向上”和“向下”以及其他类似的术语在本说明书中用于更清楚地描述某些实施例。
图2A至图2F示出了用于使用硅中介层技术的现有技术方法。在图2A中，硅晶片呈现为具有从顶侧的蚀刻特征。在图2B中，执行电介质制造步骤，将电介质放置在晶片的蚀刻特征的顶层上。在图2C中，将阻挡/粘附层与晶种层放置在介电层上。在图2D中，发生电镀步骤，填充从蚀刻特征中剩余的特征。还产生来自电镀的过填充层。在图2E中，发生过量的过填充层的移除。最后，在图2F中，可以使用诸如研磨或蚀刻之类的机械方法来移除晶片的底层，从而产生最终产品。如图1所列出的，除了所需设备的大量资本支出外，采用深反应性离子蚀刻(DRIE)的普通Bosch工艺的慢的硅蚀刻速率以及将通孔与周围的硅绝缘所涉及的附加步骤的复杂性，导致制造成本高昂。
参考图3A至图3F，示出了用于使用嵌入式铜迹线技术的现有技术方法。在图3A中，硅晶片呈现为具有介电层，所述介电层具有由第一光刻工艺创建的表面特征。在图3B中，执行第二光刻工艺以提供介电层上的进一步表面特征化。在图3C中，通过物理气相沉积(PVD)溅射阻挡/晶种层。在图3D中，通过电化学电镀(ECP)在特征中填充铜层。图3D中提供的铜层具有覆盖层，所述覆盖层与过量的阻挡/晶种层一起随后在图3E中通过化学机械抛光(CMP)去除。如图3F所示，可以对连续再分配层(RDL)堆叠重复此工艺。如图1所示，通过CMP进行对铜覆盖层的重复消除对此方法的总成本具有不利影响。然而，这种基于铜双重镶嵌的RDL方案的最大布线/毫米受到与厚电介质膜的均匀性、CMP平坦化质量以及制造期间的清洁度条件妥协的光刻能力的分辨率和焦点深度的限制。
参考图4，提供了一种在介电层(基板)上使用镀铜和使用伴随有钼粘附层的晶种层的方法。钼可以是二硫化钼的形式。介电层可以是旋涂、沉积或干式膜或基板的形式，并且可包括诸如聚酰亚胺、环氧树脂、带填料的环氧树脂、Kaptrex、Apical、Kapton、UPILEX之类的材料或其他类似材料。在操作1中，提供介电层400作为基板。为了使布置的其余部分能够黏附到聚酰亚胺层上，提供了粘附层402，其中所述粘附层具有钼。粘附层402可以溅射到介电层400的顶部上，作为提供粘附层402的非限制性方式。在粘附层402上还提供了铜晶种层404。在铜晶种层上设置光刻胶408的表面层。可以通过掩模410将光刻胶层408图案化到足够的量，以形成用于电处理的期望图案的模板。
光刻胶层408可以是正光刻胶层，使得当抗蚀剂暴露于光时，经历光的部分可溶于光刻胶显影剂(如稍后在操作3中所述)。作为非限制性实施例，这样的图案化可以通过光刻来执行。如将理解的，光刻可以产生简单的配置或可以产生显著复杂的布置。在操作2中，发生镀铜，从而填充布置的图案化表面，由此产生的布置从底部延伸到顶部为：介电层400、粘附层402、铜晶种层404、以及在铜晶种层404上的光刻胶408和铜结构406的层。操作2可以通过以下方式来执行：将整个布置放置在具有直流电的浴液中进行电解，以从铜金属棒中溶解铜，从而将铜离子从棒通过浴液传输到阴极(布置的暴露区域)。
在操作3中，从布置的顶部剥离光刻胶408，使铜的顶部和侧面与铜晶种层404一起暴露。在操作4中，在暴露的铜顶部和侧面以及铜晶种层404之上执行湿法蚀刻以移除铜的表面层，以暴露未被铜结构406覆盖的粘附层402的部分。最后，在操作5中，执行进一步的湿法蚀刻以移除粘附层402未被铜结构406覆盖的部分，从而得到最终产品。
如上所述，湿法蚀刻可使用液相蚀刻剂。作为示例实施例，可以将布置浸入蚀刻剂的浴液中。在浸没期间，可以搅拌或搅动液相蚀刻剂以在所需表面上执行均匀蚀刻。
图4中提供的方法提供优于图5A-5F所示的常规技术的许多优点。参考图5A-5F，在粘附层中使用钛时，朝向与介电层的界面去除钛越来越困难。为此，在图5A中需要过度蚀刻以确保完全移除钛粘附层，与之相比，图5D中可以轻松移除含钼的粘附层而无需过度蚀刻。这样的过度蚀刻会导致生产结果与设计特征不符。参考图5B，电介质表面上残留的钛导致表面泄漏电流，与之相比，图5E中当使用包含钼的粘附层时，在阻挡/晶种蚀刻之后没有金属残留物。参考图5C，钛的电阻率值为420nΩ·m，与之相比，图5F中钼的电阻率值为53.4nΩ·m。钼的固有电阻率比钛的固有电阻率低一个数量级，从而改善了器件的电气性能。
所述方法允许实现先前无法实现的分辨率，而没有此类常规方法的严重缺陷。使用钼不需要过度蚀刻，因此可以最小化底切。使用常规的钛层需要大的过度蚀刻以完全移除，这会导致铜结构下方的底切，从而引起封装的电气和可靠性问题。此外，残留的钛对电介质的接触会导致表面泄漏电流，从而使设计效率最小化。在使用钼的情况下，不会发生这种表面泄漏。与钛相比，钼层的使用还提供了低电阻，从而提供了更好的电接触。与钛布置相比，钼的使用还提供了优异的翘曲调制。
本公开内容的各方面还允许最小化粘附层底切。这样的底切的最小化允许亚微米线/间距和较厚的阻挡晶种沉积来补偿底层粗糙度。这样的配置使得能够在大型基板/面板上进行半加成工艺。
在本公开内容的一个非限制性示例实施例中，公开了一种用于制造电气部件的方法，所述方法包括：提供聚酰亚胺基板；用包含钼的粘附层涂覆聚酰亚胺基板的至少一侧；用铜晶种层涂覆粘附层；用光刻胶涂层覆盖铜晶种层的至少一部分；移除光刻胶涂层的一部分以产生表面特征；执行镀铜工艺，其中表面特征填充有铜；移除光刻胶以产生铜表面；在铜表面上执行铜蚀刻以产生铜蚀刻表面，并在铜蚀刻表面上执行粘附层蚀刻。
在另一个示例实施例中，可以执行所述方法，其中铜蚀刻是湿法铜蚀刻。
在另一个示例实施例中，可以执行所述方法，其中通过光刻胶显影剂移除光刻胶涂层的部分。
在另一个示例实施例中，可以执行所述方法，其中聚酰亚胺基板为Kaptrex、Apical、Kapton与UPILEX中的一者。
在另一个示例实施例中，可以执行所述方法，其中通过溅射工艺在聚酰亚胺基板的至少一侧上涂覆包含钼的粘附层。
在另一个示例实施例中，可以执行所述方法，其中溅射工艺由磁控管产生。
在另一个示例实施例中，可以执行所述方法，其中钼为二硫化钼。
在另一个示例实施例中，公开了一种用于制造电气部件的方法。在此方法中，所述制造包括：提供具有含钼的粘附层和铜晶种层的聚酰亚胺基板；用光刻胶涂层覆盖铜晶种层的至少一部分；通过掩模将光刻胶涂层暴露于辐射源；移除光刻胶涂层的一部分以产生从掩模转移的表面特征；执行镀铜工艺，其中表面特征填充有铜；移除光刻胶以产生铜表面；在铜表面上执行铜蚀刻以产生铜蚀刻表面；以及在铜蚀刻表面上执行粘附层蚀刻。
在另一个示例实施例中，可以执行所述方法，其中铜蚀刻为湿法铜蚀刻。
在另一个示例实施例中，可以执行所述方法，其中通过光刻胶显影剂移除光刻胶涂层的部分。
在另一个示例实施例中，可以执行所述方法，其中聚酰亚胺基板为Kaptrex、Apical、Kapton与UPILEX中的一者。
在另一个示例实施例中，可以执行所述方法，其中通过溅射工艺在聚酰亚胺基板的至少一侧上涂覆包含钼的粘附层。
在另一个示例实施例中，可以执行所述方法，其中溅射工艺由磁控管产生。
在另一个示例实施例中，可以执行所述方法，其中钼为二硫化钼。
在另一个示例实施例中，可以执行所述方法，其中执行镀铜工艺，其中表面特征通过电解被填充有铜。
在另一个示例实施例中，公开一种布置，所述布置包括：具有第一表面的聚酰亚胺基板；连接至第一表面的钼粘附层；连接至钼粘附层的铜晶种层；以及连接至铜晶种层的铜层。
在另一个示例实施例中，所述布置可配置为其中晶种层为铜晶种层。
在另一个示例实施例中，所述布置可配置为其中铜层具有线空间封装比率小于10/10μm的特征。
在另一个示例实施例中，所述布置可配置为其中铜层具有线空间封装比率小于5/5μm的特征。
在另一个示例实施例中，所述布置可配置为其中铜层具有线空间封装比率小于2/2μm的特征。
尽管本文中已经描述了实施例，但是受益于本公开的本领域技术人员将理解，设想了不背离本申请案的发明范围的其他实施例。因此，本权利要求或任何后续相关权利要求的范围不应受到本文所述实施例的描述的过度限制。

Claims (15)

1.一种用于制造电气部件的方法，包括：
提供聚酰亚胺基板；
用包含钼的粘附层涂覆所述聚酰亚胺基板的至少一侧；
用铜晶种层涂覆所述粘附层；
用光刻胶的涂层覆盖所述铜晶种层的至少一部分；
移除所述光刻胶的所述涂层的一部分以产生表面特征；
执行镀铜工艺，其中所述表面特征填充有铜；
移除所述光刻胶以产生铜表面；
在所述铜表面上执行铜晶种层蚀刻以产生铜蚀刻表面；以及
在所述铜蚀刻表面上执行粘附层蚀刻。
2.如权利要求1所述的方法，其中所述铜蚀刻为湿法铜蚀刻。
3.如权利要求1所述的方法，其中所述移除所述光刻胶的所述涂层的所述部分通过光刻胶显影剂来执行。
4.如权利要求1所述的方法，其中所述聚酰亚胺基板为聚酰亚胺膜，或者其中所述钼为二硫化钼。
5.如权利要求1所述的方法，其中所述用包含钼的粘附层涂覆所述聚酰亚胺基板的所述至少一侧通过溅射工艺来执行，并且其中所述溅射工艺通过磁控管来产生。
6.一种用于制造电气部件的方法，包括：
提供具有含钼粘附层和铜晶种层的聚酰亚胺基板；
用光刻胶的涂层覆盖所述铜晶种层的至少一部分；
通过掩模将光刻胶的所述涂层暴露于辐射源；
移除所述光刻胶的所述涂层的一部分以产生从所述掩模转移的表面特征；
执行镀铜工艺，其中所述表面特征填充有铜；
移除所述光刻胶以产生铜表面；
在所述铜表面上执行铜晶种层蚀刻以产生铜蚀刻表面；以及
在所述铜蚀刻表面上执行粘附层蚀刻。
7.如权利要求6所述的方法，其中所述铜蚀刻为湿法铜蚀刻。
8.如权利要求6所述的方法，其中所述移除所述光刻胶的所述涂层的所述部分通过光刻胶显影剂来执行。
9.如权利要求6所述的方法，其中所述聚酰亚胺基板为聚酰亚胺膜，或者其中所述钼为二硫化钼。
10.如权利要求6所述的方法，其中所述用包含钼的粘附层涂覆所述聚酰亚胺基板的至少一侧通过溅射工艺来执行，并且其中所述溅射工艺通过磁控管来产生。
11.一种布置，包括：
聚酰亚胺基板，所述聚酰亚胺基板具有第一表面；
钼粘附层，所述钼粘附层连接至所述第一表面；
晶种层，所述晶种层连接至所述钼粘附层；以及
铜层，所述铜层连接至所述晶种层。
12.如权利要求11所述的布置，其中所述晶种层为铜晶种层。
13.如权利要求11所述的布置，其中所述铜层具有线空间封装比率小于10/10μm的特征。
14.如权利要求11所述的布置，其中所述铜层具有线空间封装比率小于5/5μm的特征。
15.如权利要求11所述的布置，其中所述铜层具有线空间封装比率小于2/2μm的特征。
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