TWI418272B - 處理核心基板之空腔的方法 - Google Patents

處理核心基板之空腔的方法 Download PDF

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TWI418272B
TWI418272B TW099124561A TW99124561A TWI418272B TW I418272 B TWI418272 B TW I418272B TW 099124561 A TW099124561 A TW 099124561A TW 99124561 A TW99124561 A TW 99124561A TW I418272 B TWI418272 B TW I418272B
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Taiwan
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electronic device
core substrate
cavity
embedded
circuit board
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TW099124561A
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TW201112897A (en
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Jin-Soo Jeong
Doo-Hwan Lee
Hwa-Sun Park
Jae-Kul Lee
Yul-Kyo Chung
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Samsung Electro Mech
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Priority claimed from KR1020090078738A external-priority patent/KR20110021123A/ko
Priority claimed from KR1020090102504A external-priority patent/KR101107067B1/ko
Application filed by Samsung Electro Mech filed Critical Samsung Electro Mech
Publication of TW201112897A publication Critical patent/TW201112897A/zh
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Publication of TWI418272B publication Critical patent/TWI418272B/zh

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Description

處理核心基板之空腔的方法
本發明是關於一種處理核心基板之空腔的方法。
為了製造一個嵌入式基板(電子裝置嵌入於基板中)，必須處理基板中的空腔(用於安裝電子裝置的空間)。空腔可於基板內以打孔方法來處理，其係使用CNC鑽孔或模具的機械過程，使用雷射(二氧化碳雷射或YAG雷射)等的鑽孔方法。
當以機械處理來處理空腔時，空腔的大小不準確，而且與基板的機械摩擦有可能導致損壞，如空腔內壁上的毛邊、裂紋和增白。基於這個原因，往往是用雷射鑽孔處理空腔。
在傳統的方法中，電路是形成於核心基板上，然後空腔是以直接雷射鑽孔於裸露絕緣體形成。在這種情況下，雷射光束移除部分的裸露絕緣體以形成空腔，但雷射光束也損壞(變形)了絕緣體的空腔本身以外的區域。此外，雷射鑽孔光束光罩的形狀會轉到絕緣體的表面，因此降低了空腔大小的精確度。
本發明提供一種處理核心基板之空腔的方法，其可實現精確的空腔形狀。
根據本發明之一態樣，提供一種處理核心基板之空腔的方法。根據本發明一實施例之處理核心基板之空腔的方法包括以下步驟：形成一第一處理區域於一核心基板之一表面上，該第一處理區域係以一電路圖型分界；形成一第二處理區域於該核心基板之另一表面上，該第二處理區域係以一電路圖型分界：及透過從該核心基板之該表面移除整個該第一處理區域，處理一空腔。
該第二處理區域可寬於該第一處理區域，且該第一處理區域之一中心與該第二處理區域之一中心可置於一相同垂直線上。該第一處理區域與該第二處理區域具有一相似形狀。
本發明的額外態樣及優點將以部分揭示於下面實施方式中，且部分將於實施方式中顯而易見，或可自本發明之實施習得。
既然本發明可以有各種不同的排列方式和實施例，將參照隨附圖式說明和描述某些實施例。然而，這絕不是要將本發明限制於某些實施例，並應解釋為包括所有本發明的思想和範圍所涵蓋的排列方式、均等物和替代物。在整個本發明的說明中，當描述某種技術是決定迴避本發明論點時，相關的詳細說明將被省略。
以下，將參照隨附圖式詳細地介紹一些處理核心基板之空腔的方法的實施例。在不同的圖式標號中，相同或者相應的元件將被給予相同的參考數標，任何相同或者相應的元件的多餘描述將不再重複。
圖1至圖3繪示根據本發明一實施例之處理核心基板之空腔的方法。圖1至圖3繪示了核心基板10、第一處理區域A1、第二處理區域A2、電路圖型12、介層14、絕緣體16、雷射光束L。
首先，正如圖1所示，以電路圖型12分界(demarcate)的第一處理區域A1是形成於核心基板10的一表面上，更具體來說是在絕緣體16的一表面上。在這裡，第一處理區域A1是指直接以雷射光束照射之絕緣體16的一邊上的表面。第一處理區域A1是以形成於絕緣體16的表面上的電路圖型12分界。換言之，沒有被電路圖型12覆蓋而暴露的區域成為第一處理區域A1。
可以減的程序、加的程序、噴墨程序、以及其他各種程序來將電路圖型12形成於絕緣體16的表面上。
以電路圖型12分界的第二處理區域A2是形成於絕緣體16的另一表面。如同第一處理區域A1，第二處理區域A2是以形成於絕緣體16的較低表面上的電路圖型12來分界，且第二處理區域A2是指暴露而沒有被形成於核心基板10的下表面上的電路圖型12所覆蓋的區域。在本實施例中，第二處理區域A2是形成以與第一處理區域A1對稱。亦即，第一處理區域A1和第二處理區域A2是就絕緣體16之相同大小及形狀形成於對稱的地點。
形成於絕緣體16的上下表面的電路圖型12可透過介層14(其穿透絕緣體16)彼此電性連接。
在第一處理區域A1和第二處理區域A2依上所述形成之後，如圖2所示，透過使用雷射光束L而自核心基板10的表面移除整個第一處理區域A1。藉由上述方法來處理空腔時，如圖3所示，原先設計的空腔形狀和尺寸W可以穩定牢固，這是因為形狀和空腔是以電路圖型12分界的。換言之，空腔大小是由電路圖型12決定的。因此，可以提高空腔大小的精確度，且可以提高空腔的內壁與表面的處理品質。圖3說明一個矩形的處理區域是以電路圖型12分界，並說明形狀為矩形柱體之空腔的形成。
圖4至圖5繪示根據本發明另一實施例之處理核心基板之空腔的方法。本實施例與先前描述的實施例的不同之處在於：第二處理區域A2比第一處理區域A1形成得更寬。以下主要描述本實施例與先前描述的實施例的不同之處。
根據本實施例，如圖4所示，第二處理區域A2比第一處理區域A1形成得更寬。圖4說明第一處理區域A1的大小是W1和第二處理區域A2的大小W2。
透過將第二處理區域A2設計並形成為比第一處理區域A1更寬，即使在電路圖型12a、12b形成於核心基板10的上下表面時有一些層間離心率，也可能阻止空腔的大小因離心率而被減小且精確地處理具有所欲大小的空腔。圖5說明如何用雷射光束L處理空腔。
圖6繪示由於層間離心率而尺寸縮小的空腔。正如圖6所示，當核心基板10的上部與下部電路圖型12之間有離心率時，由於空腔中形成的斜坡，必然會造成空腔的尺寸W3較原先設計的空腔尺寸W1為小。也就是說，用於嵌入電子裝置20的空間變小了。
如第7圖所示，將第二處理區域A2形成為大於第一處理區域A1，第一處理區域A1與第二處理區域A2之間的大小差異可以補足離心率，可達到原來設計的空腔尺寸。
由於電路圖型12a、12b的離心率可以出現在X軸方向和Y軸方向，第一處理區域A1的中心和第二處理區域A2的中心可置於同一垂直線，以補足電路圖型12a、12b的離心率。圖8A繪示第一處理區域A1的中心與第二處理區域A2的中心是重疊的。
此外，透過將第一處理區域A1和第二處理區域A2形成類似的形狀，電路圖型12a、12B的離心率在每個方向可以得到更充分的補足。圖8A及8B繪示第一處理區域A1與第二處理區域A2具有正方形的形狀。
以下，將加以說明根據本發明另一實施例的嵌入電子裝置之印刷電路板。
圖9繪示當電子裝置與絕緣體堆疊在一起時之壓力測試的模型示意圖。圖10繪示不同厚度絕緣體的壓力的圖表。圖11繪示不同厚度絕緣體的翹曲度的圖表。圖12繪示根據本發明一實施例之嵌入電子裝置之印刷電路板的示意圖。
本發明具有嵌入電子裝置之幾何對稱結構和此種結構之嵌入電子裝置的方法，以實現超薄、高度可靠的嵌入電子裝置中之印刷電路板，其可最小化在反覆熱應力環境下的翹曲度。基板在熱應力下的翹曲度是由物理性質數值所決定，如熱膨脹係數(CTE)、楊氏模量和柏松比(Poisson ratio)、和應用材料的幾何因素。對於繪示於圖9的印刷電路板，中線可以下列式子表示。
在這裡，EI 是電子裝置的楊氏模量，tI 是電子裝置的厚度(m)，Ed 是絕緣層的楊氏模量(Pa)，td 是絕緣層的厚度，t是基板的整體厚度(=td +tI )。
從上述式子計算所得之基板的彎矩M(以Nm表示)和正向力N(以N表示)可以下列式子表示。
在這裡，EI 是電子裝置的楊氏模量，tI 是電子裝置的厚度，αI 是電子裝置的熱膨脹係數，Ed 是絕緣層的楊氏模量(Pa)，td 是絕緣層的厚度，αd 是絕緣層的熱膨脹係數(m/K)，ΔT是溫度(K)的變化，w是基板的寬度。
從上述式子計算所得之柔度矩陣(compliance matrix)計算從上面的表達式可以下列式子表示。
從上述式子計算所得之剛度矩陣如下。
Q =S -1 　(4)
ABD矩陣可以下列式子表示。
基板的應變和曲率的可以下列式子得到。
從上述計算得出的應變值如下。
圖10繪示呈現於圖表的壓力值。也就是說，圖10顯示了在基板的頂部和底部上根據絕緣體厚度之壓力的變化，假設電子裝置有固定厚度100um。
圖11說明電子裝置的厚度與絕緣體的厚度的相依性，其係基於翹曲度而計算。換句話說，圖11顯示當電子裝置有固定的厚度50um和100um時，基於絕緣體厚度之基板翹曲度。
在圖11中，假設絕緣體厚度為50um，厚度50um的IC具有翹曲度0.26mm，當IC的厚度增加一倍至100um時，翹曲度減少1/3至0.09mm。由此可以推斷，基板的翹曲變形較絕緣體的厚度更取決於電子裝置的厚度。因此，可以預料的是，在幾何不對稱的印刷電路板中，電子裝置變得更薄時，減少基板的厚度將使翹曲變形增加到無法忍受的程度。
為了解決這個問題，必須最小化翹曲度，可透過調整電子裝置，將其置於基板絕緣層的中心，以使電子裝置幾何對稱。在本實施例中，可最小化反覆熱應力下之翹曲的超薄、高度可靠的嵌入電子裝置之印刷電路板是以幾何對稱性來實現。
圖12繪示根據本發明一實施例之嵌入電子裝置之印刷電路板100的剖面圖。如圖12所示，根據本發明之嵌入電子裝置之印刷電路板100包括核心基板110、電子裝置120、第一絕緣層130a、及第二絕緣層130b。核心基板110中有空腔116形成於其中，電子裝置120是以面朝上方法(face-up method)嵌入於空腔116中且具有電極122形成於其表面上，第一絕緣層130a是堆疊於核心基板110的上表面，第二絕緣層130b是堆疊於核心基板110的下表面並具有與第一絕緣層130a相同的厚度。在這裡，包括電極122之厚度的電子裝置之厚度(以b代表)與核心基板110的厚度相同。
在這裡，所謂「相同」並不一定指的是數學上精確相同數值的厚度，是指實質上相同的厚度，其中考慮了設計誤差、製造誤差和測量誤差。以下本發明說明使用之「相同」將意指上文所述的實質相同。
按照本實施例，嵌入電子裝置之印刷電路板100是透過以對稱結構來設計和製造嵌入式電子裝置120以最小化基板的翹曲。此外，透過將包括電極122之厚度的電子裝置之厚度(b)設計成與核心基板110的厚度相同，可提供核心基板110本身的對稱性，因此可最小化嵌入電子裝置120之核心基板110本身的翹曲。換言之，在實現核心基板110的垂直對稱時，也考慮到形成於電子裝置120之表面上的電極122之厚度，因此最大化核心基板110本身的對稱性。此對稱結構的功能是在印刷電路板和嵌入於印刷電路板中的電子裝置120變薄時，可降低增加翹曲度的風險。
此外，透過以面朝上方法來安裝嵌入在核心基板100中之電子裝置120，電路可有更好的匹配。在實際的印刷電路板中，上表面和下表面不匹配的程度約為20um至50um，但電子裝置的電極和電路板上的電路之間的匹配可透過以面朝上方法嵌入電子裝置120以及將電極122向上放置來提高，如本實施例如示。
如果內部電路114a、114b是形成於核心基板110的表面上，包括電極之厚度的電子裝置120之厚度(「b」)可設計成與包括內層114a、114b之厚度的核心基板110之厚度(「a」)相同。
較佳實施方式為電子裝置120之任一端垂直邊與空腔116之內壁之間的距離總和至少為60um。由於空腔116是使用鑽孔或雷射來處理，且電子裝置120可在切割過程中被切成晶片，距離是根據每一粗糙介面的最外層線。
雖然電子裝置120和內壁之間的距離是設計成最小值為30um，電子裝置120由於裝置容忍度而與一邊的內壁接觸是有可能的。因此，較佳情況是每個「C」和「D」的範圍是介於0和60um之間，且「C」和「D」的總和至少為60um。
當一邊是設計為小於50um，可觀察到電子裝置120並非適當地插入至空腔116中，而是放在空腔116的一邊上。此外，根據模擬和實際資料，隨著空腔116的變大，翹曲度會減小。但是，如果空腔116變得太薄，要保障電路的空間變得很難，因此較佳的情況是「C+D」的最大數值為160um或更小。
至此，已描述根據本發明一實施例之嵌入電子裝置之印刷電路板的結構。以下參照圖13至圖19描述製造嵌入電子裝置之印刷電路板的方法。由於根據本實施例之嵌入電子裝置之印刷電路板的結構與上述之結構完全相同，將不會描述結構特徵，主要是描述製造過程。
首先，準備核心基板110(見圖13)。內部電路114a、114b可形成於核心基板110的表面上，在這種情況下，核心基板110的上及下表面是透過介層112相互連接。
接下來，空腔116穿過核心基板110(見圖14)。空腔116是電子裝置120之後嵌入之處，且考慮了所嵌入之電子裝置的大小和形狀之後，可以合適的大小和形狀來處理。可使用機械鑽孔或雷射鑽孔來處理核心基板110中的空腔116。
然後，黏合層140是黏合至核心基板110的下表面(見圖15)。將黏合層140黏合至核心基板的下表面(空腔116穿過其中)，空腔的下邊會被黏合層140密封。
其次，電子裝置120是以面朝上方法黏合至透過空腔116暴露之黏合層140的表面(見圖16)，然後電子裝置120是透過將第一絕緣層130a堆疊在核心基板110的上表面上而覆蓋(見圖17)。空腔116的內部(其中嵌入電子裝置120)也是透過將第一絕緣層130a堆疊在核心基板110的上表面上而填補。
然後，移除黏合至核心基板110的下表面的黏合層140，而第二絕緣層130b是堆疊在核心基板110的下表面(見圖18)。
隨後，電路圖型132a、132b和介層134a、134b是形成於第一絕緣層130a和第二絕緣層130b上(見圖19)。
至此，本發明的一些實施例已被描述。但是，本發明所屬技術領域之通常知識者應當了解，在沒有偏離揭示於下附請求項之本發明技術思想和範圍的情況下，本發明可以有各種不同的排列方式和更動。
除上述實施例之外，有大量實施例是在本發明的請求項範圍內。
A1．．．第一處理區域
A2．．．第二處理區域
L．．．雷射光束
10．．．核心基板
12a．．．電路圖型
12b．．．電路圖型
14．．．介層
16．．．絕緣體
20．．．電子裝置
100．．．印刷電路板
110．．．核心基板
112．．．介層
114a．．．內部電路
114b．．．內部電路
116．．．空腔
120．．．電子裝置
122．．．電極
130a．．．第一絕緣層
130b．．．第二絕緣層
132a．．．電路圖型
132b．．．電路圖型
134a．．．介層
134b．．．介層
140．．．黏合層
圖1至圖3繪示根據本發明一實施例之處理核心基板之空腔的方法。
圖4至圖5繪示根據本發明另一實施例之處理核心基板之空腔的方法。
圖6繪示具有層間離心率的空腔。
圖7繪示根據本發明另一實施例之嵌入於核心基板的電子裝置，其中空腔係於核心基板中處理。
圖8A及8B繪示根據本發明另一實施例之第一處理區域及第二處理區域。
圖9繪示當電子裝置與絕緣體堆疊在一起時之壓力測試的模型示意圖。
圖10繪示不同厚度絕緣體的壓力的圖表。
圖11繪示不同厚度絕緣體的翹曲度的圖表。
圖12繪示根據本發明一實施例之嵌入電子裝置之印刷電路板的示意圖。
圖13至圖19繪示根據本發明一實施例之製造嵌入電子裝置之印刷電路板的過程示意圖。
10．．．核心基板
12a．．．電路圖型
12b．．．電路圖型
14．．．介層
16．．．絕緣體
A1．．．第一處理區域
A2．．．第二處理區域

Claims (16)

  1. 一種處理一核心基板之一空腔的方法，該方法包括以下步驟：形成一第一處理區域於一核心基板之一表面上，該第一處理區域係以一電路圖型分界；形成一第二處理區域於該核心基板之其他表面上，該第二處理區域係以一電路圖型分界：及透過使用雷射光束從該核心基板之該表面移除整個該第一處理區域來處理一空腔，該移除之區域不包括形成一電路圖型之一區域。
  2. 如請求項1之方法，其中該第二處理區域寬於該第一處理區域。
  3. 如請求項2之方法，其中該第一處理區域之一中心與該第二處理區域之一中心係置於一相同垂直線上。
  4. 如請求項3之方法，其中該第一處理區域與該第二處理區域具有一相似形狀。
  5. 一種嵌入電子裝置之印刷電路板，包括：一核心基板；一第一內部電路，該第一內部電路形成於該核心基板之 一表面上；一第二內部電路，該第二內部電路形成於該核心基板之其他表面上；一空腔，該空腔係基於該第一內部電路而穿透該核心基板：一電子裝置，該電子裝置嵌入於該空腔中，一電極，該電極形成於該電子裝置之一表面上；一第一絕緣層，該第一絕緣層堆疊於該核心基板之一表面上；及一第二絕緣層，該第二絕緣層堆疊於該核心基板之其他表面上，該第二絕緣層具有與該第一絕緣層相同之厚度，其中該第二內部電路自該空腔的一內壁向外方向分離。
  6. 如請求項5之嵌入電子裝置之印刷電路板，其中：一第一區域係藉由該第一內部電路在該核心基板之該一個表面上分界，一第二區域係藉由該第二內部電路在該核心基板之該其他表面上分界，該第二區域比該第一區域寬，該空腔之一橫向區塊的形狀與尺寸與該第一區域相同，以及該空腔之一較低部分定位在該第二區域之內。
  7. 如請求項5之嵌入電子裝置之印刷電路板，其中： 一內部電路係形成於該核心基板之一表面上；及包括該電極之一厚度的該電子裝置之一厚度係與包括該第一內部電路與該第二內部電路之一厚度的該核心基板之一厚度相同。
  8. 如請求項5之嵌入電子裝置之印刷電路板，其中自該電子裝置之任一垂直邊至該空腔之一內壁的距離之一總和係介於60um或更大與160um或更小之間。
  9. 如請求項5之嵌入電子裝置之印刷電路板，其中該第一內部電路的一側表面係與該空腔之內壁設置在一相同的表面。
  10. 如請求項5之嵌入電子裝置之印刷電路板，其中該空腔之一橫向區塊的形狀與尺寸與該核心基板之該一表面至該其他表面一致。
  11. 如請求項6之嵌入電子裝置之印刷電路板，其中該第一區域之一中心與該第二區域之一中心係置於一相同垂直線上。
  12. 如請求項5之嵌入電子裝置之印刷電路板，其中該空腔之一橫向區塊的尺寸自該核心基板之該一表面至該其他表面增大，因而該空腔之內壁具有一斜坡。
  13. 如請求項6之嵌入電子裝置之印刷電路板，其中分界該第一區域之該第一內部電路之一部分係與該第一內部電路之剩餘部分電性絕緣。
  14. 如請求項6之嵌入電子裝置之印刷電路板，其中分界該第二區域之該第二內部電路之一部分係與該第二內部電路之剩餘部分電性絕緣。
  15. 如請求項5之嵌入電子裝置之印刷電路板，進一步包括：一電路圖型，該電路圖型分別形成在該第一絕緣層與該第二絕緣層；以及一介層，該介層裝配以使該電路圖型與該電子裝置之該電極電性連接。
  16. 如請求項5之嵌入電子裝置之印刷電路板，其中該電子裝置以一面朝上之方法嵌入。
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