CN100524717C - 芯片内埋的模块化结构 - Google Patents

芯片内埋的模块化结构 Download PDF

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CN100524717C
CN100524717C CNB2005101233955A CN200510123395A CN100524717C CN 100524717 C CN100524717 C CN 100524717C CN B2005101233955 A CNB2005101233955 A CN B2005101233955A CN 200510123395 A CN200510123395 A CN 200510123395A CN 100524717 C CN100524717 C CN 100524717C
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dielectric layer
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modular construction
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CN1971894A (zh
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许诗滨
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Quanmao Precision Science & Technology Co Ltd
Phoenix Precision Technology Corp
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Abstract

本发明的芯片内埋的模块化结构包括介电层、至少一嵌埋在该介电层的半导体芯片以及至少一是形成于该介电层表面的线路结构，且该线路结构是借由多个形成于该介电层中的导电结构电性连接到该半导体芯片，后续可将该模块化结构嵌埋在电子装置中，并通过该介电层表面的线路结构与电子装置作电性连接；本发明的芯片内埋的模块化结构应用在各式电子装置的制程中，使形成在该模块化结构表面的线路结构能够通过各式导电结构与电子装置间作电性连接，借此提供多功能、高密度、缩短布线长度、提升电性功能的电子装置，同时由于本发明在电子装置制程中，通过整合该预先制作的内埋芯片的模块化结构，可节省制程时间，有利于大量生产制造。

Description

芯片内埋的模块化结构
技术领域
本发明是关于一种芯片内埋的模块化结构，特别是关于一种整合至少一半导体芯片的模块化结构。
背景技术
随着电子产业的蓬勃发展，电子产品也向轻、薄、短、小、高集成、多功能化方向发展。为满足半导体封装件高集成度(Integration)以及微型化(Miniaturization)的封装需求，半导体芯片的封装形逐渐由单一芯片的球栅阵列(BGA)封装或芯片倒装式(Flip Chip，FC)封装演变为3D封装和模块化封装形态，使得封装结构产生了不同的面貌，例如SiP(System in Package)，SIP(System Integrated Package)，SiB(System inBoard)等多种形式。
这些3D及模块化封装形态是以芯片倒装技术(flip chip)或引线技术(wire bonding)将单一的半导体芯片，一个接一个的连接以芯片承载板表面，也或以表面贴装技术(SMT)粘贴在芯片承载板表面。这些封装形态虽然可以将多个不同的元件进行模块化设计及封装，但这种封装是一种高难度及高成本的组合，虽然可实现多功能及模块化的目的，但是其缺点是诸多元件的电性互连及其性能会由于噪声的干扰受到限制，且由于元件的面积及体积限制使得承载板表面布线难度增加，以及由于这些元件是全部分布在基板表面，因而不利于模块化结构尺寸的缩小及性能的提高。
为此，有业界人士提出将半导体元件埋入基板的作法。如图1所示，它是现有半导体元件埋入基板的封装件的剖面示意图。如图所示，该封装件包括承载板10，且该承载板10的一表面100形成有至少一开口100a；至少一半导体芯片11，且该半导体芯片11上形成有多个电性连接垫110，接置在该承载板10上且收纳在该开口100a中；线路增层结构12形成于该承载板10上，且该线路增层结构12是借由多个导电盲孔120电性连接到该半导体芯片11上的电性连接垫110。
该半导体芯片11具有一主动面11a及与该主动面相对的非主动面11b，且该主动面11a上形成有多个电性连接垫110，该非主动面11b是通过胶粘剂13接置在该承载板开口100a中。
该线路增层结构12包括至少一绝缘层121，与该绝缘层121交错叠置的线路层122，以及贯穿该绝缘层121电性连接该线路层122的导电盲孔120，且该多个导电盲孔120能够电性连接到收纳于该承载板开口100a的该半导体芯片11的电性连接垫110。在该线路增层结构12最外表面的线路层上则形成有多个电性连接端123，且该最外层线路层上被覆有一防焊层124，该防焊层124具有多个开口外露出该电性连接端123，用以提供植置有导电元件，例如焊球(Solder ball)125，供收纳于该承载板10中的该半导体芯片11，能够通过其表面的电性连接垫110、该线路增层结构12以及该焊球125电性导接到外部组件。
上述封装结构虽然提高了芯片的封装密度及电性功能，但是埋入的半导体芯片大多数是单一形式的元件，尚未形成多功能的模块架构，况且，若应用在多芯片时，其制作过程中仍需要分别人各该多个芯片提供电性连接，耗费了制作时间及成本，不利大量生产。
因此，如何提供一种多功能、高密度的芯片内埋的模块化结构，能够缩短布线长度、简化制程、提升电性能以及使封装结构达到量产目的，避免现有技术的缺失，实已成为目前业界亟待攻克的难题。
发明内容
为克服上述现有技术的缺点，本发明的主要目的在于提供一种多功能、高密度的芯片内埋的模块化结构。
本发明的另一目的在于提供一种可缩短布线长度、提升电性功能的芯片内埋的模块化结构。
本发明的又一目的在于将芯片内埋的模块化结构埋入电子装置，如主板(Mother board)，模块卡等电路板或IC基板与半导体装置中，提供一种能够应用在电子装置制程中，且有利于电子装置大量制造生产的芯片内埋的模块化结构。
为达上述及其它目的，本发明一种芯片内埋的模块化结构包括：该芯片内埋的模块化结构包括：介电层；至少一嵌埋在该介电层的半导体芯片；以及至少一形成于该介电层表面的线路结构，且该线路结构借由多条形成于该介电层中的导电结构电性连接到该半导体芯片，可将该模块化结构嵌埋在一电子装置中，并通过形成于该介电层表面的线路结构与电子装置进行电性连接。
本发明还涉及的另一个芯片内埋的模块化结构包括：第一介电层；至少一半导体芯片，具有一主动面及一相对的非主动面，借由其非主动面接置于该第一介电层上，且在该主动面上形成有多个电性连接垫；第二介电层，形成于该第一介电层上，将该半导体芯片埋设在该第一及第二介电层之间；以及线路结构，形成于该第二介电层上，且该线路结构是借由多条导电结构电性连接到该半导体芯片主动面上的电性连接垫，可将该模块化结构嵌埋在一电子装置中，并通过该其表面线路结构与电子装置进行电性连接。其中，该芯片内埋的模块化结构还可包括另一形成于该第一介电层表面的线路结构，以及贯穿该第一及第二介电层以电性连接其表面线路结构的层间导电结构，为电子装置提供更佳的电性功能。
本发明还涉及的又一个芯片内埋的模块化结构包括：第一介电层；芯层，接置在该第一介电层上，且该芯层中具有至少一贯穿开孔；至少一半导体芯片，接置在该第一介电层上并收纳于芯层的开孔中，且该半导体芯片的主动面形成有多个电性连接垫；第二介电层，间隔该芯层形成于该第一介电层上，使该第一及第二介电层填充在该芯层的开孔，将该半导体芯片固定在该芯层开孔中；以及线路结构，形成于该第二介电层上，且该线路结构是借由多条导电结构电性连接到该半导体芯片主动面上的电性连接垫，可将该模块化结构嵌埋在一电子装置中，并通过线路结构与电子装置进行电性连接。
本发明的芯片内埋的模块化结构应用在各式电子装置的制程中，将该模块化结构嵌埋在电子装置中，并使形成在该模块化结构表面的线路结构能够通过各式导电结构(例如导电盲孔、导电凸块、电镀导通孔)等，与电子装置间作电性连接，借此提供多功能、高密度、缩短布线长度、提升电性功能的电子装置，同时由于本发明在电子装置制程中，通过整合该预先制作的内埋芯片的模块化结构，可节省制程时间，有利于大量生产制造。
附图说明
图1是现有半导体封装件的剖面示意图；
图2是本发明的芯片内埋的模块化结构实施例1的剖面示意图；
图3是本发明的芯片内埋的模块化结构实施例2的剖面示意图；
图4是本发明的芯片内埋的模块化结构实施例3的剖面示意图；
图5是本发明的芯片内埋的模块化结构实施例4的剖面示意图；以及
图6至图8是整合本发明的芯片内埋的模块化结构的电子装置剖面示意图。
具体实施方式
在此需说明的是本发明的芯片内埋的模块化结构中可埋设至少一半导体芯片，为简化说明本发明的优点及功效，以下实施例中仅例示出两个半导体芯片埋设在模块化结构中，但并非以此限制本发明的范围。
实施例1
请参阅图2，它是本发明的芯片内埋的模块化结构实施例1的剖面示意图。如图所示，该芯片内埋的模块化结构包括：第一介电层20；半导体芯片21a、21b，接置在该第一介电层20上，且该半导体芯片21a、21b上形成有多个电性连接垫210a、210b；第二介电层23，压合或涂布在该第一介电层20上，使得该半导体芯片21a、21b埋设在该第一介电层20及该第二介电层23之间；以及线路结构24，形成于该第二介电层23上，且该线路结构24是通过多条形成于该第二介电层23中的导电结构241(可例如是导电盲孔或凸块等)，电性连接到该半导体芯片21a、21b上的电性连接垫210a、210b。供后续可将该模块化结构嵌埋在电子装置如主板(Mother board)、子卡(Daughter Card)等电路板或IC基板与半导体装置中，并通过形成在该第二介电层23表面的线路结构24与电子装置作电性连接。
该第一介电层20是由薄膜型(Film type)或液态树脂的FR-4树脂、FR-5树脂、环氧树脂(Epoxy)、聚酯树脂(Polyesters)、氰酸脂(Cyanateester)、聚酰亚胺(Polyimide)、双马来酰亚胺三嗪(BT，Bismaleimidetriazine)、ABF(Ajinomoto build-up film)、Aramide树脂或混合环氧树脂玻、璃纤维(Glass fiber)等绝缘性材料制成。
该半导体芯片21a具有主动面211及与该主动面相对的非主动面212，且该半导体芯片21a的主动面211上形成有电性连接垫210a，该半导体芯片21a的非主动面212接置在该第一介电层20上。其中，该半导体芯片21a可选择为主动芯片或被动芯片，例如电容芯片、电阻芯片、存储器芯片(memory chip)、ASIC(Application Specific IntegratedCircuit)芯片、光电元件及微处理器(microprocessor)芯片中的一个。
该半导体芯片21b是具有主动面213及与该主动面213相对的非主动面214，且该半导体芯片21b的主动面213上形成有电性连接垫210b，该半导体芯片21b的非主动面214接置在该第一介电层20上。其中，该半导体芯片21b是可选择为主动或被动芯片，且它可以是与该半导体芯片21a相同或不同的芯片。
该第二介电层23，压合或涂布在该第一介电层20上，并可借由该第一及第二介电层20、23压合或涂布后，将该半导体芯片21a、21b埋设在该第一及第二介电层20、23形成的绝缘体中。该第二介电层23可视实际需要，选择与该第一介电层20相同或不同的材质。
该线路结构24，是形成在该第二介电层23上，且该线路结构24可借由形成在该第二介电层23中的多个例如导电盲孔或导电凸块等导电结构241，电性连接到该半导体芯片21a、21b主动面上的电性连接垫210a、210b。该线路结构24的形成方式是业界现有的技术，故在此不再为文赘述。
实施例2
请参阅图3，它是本发明的芯片内埋的模块化结构实施例2的剖面示意图。与本发明实施例1的结构大致相同，以下仅对其不同之处进行说明。如图所示，实施例2与实施例1的主要差异在于第一介电层30与第二介电层33之间还具有一芯层32，且该芯层32中形成有贯穿开孔320、322，供半导体芯片31a、31b收纳于该开孔320、322中，当该第二介电层33间隔该芯层32压合或涂布在该第一介电层30后，该第一及第二介电层30、33能够填充在这些开孔320、322中，将这些半导体芯片31a、31b埋设在其对应的开孔中，并可借由形成在该第二介电层33上的线路结构34以及导电结构341，提供芯片31a、31b向外的电性延伸。其中，该芯层32的材质可以是有机材料，金属或陶瓷等材料。
实施例3
请参阅图4，它是本发明实施例3的剖面示意图，如图所示，该芯片内埋的模块化结构包括：第一介电层40；半导体芯片41a、41b，接置在该第一介电层40上，且该半导体芯片41a、41b上形成有多个电性连接垫410a、410b；第二介电层43压合或涂布在该第一介电层40上，使得该半导体芯片41a、41b埋设在该第一及第二介电层40、43之间；线路结构44，形成在该第二介电层43上，且该线路结构44是借由多个导电结构441电性连接到该半导体芯片41a、41b的电性连接垫410a、410b；线路结构45，形成于该第一介电层40外表面；以及导电通孔46，贯穿该第一及第二介电层40、43，电性连接形成于该第一及第二介电层外表面的线路结构44、45。
该线路结构44，形成于该第二介电层43上，且该线路结构44是借由形成于该第二介电层43中的多个导电结构441(如导电盲孔或凸块)，电性连接到该半导体芯片44a、44b主动面上的电性连接垫410a、410b。该线路结构45，形成于该第一介电层40上，且该线路结构45也可借通过多个导电结构451(如导电盲孔或凸块)连接到该芯片41a、41b的非主动面，并借由该导电结构451及部分线路结构45提供半导体芯片41a、41b良好的散热途径。同时，形成于该第一及第二介电层40、43上的线路结构45、44，可借由该导电通孔46相互电性导接，进一步电性整合以提升其电性功能。
实施例4
请参阅图5，它是本发明实施例4的剖面示意图，其结构与本发明实施例3的模块化结构大致相同，以下仅对其不同之处进行说明。如图所示，实施例4与实施例3的主要差异是在第一介电层50与第二介电层53之间还具有芯层52，且该芯层52中形成有贯穿开孔520、522，供半导体芯片51a、51b分别收纳于该开孔520、522中，该第二介电层53间隔该芯层52压合或涂布于该第一介电层50，且该第一及第二介电层50、53能够填充在这些开孔520、522中，将这些半导体芯片51a、51b埋设在其对应的开孔中。其中，该芯层52可以是有机材料，金属或陶瓷等材料。
另在该第一及第二介电层50、53上形成有线路结构54、55，且该线路结构54、55能够借由多条导电结构541、551分别导接到半导体芯片51a、51b的主动面及非主动面，提供半导体芯片51a、51b能够借由该导电结构541及线路结构54进行电性延伸，以及通过该导电结构551及线路结构55进行导热。同时，形成于该第一及第二介电层50、53上的线路结构55、54可借由导电通孔56相互电性导接，进一步作电性整合以提升电性功能。
因此，本发明的芯片内埋的模块化结构是将半导体芯片埋设在介电层中，在后续进一步进行半导体构装时，通过与其电性连接的线路结构能够电性导接到外部电子装置，提供后续制程较大的构装弹性。
与现有技术相比，本发明的芯片内埋的模块化结构是将至少一半导体芯片埋设在介电材料中，并直接从该半导体芯片的电性连接垫上进行电性延伸，可缩短布线路径、提升电性功能，同时可提升封装密度，提供具有多功能的模块化结构。
在本发明中半导体芯片产生的热量可通过导电结构传递到线路结构所形成的散热路径中进行散热，有效逸散半导体芯片的热量，提升模块化结构的操作性能。此外本发明的芯片内埋的模块化结构还可进行进一步构装形成多功能、高集成度、高性能的电子装置。
图6至图8是将上述芯片内埋的模块化结构进一步封装后形成的封装件的剖面示意图。
请参阅图6，它是将上述芯片内埋的模块化结构埋入IC基板后形成的半导体封装件的剖面示意图。为简化说明，仅以本发明实施例3的芯片内埋的模块化结构为例进行说明，但并非用以限制本发明。
如图所示，该芯片内埋的模块化结构6a是作为IC基板的核心层，并在该芯片内埋的模块化结构6a上进行线路增层制程以形成线路增层结构61，且该线路增层结构61是可电性连接到该模块化结构6a表面的线路结构64，并使线路增层结构61的表面线路能够电性连接到外部电子元件，例如，该基板上表面的至少一半导体芯片68，该基板下表面植设多个锡球69。当然，在制程应用时，也可将该芯片模块化结构直接嵌埋在核心层中，并利用增层作业将嵌埋在核心层中的模块化结构表面线路向外进行电性延伸，通过整合该模块化结构提升电子装置的电性功能。
图7是将本发明上述芯片内埋的模块化结构整合在半导体装置的剖面示意图。如图所示，该芯片内埋的模块化结构7a是可置于该电路板的任一绝缘层70中，并在该绝缘层70上进行电路增层制程形成线路增层结构71，同时使该线路增层结构71能够电性导接到该芯片内埋的模块化结构7a表面线路结构74，再借由该线路增层结构71与外部电子元件，例如在上表面设置并电性连接半导体芯片78及被动元件77，在下表面植设多个锡球79，如此即可通过整合该模块化结构提升半导体装置的电性功能。
图8是将本发明上述芯片内埋的模块化结构埋入电路板的剖面示意图。如图所示，该芯片内埋的模块化结构8a是可埋入该电路板8中的任一层，并与该电路板8的线路层80进行电性连接，形成一模块化电子构装或组装结构。
此处须应特别注意的是，该图6至图8中所应用的芯片内埋的模块化结构是可选择性替换为本发明实施例1实施例4(如图2至图5所示)的芯片内埋的模块化结构所组群组中的一个。
因此，本发明的芯片内埋的模块化结构可应用在各式电子装置的制程中，将该模块化结构嵌埋于电子装置中，并使形成于该模块化结构表面的线路结构能够通过各式导电结构(例如导电盲孔、导电凸块或电镀导通孔等)，与电子装置间作电性连接，借此提供多功能、高密度、缩短布线长度、提升电性功能的电子装置，同时由于在电子装置制程中，通过整合该预先制作的内埋芯片的模块化结构，可节省制程时间利于大量生产制造。

Claims (10)

1.一种芯片内埋的模块化结构，其特征在于，该芯片内埋的模块化结构包括：
第一介电层；
至少一半导体芯片，具有一主动面及一相对的非主动面，借由其非主动面接置于该第一介电层上，且在该主动面上形成有多个电性连接垫；
第二介电层，形成于该第一介电层上，将该半导体芯片埋设在该第一及第二介电层之间；
线路结构，形成于该第二介电层上，且该线路结构是借由多条导电结构电性连接到该半导体芯片主动面上的电性连接垫；
另一线路结构，形成于该第一介电层外露表面，且该线路结构借由形成于该第一介电层中的导电结构导接到该半导体芯片，该第一介电层表面的线路结构作为导热层，为半导体芯片提供散热作用；以及
导电通孔，贯穿该第一及第二介电层，用以电性连接该第一及第二介电层之表面上的线路结构，以将该模块化结构嵌埋于一电子装置中，并透过该第一及第二介电层之表面上的线路结构而与该电子装置作电性连接。
2.如权利要求1所述的芯片内埋的模块化结构，其特征在于，该第一介电层及第二介电层是由不同材料构成。
3.如权利要求1所述的芯片内埋的模块化结构，其特征在于，该第一介电层及第二介电层是由相同的材料构成。
4.如权利要求1所述的芯片内埋的模块化结构，其特征在于，该芯片内埋的模块化结构是嵌埋在电子装置中，并借由线路增层制程以自该模块化结构的表面线路结构上电性延伸形成线路增层结构。
5.一种芯片内埋的模块化结构，其特征在于，该芯片内埋的模块化结构包括：
第一介电层；
芯层，接置在该第一介电层上，且该芯层中具有至少一贯穿开孔；
至少一半导体芯片，接置在该第一介电层上并收纳于芯层的开孔中，且该半导体芯片的主动面形成有多个电性连接垫；
第二介电层，间隔该芯层形成于该第一介电层上，使该第一及第二介电层填充在该芯层的开孔，将该半导体芯片固定在该芯层开孔中；
线路结构，形成于该第二介电层上，且该线路结构是借由多条导电结构电性连接到该半导体芯片主动面上的电性连接垫；
另一线路结构，形成于该第一介电层外露表面，且该线路结构借由形成于该第一介电层中的导电结构导接到该半导体芯片，该第一介电层表面的线路结构作为导热层，为半导体芯片提供散热作用；以及
导电通孔，贯穿该芯层、第一及第二介电层，用以电性连接该第一及第二介电层之表面上的线路结构，以将该模块化结构嵌埋于一电子装置中，并透过该第一及第二介电层之表面上的线路结构而与该电子装置作电性连接。
6.如权利要求5所述的芯片内埋的模块化结构，其特征在于，该芯层是绝缘板或金属板。
7.如权利要求6所述的芯片内埋的模块化结构，其特征在于，该芯层是陶瓷板。
8.如权利要求5所述的芯片内埋的模块化结构，其特征在于，该第一及第二介电层是由不同材料构成。
9.如权利要求5所述的芯片内埋的模块化结构，其特征在于，该第一及第二介电层是由相同材料构成。
10.如权利要求5所述的芯片内埋的模块化结构，其特征在于，该芯片内埋的模块化结构是嵌埋在电子装置中，并借由线路增层制程以自该模块化结构的表面线路结构上电性延伸形成线路增层结构。
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