CN102696105B - 具有嵌入在接线体中的芯片的芯片封装件 - Google Patents
具有嵌入在接线体中的芯片的芯片封装件 Download PDFInfo
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- CN102696105B CN102696105B CN201080045635.3A CN201080045635A CN102696105B CN 102696105 B CN102696105 B CN 102696105B CN 201080045635 A CN201080045635 A CN 201080045635A CN 102696105 B CN102696105 B CN 102696105B
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Abstract
公开了一种电子装置(80)。该电子装置包括至少一个电子芯片(30)和电子芯片(30)的封装件。封装件包括层压基板(10),其中,电子芯片(30)附接在层压基板(10)上。层压基板(10)包括一个或多个导电层(12a-d)、一个或多个绝缘层(16a-c)以及形成在层压基板(10)的与连接到电子芯片(30)的面相反的面上的导电层(12d)中的多个焊盘(20)。此外,封装件包括围绕电子芯片(30)形成的绝缘体(60)。而且,封装件包括延伸穿过绝缘体(60)的多个电极(64)。对于层压基板(10)的每个焊盘(20),在一个或多个导电层(12a-d)和穿过一个或多个绝缘层(16a-c)的一个或多个通道(18)中形成接线,以电连接焊盘(20)和至少一个电极(64)。封装还包括形成在绝缘体(60)和电子芯片(30)上的互连体(70)。互连体(70)包括在互连体(70)的与连接到绝缘体(60)和电子芯片(30)的面相反的面上的多个焊盘(72),且互连体还包括在互连体(70)内部的接线(74),用于电子芯片(30)的焊盘(32)、电极(64)和互连体(70)的焊盘(72)之间的电连接。还公开了一种制造电子装置(80)的方法。
Description
技术领域
本发明涉及一种包括电子芯片和电子芯片封装件的电子装置。此外,本发明涉及一种制造该电子装置的方法。
背景技术
电子芯片,例如半导体芯片,不断向着更高功能和更高集成度发展。因此,用于这些芯片的封装的输入/输出(I/O)互连线的数量不断增加。为了以可接受的间距(或相邻I/O之间的距离)排列更多的I/O,电子封装已经从I/O沿封装件的两边的双列直插式封装(DIP)和I/O沿封装件的所有四个边的四列扁平封装(QFP)发展为I/O在整个底部表面的球栅阵列(BGA)。
封装技术的下一阶段是所谓的3D(三维)封装技术,在该技术中,I/O位于封装的顶面和底面,使得在印刷电路板(PCB)上,组件可以相互堆叠,由此比例如元件并排安装在PCB上节省空间。例如,美国专利2007/0296065 A1公开了一种具有导电支撑基板的三维电子封装装置,所述三维电子封装装置可通过该装置两面上的信号接点实现多芯片堆叠。
尽管上面所描述的3D封装技术提高了空间利用率,例如,与在PCB上并排安装电子装置相比,但希望提供更进一步提高空间利用率的电子封装技术。
发明内容
本发明的目的是提供以相对高效的空间利用率对电子芯片进行封装。
根据第一方面,提供一种电子装置。所述电子装置包括至少一个电子芯片,所述电子芯片在其第一面上具有互连焊盘。所述电子装置还包括用于所述电子芯片的封装件。所述封装件包括层压基板,所述层压基板由一个或多个包含导电材料的导电层和由介电材料形成的一个或多个绝缘层的层压件制成。所述电子芯片以其第二面附接在所述层压基板的第一面上且附接在第一区域中,所述电子芯片的第二面与所述电子芯片的第一面相反并面向所述层压基板的第一面。所述层压基板包括形成在所述层压基板的第二面上的所述层压基板的导电层中的多个焊盘,所述层压基板的第二面与所述层压基板的第一面相反。所述封装件还包括电绝缘材料的绝缘体,所述绝缘体围绕所述电子芯片形成在所述层压基板的第一面上。所述绝缘体的第一表面基本上与所述电子芯片的第一面共面。此外,所述封装件包括导电材料的多个电极,所述电极形成在所述层压基板的第一面上且形成在第二区域中。所述第二区域在所述第一区域外。所述电极延伸穿过所述绝缘体。此外,对于所述层压基板的所述多个焊盘中的每个焊盘,所述封装件包括接线,所述接线形成在所述层压基板的一个或多个导电层和穿过所述层压基板的一个或多个绝缘层的一个或多个导电通道中,以电连接所述焊盘和至少一个电极。此外,所述封装件包括互连体,所述互连体形成在所述绝缘体的第一表面和所述电子芯片的第一面上。所述互连体包括:多个焊盘,所述多个焊盘在所述互连体的与所述互连体面向所述电子芯片和所述绝缘体的面相反的一面上;以及接线,所述接线用于所述电子芯片的焊盘、所述电极和所述互连体的焊盘之间的电连接。
可以利用薄膜工艺形成所述互连体,以产生所述互连体的焊盘、所述互连体的所述接线以及所述互连体的电绝缘材料。
所述层压基板的至少一个绝缘层可以包括聚合树脂材料。所述聚合树脂材料可以被加固。
例如,所述聚合树脂材料可包括味之素内置膜(ABF)、苯并环丁烯(BCB),双马来酰亚胺三嗪(BT)、环氧树脂、聚酯、聚酰亚胺和/或聚四氟乙烯。
可以利用有机球栅阵列(BGA)基板制造方法形成所述层压基板。
所述绝缘体可以被传递模塑。
所述电子装置还可包括焊球,所述焊球附接在所述互连体的一个或多个焊盘上和/或所述层压基板的一个或多个焊盘上。
根据第二方面,一种电子设备包括如第一方面所述的第一电子装置。所述电子设备还可包括印刷电路板(PCB)和如第一方面所述的第二电子装置。所述第一电子装置可以安装在所述PCB上,所述第二电子装置可以以3D封装形式安装在所述第一电子装置上。例如,所述电子设备可以是但不局限于:便携式电子设备、手机、电脑、便携式媒体播放器、卫星导航设备、传呼机、通信器、电子记事本、智能电话或个人数字助理(PDA)。
根据第三方面,提供一种制造如第一方面所述的电子装置的方法。该方法包括将所述电子芯片附接到所述层压基板上。该方法还包括利用模塑法形成所述绝缘体。此外,该方法包括在待形成电极的位置提供贯穿所述绝缘体的孔。此外,该方法包括通过向所述绝缘体中设置的所述孔供应导电材料形成所述电极。此外,该方法包括通过重复地执行薄膜沉积或电镀,以及选择性去除交替的介电材料和导电材料,来形成所述互连体。
供应所述电极的导电材料可以包括利用电镀法或溅射法供应导电材料。
该方法还可以包括将焊球附接到所述互连体的一个或多个焊盘上和/或所述层压基板的一个或多个焊盘上。
该方法可以包括利用有机BGA基板制造方法形成所述层压基板。
利用模塑法形成所述绝缘体可以包括将附接有所述电子芯片的层压基板放置在传递模具中以及将模塑料注入到所述传递模具中以形成所述绝缘体。
在从属权利要求中限定本发明的其他实施方式。
应当强调的是,本说明书中所使用的术语“包括”用于列举陈述的特征、整体、步骤或元件的存在,但并不排除一个或多个其它特征、整体、步骤、元件或其组合的存在或增加。
附图说明
在参照附图的以下具体描述中,将呈现本发明的实施方式的其他目的、特征及优势,附图中:
图1-9示出根据本发明的实施方式的电子装置或其部分的多个示图;和
图10示意性地示出包括根据本发明的实施方式的电子装置的电子设备。
图11示出根据本发明的实施方式的电子设备的部分示图。
具体实施方式
在下文中,参照附图描述本发明的实施方式。应当强调的是,为了便于在同一幅图中示出尺寸大为不同的对象,附图中所示的特征未按比例绘制。
根据本发明的实施方式,按照下文参照图1-7所描述的,进行电子装置80(图6-7)的制造。所述电子装置80以电子芯片30(例如半导体芯片)和所述电子芯片的封装件的形式。例如,这样的电子装置可以安装在印刷电路板(PCB)上或者以3D(三维)封装形式与另一这样的电子装置80层叠。根据所述实施方式,该制造过程从层压基板10(其是封装件的一部分)开始,在图1中以截面图示出该层压基板10。所述层压基板10由包括一个或多于一个的导电层12a-d的层压件制成。每个导电层12a-d包括导电材料14。例如,所述导电材料可以是金属(例如铜)或金属合金。如图1所示,所述导电层12a-d没有完全被所述导电材料14填充。而是,所述导电材料14用于形成所述导电层12a-d中的导线,其中,所述导线被所述导电层中无导电材料的区域隔开。在图1中用白色空间15示出所述导电层12a-d中的导电材料的不存在。
所述层压基板10还包括介电材料的一个或多于一个的绝缘层16a-c。在多个导电层12a-d的情况中,所述导电层12a-d由介电材料17的绝缘层16a-c分隔。所述绝缘层16a-c中的一个或多个绝缘层可以包括聚合树脂材料。例如,所述聚合树脂材料可以是或者包括味之素内置膜(Ajinomoto Build-up Film-ABF)、苯并环丁烯(BCB)、双马来酰亚胺三嗪(BT)、环氧树脂、聚酯、聚酰亚胺和/或聚四氟乙烯。此外,绝缘层16a-c中的一个或多个绝缘层可以包括用于聚合树脂材料的加固材料,例如玻璃纤维加固材料。
所述层压基板10还包括穿过所述层压基板10的绝缘层16a-c的导电通道18。所述通道由导电材料制成,例如金属或金属合金。所述通道提供不同导电层之间的电连接。
用于提供所述电子装置和其它元件之间的电连接的焊盘20形成在位于所述层压基板10的一面上的导电层12d上。
所述层压基板10可以与球栅阵列(BGA)封装中所用的有机基板类型相同。因此,可以利用与制造BGA基板所用的制造方法类似的制造方法形成所述层压基板10。例如,该制造方法可以以这样的层压件开始:该层压件包括一面或两面上有金属层的单一介电基板。通过借助蚀刻法选择性地去除金属形成布线。通过穿过所述层压件钻孔并使每个孔的至少部分填充导电材料来形成通道。可以将更多这样的介电层和金属层层压在一起(例如利用热压法),以形成具有多于两个导电层12a-d的层压基板10。BGA基板的制造方法是本领域所已知的,因此本文不作进一步描述。
如图2所示,接着将电子芯片30(例如半导体芯片)附接在所述层压基板10上,该电子芯片30位于与所述层压基板的焊盘20相反的那一面上。下文中将电子芯片30简称为芯片30。所述芯片30可以具有任何类型的电子功能,例如模拟和/或数字,本发明不局限于任一特定的这样的功能。下文中将所述层压基板10上附接有所述芯片30的区域称为芯片区域。下面所描述的实施方式中,将单个芯片30附接在所述层压基板10的芯片区域内。然而,在其他实施方式中,可以将多于一个的芯片30附接在所述层压基板10的芯片区域内。所述芯片30在其一面上具有互连焊盘32。所述芯片30附接在所述层压基板10上,使得所述芯片30的包括焊盘32的面远离所述层压基板10。例如,可利用任一合适的粘合剂34将所述芯片30附接在所述层压基板上。
在下一步骤中,如图3所示,将附接有所述芯片30的层压基板10放置在传递模具50中。所述传递模具50的表面覆盖有密封薄膜52a-b。接着,将电绝缘材料的模塑料(例如氧化硅填充的环氧树脂)注入所述传递模具50的开口54以形成绝缘体60,进一步在图4中示出。电绝缘材料的绝缘体60形成在所述层压基板10的与附接有所述芯片30的面相同的面上且在所述芯片30周围。所述绝缘体60的远离所述层压基板10的表面基本上与所述电子芯片30的远离所述层压基板10的面共面。由于密封薄膜52a-b,在传递模塑期间,所述层压基板的焊盘20和所述芯片30的焊盘32未被所述模塑料覆盖。因此,所述层压基板的焊盘20和所述芯片30的焊盘32是自由裸露的。
随后,如图5所示,形成贯穿所述绝缘体60的孔62。例如可通过机械钻孔或激光钻孔形成所述孔62。
在下一步骤中,如图6所示,通过向所述绝缘体60中形成的孔62中供应导电材料,形成多个电极64。所述电极64的导电材料可以是金属(例如铜)或金属合金。例如,可以利用电镀法或溅射法向所述孔62提供所述电极64的导电材料。因此,所述电极64形成在所述层压基板10的与附接有芯片30的这一面相同的面上,并且在所述芯片区域外的区域中。而且,所述电极64穿过所述绝缘体60延伸至所述绝缘体60的远离所述层压基板10的表面。在所述层压基板10的导电层12a-b中且经由通道18形成接线,使得对于所述层压基板10的多个焊盘20中的每一个焊盘而言,所述焊盘20与至少一个电极64电连接。
在随后的步骤中,如图7所示,在所述绝缘体60的表面上和所述芯片30的远离所述层压基板10的面上形成互连体70。所述互连体70在其远离所述电子芯片30和所述绝缘体60的面上包括多个焊盘72。而且,所述互连体包括用于所述芯片30的焊盘32、所述电极64和所述互连体70的焊盘72之间的电连接的接线74。因此,所述芯片30的焊盘32可以通过接线74、电极64以及形成在所述层压基板10的导电层12a-d和通道18中的接线电连接到所述层压基板10的焊盘20,或者通过接线74电连接到所述互连体70的焊盘72。此外,尽管未在图中明确示出,但所述层压基板10的焊盘20可以通过所述层压基板10的导电层12a-d和通道18中的接线、电极64以及所述互连体70的接线74电连接到所述互连体的焊盘72。
图7所示的截面图是根据一实施方式的电子装置80的截面图。所述电子装置80包括所述芯片30和所述芯片30的封装件。所述封装件包括所述层压基板10、所述绝缘体60、所述电极64以及所述互连体70。
可以利用薄膜工艺形成所述互连体70,以产生所述互连体70的焊盘72、所述互连体70的接线74以及所述互连体70的电绝缘材料76。例如,可以通过重复地执行薄膜沉积或电镀,以及选择性去除交替的介电材料和导电材料,形成所述互连体70。例如,所述导电材料可以是金属和金属合金。这种薄膜工艺是本领域所知的,因此这里不作进一步描述。
图1-7示出所述电子装置80或其部分的截面图。为了进一步说明本发明的实施方式,图8a-c中提供“俯视”图和“仰视”图。图8a示出了从所述焊盘20所在的这一面看的所述层压基板10的示图。在图8a中,所述焊盘20均匀分布在所述层压基板10的表面上。然而,在其它实施方式中,所述焊盘20可以以图8a所示方式以外的其它方式分布,且不一定均匀分布在所述层压基板10的表面上。
图8b示出了从所述层压基板10的布置有所述绝缘体60、所述芯片30和所述电极64的面观察的图6的装置的示图。图8b示出所述电极64可以如何分布在所述芯片30周围的示例。然而,在其它实施方式中,所述电极64可以以图8b所示方式以外的其它方式分布。
图8c示出了从所述电子装置80的布置有所述互连体70的面观察的电子装置80的示图。在图8c中,所述焊盘72均匀分布在所述互连体70的表面上。然而,在其它实施方式中,所述焊盘72可以以图8c所示方式以外的其它方式分布,且不一定均匀分布在所述互连体70的表面上。
在一些实施方式中,所述电子装置80的制造可以包括将焊球90附接到所述互连体70的一个或多个焊盘72上的附加步骤,如图9所示。另外地或者备选地,可以将焊球(未示出)附接到所述层压基板10的一个或多个焊盘20上。
具有多个导电层12a-d的层压基板10的优势是所述焊盘20可以放置得相对密集,即单位面积上有相对多的焊盘20。例如,与美国专利2007/0296065 A1中所公开的导电基板的焊盘的密度受所述导电基板的布线能力限制的封装相比,所述层压基板10的焊盘20可以放置得较密集,比如,这是因为所述焊盘20和沿从所述焊盘到所述电极64的路线的导线的部分或全部可以在不同的导电层12a-d中实现。因此,由于可将相对大数量的焊盘20局限在相对小的面积内,则在所述电子装置80中使用所述层压基板10提供了相对高效的空间利用率。尽管具有单导电层的层压基板10的布线能力不像具有多个导电层12a-d的层压基板10一样好且因此无法具有与后者相同的焊盘密度,但与例如US2007/0296065 A1的导电基板相比,其仍促进了较高的焊盘密度,例如这是由于接线可以制造得比US 2007/0296065 A1的导电基板的接线薄很多。而且,具有包括单导电层的层压基板10的实施方式具有比包括多个导电层12a-d的层压基板10的厚度薄的另一优势。
使用所述层压基板10的另一优势是,可以在组装所述电子装置80之前,在分开的独立的生产步骤中生产和测试(例如,针对生产故障,例如短路故障或断路故障)所述层压基板10,从物流的观点看这是有益的。例如,在组装所述电子装置80之前,可以从生产线上移除有问题的层压基板10。
此外,由于可以利用完善的有机BGA的制造方法制造所述层压基板10,因此制造所述层压基板10的成本和复杂度可以相对低。
此外,利用薄膜制造工艺产生所述互连体70的所述电子装置80的实施方式具有可以使所述电子装置80的厚度相对小的优势,由此进一步提高空间利用率。
已利用上述实施方式描述了单个电子装置80的制造。然而,根据本发明的实施方式的电子装置80也适于并行制造,举例而言,例如晶圆级封装。根据本发明的实施方式,这样的并行制造从一组多个并排放置的层压基板10形成多个并排放置的电子装置80开始。然后将这些电子装置80分开,例如通过切割,以形成一个个的电子装置80。
根据本发明的实施方式,所述电子装置80可以包括在电子设备200中,如图10示意性地所示。在一些实施方式中,根据本发明的实施方式的若干这样的电子装置80可包括在该电子设备200中,并且以3D封装形式彼此层叠地安装以有效利用所述电子设备200内的空间。这在图11中示出,图11示出两个电子装置80,第一个电子装置安装在所述电子设备200的PCB 250上,第二个电子装置安装在第一个电子装置上。还如图11所示,在所述电子设备200中,可将其它无源或有源的电子元件(例如元件260和元件270)安装在一个或多个电子装置80上。所述电子设备200的若干电子装置80不需要相同。例如,对于所述电子设备200内的不同的电子装置80而言,所包括的芯片30的电子功能可以不同。
由于有效地利用了空间,在便携式电子设备中使用所述电子装置80可以尤其有益。因此,所述电子设备200可以是便携式电子设备,例如但不局限于手机、便携式媒体播放器、便携式卫星导航设备(如便携式GPS(全球定位系统)设备)、笔记本电脑、传呼机、通信器(或电子记事本)、智能电话或个人数字助理(PDA)。然而,所述电子装置80还可以用在其它类型的电子设备中,例如但不局限于固定计算机或固定卫星导航装置(例如安装在交通工具中,如汽车)。
参照具体实施方式对本发明进行了以上描述。然而,以上描述之外的其它实施方式可能在本发明的范围内。与以上描述的方法步骤不同的方法步骤可以提供在本发明的范围内。所述实施方式的不同特征和步骤可以组合在与所描述的组合体不同的其他组合体中。本发明的范围仅由所附的专利权利要求限定。
Claims (17)
1.一种电子装置(80),所述电子装置包括:
至少一个电子芯片(30),所述电子芯片在其第一面上具有互连焊盘(32);和
用于所述电子芯片(30)的封装件,所述封装件包括:
-层压基板(10),所述层压基板由多个包含导电材料(14)的导电层(12a-d)和由介电材料(17)的一个或多个绝缘层(16a-c)的层压件制成,其中,所述电子芯片(30)以所述电子芯片(30)的第二面附接在所述层压基板(10)的第一面上且附接在第一区域中,所述电子芯片(30)的所述第二面与所述电子芯片(30)的第一面相反并面向所述层压基板(10)的所述第一面,且所述层压基板(10)包括形成在所述层压基板(10)的第二面上的所述层压基板(10)的导电层(12d)中的多个焊盘(20),所述层压基板(10)的第二面与所述层压基板(10)的第一面相反;
-电绝缘材料的绝缘体(60),所述绝缘体(60)围绕所述电子芯片(30)形成在所述层压基板(10)的所述第一面上,其中,所述绝缘体(60)的第一表面与所述电子芯片(30)的第一面共面;
-导电材料的多个电极(64),所述电极(64)形成在所述层压基板(10)的第一面上且在第二区域中,其中,所述第二区域在所述第一区域外,且所述电极(64)穿过所述绝缘体(60)延伸;
-对于所述层压基板(10)的所述多个焊盘(20)中的每个焊盘(20),在所述层压基板的多个导电层(12a-d)中和穿过所述层压基板(10)的一个或多个绝缘层(16a-c)的一个或多个导电通道(18)中形成接线,所述接线用以将所述焊盘(20)和至少一个电极(64)电连接;和
-互连体(70),所述互连体形成在所述绝缘体(60)的第一表面和所述电子芯片(30)的所述第一面上,其中,所述互连体(70)包括:多个焊盘(72),所述多个焊盘在所述互连体(70)的与所述互连体(70)的面向所述电子芯片(30)和所述绝缘体(60)的面相反的面上;以及用于所述电子芯片(30)的焊盘(32)、所述电极(64)和所述互连体(70)的焊盘(72)之间的电连接的接线(74)。
2.如权利要求1所述的电子装置(80),其中,利用薄膜工艺形成所述互连体(70),以产生所述互连体(70)的所述焊盘(72)、所述互连体(70)的接线(74)以及所述互连体(70)的电绝缘材料(76)。
3.如权利要求1或2所述的电子装置(80),其中,所述层压基板(10)的所述绝缘层(16a-c)中的至少一个绝缘层包括聚合树脂材料。
4.如权利要求3所述的电子装置(80),其中,所述聚合树脂材料被加固。
5.如权利要求3所述的电子装置(80),其中,所述聚合树脂材料包括味之素内置膜、苯并环丁烯、双马来酰亚胺三嗪、环氧树脂、聚酯、聚酰亚胺和/或聚四氟乙烯。
6.如权利要求1或2所述的电子装置(80),其中,利用有机球栅阵列BGA基板制造工艺形成所述层压基板(10)。
7.如权利要求1或2所述的电子装置(80),其中,所述绝缘体(60)被传递模塑。
8.如权利要求1或2所述的电子装置(80),其中,所述电子装置(80)还包括焊球(90),所述焊球(90)附接在所述互连体(70)的一个或多个焊盘(72)上和/或所述层压基板(10)的一个或多个焊盘(20)上。
9.一种电子设备,所述电子设备包括第一个如前述任一项权利要求所述的电子装置(80)。
10.如权利要求9所述的电子设备,其中,所述电子设备还包括印刷电路板PCB(250)和第二个如权利要求1到8中任一项所述的电子装置(80),其中,第一个电子装置(80)安装在所述PCB(250)上,第二个电子装置(80)以3D封装形式安装在所述第一个电子装置(80)上。
11.如权利要求9或10所述的电子设备,其中,所述电子设备(200)是便携式电子设备。
12.如权利要求11所述的电子设备,其中,所述便携式电子设备是手机、电脑、便携式媒体播放器、卫星导航装置、传呼机、电子记事本、或个人数字助理PDA。
13.一种用于制造如权利要求1到8中任一项所述的电子装置(80)的方法,所述方法包括:
将所述电子芯片(30)附接到所述层压基板(10);
利用模塑法形成所述绝缘体(60);
在待形成电极(64)的位置,提供贯穿所述绝缘体(60)的孔(62);
通过向所述绝缘体(60)中提供的所述孔(62)供应导电材料,产生所述电极(64);
通过重复地执行薄膜沉积或电镀,以及选择性去除交替的介电材料和导电材料,形成所述互连体(70)。
14.如权利要求13所述的方法,其中,供应所述电极(64)的导电材料包括利用电镀法或溅射法供应所述导电材料。
15.如权利要求13或14所述的方法,其中,所述方法还包括将焊球(90)附接到所述互连体(70)的一个或多个焊盘(72)和/或所述层压基板(10)的一个或多个焊盘(20)。
16.如权利要求13或14所述的方法,其中,所述方法包括利用有机BGA基板制造工艺形成所述层压基板(10)。
17.如权利要求13或14所述的方法,其中,利用模塑法形成所述绝缘体(60)包括:
将附接有所述电子芯片(30)的层压基板(10)放置在传递模具(50)中;
将模塑料注入到所述传递模具(50)中以形成所述绝缘体(60)。
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US (1) | US8749049B2 (zh) |
EP (1) | EP2309535A1 (zh) |
KR (1) | KR20120095357A (zh) |
CN (1) | CN102696105B (zh) |
WO (1) | WO2011042256A1 (zh) |
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CN109244642A (zh) * | 2018-08-07 | 2019-01-18 | 清华大学 | 封装天线及其制造方法 |
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US9219029B2 (en) | 2011-12-15 | 2015-12-22 | Stats Chippac Ltd. | Integrated circuit packaging system with terminals and method of manufacture thereof |
US8623711B2 (en) * | 2011-12-15 | 2014-01-07 | Stats Chippac Ltd. | Integrated circuit packaging system with package-on-package and method of manufacture thereof |
US8629567B2 (en) | 2011-12-15 | 2014-01-14 | Stats Chippac Ltd. | Integrated circuit packaging system with contacts and method of manufacture thereof |
RU2504046C1 (ru) * | 2012-07-12 | 2014-01-10 | Открытое акционерное общество "Концерн радиостроения "Вега" | Способ получения межсоединений в высокоплотных электронных модулях |
US9818734B2 (en) | 2012-09-14 | 2017-11-14 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming build-up interconnect structures over a temporary substrate |
US10192796B2 (en) | 2012-09-14 | 2019-01-29 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming dual-sided interconnect structures in FO-WLCSP |
US20140210106A1 (en) * | 2013-01-29 | 2014-07-31 | Apple Inc. | ULTRA THIN PoP PACKAGE |
US9627338B2 (en) * | 2013-03-06 | 2017-04-18 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming ultra high density embedded semiconductor die package |
JP6199094B2 (ja) * | 2013-06-28 | 2017-09-20 | 富士機械製造株式会社 | 回路機器製造方法および、成形用の型 |
US9502270B2 (en) | 2014-07-08 | 2016-11-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device packages, packaging methods, and packaged semiconductor devices |
US9893017B2 (en) | 2015-04-09 | 2018-02-13 | STATS ChipPAC Pte. Ltd. | Double-sided semiconductor package and dual-mold method of making same |
US10787303B2 (en) | 2016-05-29 | 2020-09-29 | Cellulose Material Solutions, LLC | Packaging insulation products and methods of making and using same |
US11078007B2 (en) | 2016-06-27 | 2021-08-03 | Cellulose Material Solutions, LLC | Thermoplastic packaging insulation products and methods of making and using same |
CN109979890A (zh) * | 2017-12-28 | 2019-07-05 | 凤凰先驱股份有限公司 | 电子封装件及其制法 |
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- 2010-08-27 KR KR1020127008889A patent/KR20120095357A/ko not_active Application Discontinuation
- 2010-08-27 CN CN201080045635.3A patent/CN102696105B/zh not_active Expired - Fee Related
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CN109244642A (zh) * | 2018-08-07 | 2019-01-18 | 清华大学 | 封装天线及其制造方法 |
Also Published As
Publication number | Publication date |
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US8749049B2 (en) | 2014-06-10 |
CN102696105A (zh) | 2012-09-26 |
EP2309535A1 (en) | 2011-04-13 |
US20120273947A1 (en) | 2012-11-01 |
KR20120095357A (ko) | 2012-08-28 |
WO2011042256A1 (en) | 2011-04-14 |
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