TW201832343A - 封裝 - Google Patents

封裝 Download PDF

Info

Publication number
TW201832343A
TW201832343A TW106143032A TW106143032A TW201832343A TW 201832343 A TW201832343 A TW 201832343A TW 106143032 A TW106143032 A TW 106143032A TW 106143032 A TW106143032 A TW 106143032A TW 201832343 A TW201832343 A TW 201832343A
Authority
TW
Taiwan
Prior art keywords
dielectric
integrated circuit
patch antenna
layer
dielectric layer
Prior art date
Application number
TW106143032A
Other languages
English (en)
Other versions
TWI708363B (zh
Inventor
余振華
劉重希
史朝文
吳凱強
張守仁
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201832343A publication Critical patent/TW201832343A/zh
Application granted granted Critical
Publication of TWI708363B publication Critical patent/TWI708363B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P3/00—Waveguides; Transmission lines of the waveguide type
    • H01P3/003—Coplanar lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/12—Supports; Mounting means
    • H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/36—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith
    • H01Q1/38—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith formed by a conductive layer on an insulating support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/48—Earthing means; Earth screens; Counterpoises
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/50—Structural association of antennas with earthing switches, lead-in devices or lightning protectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/52—Means for reducing coupling between antennas; Means for reducing coupling between an antenna and another structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q9/00—Electrically-short antennas having dimensions not more than twice the operating wavelength and consisting of conductive active radiating elements
    • H01Q9/04—Resonant antennas
    • H01Q9/0407—Substantially flat resonant element parallel to ground plane, e.g. patch antenna
    • H01Q9/045—Substantially flat resonant element parallel to ground plane, e.g. patch antenna with particular feeding means
    • H01Q9/0457—Substantially flat resonant element parallel to ground plane, e.g. patch antenna with particular feeding means electromagnetically coupled to the feed line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H01L2221/68331—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding of passive members, e.g. die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6616—Vertical connections, e.g. vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6627—Waveguides, e.g. microstrip line, strip line, coplanar line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
    • H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/214—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29005—Structure
    • H01L2224/29006—Layer connector larger than the underlying bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29005—Structure
    • H01L2224/29007—Layer connector smaller than the underlying bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29075—Plural core members
    • H01L2224/2908—Plural core members being stacked
    • H01L2224/29082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29075—Plural core members
    • H01L2224/2908—Plural core members being stacked
    • H01L2224/29083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/95001—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q21/00—Antenna arrays or systems
    • H01Q21/06—Arrays of individually energised antenna units similarly polarised and spaced apart
    • H01Q21/061—Two dimensional planar arrays
    • H01Q21/065—Patch antenna array

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Electromagnetism (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Waveguide Aerials (AREA)
  • Variable-Direction Aerials And Aerial Arrays (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

一種實施例封裝包括：積體電路晶粒，包封在包封體中；貼片式天線，位於所述積體電路晶粒之上；以及介電特徵，設置在所述積體電路晶粒與所述貼片式天線之間。所述貼片式天線在俯視圖中與所述積體電路晶粒交疊。所述介電特徵的厚度是根據所述貼片式天線的工作頻寬。

Description

封裝
本發明實施例是有關於一種封裝。
由於各種電子元件（例如，電晶體、二極體、電阻器、電容器等）的集成密度持續增大，半導體行業已經歷快速增長。在很大程度上，集成密度的增大來自於最小特徵尺寸（feature size）的不斷縮減，這使得能夠將更多的元件集成到給定區域中。隨著對縮減電子裝置尺寸的需求的增長，需要更小且更具創造性的半導體晶粒封裝技術。這種封裝系統的一個實例是疊層封裝（Package-on-Package，PoP）技術。在疊層封裝裝置中，將頂部半導體封裝堆疊在底部半導體封裝的頂上，以提供高集成程度及高元件密度。疊層封裝技術一般來說能夠生產功能性得到增強且在印刷電路板（printed circuit board，PCB）上的佔用面積小的半導體裝置。
本發明實施例的一種封裝包括：積體電路晶粒，包封在包封體中；裝置，位於所述積體電路晶粒之上；以及介電特徵，設置在所述積體電路晶粒與所述裝置之間。所述裝置在俯視圖中與所述積體電路晶粒交疊。所述裝置包括訊號線及接地元件。所述介電特徵的厚度是根據所述裝置的工作頻寬。
以下公開內容提供用於實作本發明的不同特徵的許多不同的實施例或實例。以下闡述元件及配置的具體實例以簡化本公開內容。當然，這些僅為實例且不旨在進行限制。舉例來說，以下說明中將第一特徵形成在第二特徵“之上”或第二特徵“上”可包括其中第一特徵及第二特徵被形成為直接接觸的實施例，且也可包括其中第一特徵與第二特徵之間可形成有附加特徵、以使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本公開內容可能在各種實例中重複使用參考編號及/或字母。這種重複使用是出於簡潔及清晰的目的，而不是自身表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如“在...之下（beneath）”、“在...下面（below）”、“下部的（lower）”、“在...上方（above）”、“上部的（upper）”等空間相對性用語來闡述圖中所示的一個元件或特徵與另一（其他）元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的取向外還囊括裝置在使用或操作中的不同取向。設備可具有其他取向（旋轉90度或其他取向），且本文中所用的空間相對性用語可同樣相應地進行解釋。
本文所論述的實施例可在具體上下文中論述，即在具有一個或多個集成天線及一個或多個半導體晶片（例如，射頻（radio frequency，RF）晶片、基頻（baseband）晶片等）的封裝結構的上下文中論述。然而，也可對具有集成有一或多個半導體晶片的嵌置功能元件（例如，波導線）的其他封裝應用各種實施例。
在具有集成天線的實施例中，集成天線包括貼片式天線，所述貼片式天線具有一或多條訊號線（在本文中也被稱為饋電線（feed line））、接地元件、以及一或多個輻射元件。在運行期間，射頻晶片通過饋電線從貼片式天線的輻射元件接收訊號或將訊號傳送到貼片式天線的輻射元件。接地元件包括接地線及/或為所述一個或多個輻射元件提供電接地的接地平面。通過將天線與半導體晶片集成在單個封裝中，可實現尺寸的減小。
為有利地實現小的封裝佔用面積，在俯視圖中，貼片式天線的一些部分與至少一個半導體晶片交疊。然而，已觀察到，這種交疊可因由半導體晶片造成的干擾而引起貼片式天線的效率降低。各種實施例旨在通過在半導體晶片與貼片式天線（例如，貼片式天線的饋電線及接地元件）之間設置介電特徵來提高貼片式天線的效率及減小來自半導體晶片的干擾。在一些實施例中，介電特徵包括晶粒貼合膜（die attach film），所述晶粒貼合膜用於在製造期間將半導體晶片貼合到封裝。對介電特徵的厚度加以選擇來實現貼片式天線的期望效率。所述厚度可進一步對應於貼片式天線與半導體晶片之間的距離。舉例來說，已觀察到，相對厚的介電特徵可在貼片式天線與半導體晶片之間提供改善的隔離。在一些實施例中，介電特徵的厚度是基於天線的工作頻寬（operating bandwidth）、介電特徵的k值、貼片式天線的各種特徵的面積、貼片式天線的期望效率、其組合等來加以選擇。
圖1A示出根據一些實施例的半導體封裝250的剖視圖。圖1B及圖1C示出根據一些實施例的半導體封裝250的俯視圖。圖1A所示剖視圖是沿圖1B及圖1C所示線1A-1A截取。
首先參照圖1A，半導體封裝250包括包封在包封體130中的積體電路晶粒114。積體電路晶粒114可為射頻（RF）晶片，所述射頻晶片可包括或可不包括集成在積體電路晶粒114內的基頻處理器。儘管在半導體封裝250中僅示出一個積體電路晶粒，然而根據封裝設計而定，在其他實施例中在單個半導體封裝中可集成有多個積體電路晶粒114（例如，單獨的基頻晶片、處理器、記憶體等）。在這些實施例中，所述多個積體電路晶粒114中的每一者可被包封在包封體130中。
在運行期間，積體電路晶粒114通過集成在半導體封裝250中的一個或多個天線來傳送及接收無線訊號。舉例來說，半導體封裝250包括貼片式天線210，貼片式天線210包括接地元件106A、饋電線106B、介電層200的一部分、以及輻射元件204。在封裝250中，接地元件106A與饋電線106B設置在同一層中。舉例來說，饋電線106B可設置在延伸穿過接地元件106A的開口中，如圖1A及圖1C所示。在圖1A、圖1B、及圖1C所示的實施例中，接地元件106A可進一步為饋電線106B提供遮罩（電磁輻射遮罩）。接地元件106A的頂表面及底表面與饋電線106B的頂表面及底表面可實質上共面。在圖1C中由虛線標記輻射元件204的位置以供參考。在其他實施例中可使用實施例貼片式天線的其他配置（例如，具有更大或更小數目的饋電線）。
積體電路晶粒114通過重佈線結構170中的重佈線以及導通孔110而電連接到接地元件106A及饋電線106B。舉例來說，重佈線結構170可包括設置在一個或多個介電層中的多條導電重佈線。導通孔110設置在包封體130（可為模塑化合物）中且將接地元件106A及饋電線106B電連接到重佈線結構170中的重佈線。因此，導通孔110將接地元件106A及饋電線106B電連接到積體電路晶粒114。重佈線結構170中的重佈線進一步將積體電路晶粒114電連接到外部連接件166，外部連接件166可用於將封裝250結合到另一封裝元件，例如封裝基底（參見圖25）。
在一些實施例中，輻射元件204通過介電層200及可選介電層104而與接地元件106A及饋電線106B隔開。舉例來說，輻射元件204可黏著至介電層200的與接地元件106A/饋電線106B相對的表面。輻射元件204可使用黏合劑202而黏著到介電層200，或者可省略黏合劑202。輻射元件204電耦合到接地元件106A及饋電線106B。在一些實施例中，可對介電層200的材料加以選擇以促進這種電耦合且介電層200的材料可具有相對低的耗散因數（dissipation factor，Df）。舉例來說，介電層200的耗散因數可小於約0.01或者在一些實施例中甚至小於約0.001。接地元件106A可為輻射元件204提供接地平面，且饋電線106B在輻射元件204與積體電路晶粒114之間中繼訊號206。輻射元件204繼而從半導體封裝250外部的其他裝置接收無線訊號208以及將無線訊號208傳送到半導體封裝250外部的其他裝置。
如由圖1B所提供的封裝250的俯視圖所示，積體電路晶粒114（在圖1B中以虛像（ghost）示出）與接地元件106A/饋電線106B（在圖1B中以虛像示出）交疊。特徵的這種交疊可導致貼片式天線210（參見圖1A）效率降低。舉例來說，貼片式天線210的效率可能會因由積體電路晶粒114造成的干擾而降低。
為減弱這種干擾並提高貼片式天線210的效率，將介電特徵116並置在積體電路晶粒114與貼片式天線210（例如，貼片式天線210的一些部分（接地元件106A/饋電線106B））之間。介電特徵116會增強積體電路晶粒114與貼片式天線210的一些部分（例如，接地元件106A/饋電線106B）之間的隔離。介電特徵116具有厚度d ，厚度d 是從貼片式天線210的面對積體電路晶粒114的表面到積體電路晶粒114測得。在各種實施例中，厚度d 相對厚以在積體電路晶粒114與貼片式天線210之間提供合適的隔離。儘管不受限於任何特定理論，然而據信貼片式天線210的效率可由積體電路晶粒與接地元件106A/饋電線106B之間的寄生電容（parasitic capacitance）來近似表示。舉例來說，這些特徵的較低的寄生電容與貼片式天線210的提高的效率相關。另外，積體電路晶粒114與接地元件106A/饋電線106B之間的寄生電容可滿足以下方程式：其中C 是積體電路晶粒114與接地元件106A/饋電線106B之間的寄生電容；k 是介電特徵116的k值；d 是介電特徵116的厚度d；A 是接地元件106A/饋電線106B的面積（例如，通過將接地元件106A/饋電線106B的長度L乘以接地元件106A/饋電線106B的寬度W而獲得，參見圖1B）；且λ是貼片式天線210的工作波長。各種實施例操縱以上參數中的一個或多個以減小寄生電容C 並提高封裝250中的貼片式天線210的效率。
在各種實施例中，介電特徵116的厚度d 是根據貼片式天線210的工作頻寬（頻率）、介電特徵116的k值、貼片式天線210的各種特徵（例如，接地元件106A及/或饋電線106B）的面積、貼片式天線210的期望效率、其組合等來加以選擇。舉例來說，當介電特徵116的k值為約3或大於3且貼片式天線210具有為約60 GHz的工作頻寬時，介電特徵116的厚度d 可為至少100 μm。作為另一實例，當介電特徵116的k值小於3（例如，約1）且貼片式天線210具有為約60 GHz的工作頻寬時，介電特徵116的厚度d 可為至少30 μm。作為另一實例，當介電特徵116的k值為約3或大於3且貼片式天線210具有為約77 GHz的工作頻寬時，介電特徵116的厚度d 可為至少約50 μm。作為另一實例，當介電特徵116的k值小於3（例如，約1）且貼片式天線210具有為約77 GHz的工作頻寬時，介電特徵116的厚度d 可為至少約15 μm。作為另一實例，當介電特徵116的k值為約3或大於3且貼片式天線210具有為約38 GHz的工作頻寬時，介電特徵116的厚度d 可為至少約120 μm。作為另一實例，當介電特徵116的k值小於3（例如，約1）且貼片式天線210具有為約38GHz的工作頻寬時，介電特徵116的厚度d 可為至少約40 μm。
已觀察到，當積體電路晶粒114的厚度d 處於以上值以內時，貼片式天線210的效率處於基線（baseline）貼片式天線的效率的95%以內，而不具有來自積體電路晶粒的干擾。舉例來說，已對具有為約77 GHz至約81 GHz的工作頻寬的貼片式天線以及具有為約57 GHz至約64 GHz的工作頻寬的貼片式天線進行了實驗。已在分別集成在介電特徵具有約0 μm、20 μm、40 μm、50 μm、60 μm、80 μm、及100 μm的不同厚度d 的封裝中的各貼片式天線之間進行了比較。也在不具有來自積體電路晶粒的干擾的基線貼片式天線之間進行了比較。當厚度d 為0 μm且貼片式天線的工作頻寬為約77 GHz至約81 GHz時，貼片式天線的增益為7.1 dBi且貼片式天線的效率為41%。當厚度d 為20 μm且貼片式天線的工作頻寬為約77 GHz至約81 GHz時，貼片式天線的增益為9.7 dBi且貼片式天線的效率為70%。當厚度d 為40 μm且貼片式天線的工作頻寬為約77 GHz至約81 GHz時，貼片式天線的增益為10.2 dBi且貼片式天線的效率為82%。當厚度d 為50 μm且貼片式天線的工作頻寬為約77 GHz至約81 GHz時，貼片式天線的增益為10.3 dBi且貼片式天線的效率為84%。當厚度d 為60 μm且貼片式天線的工作頻寬為約77 GHz至約81 GHz時，貼片式天線的增益為10.3 dBi且貼片式天線的效率為86%。當厚度d 為80 μm且貼片式天線的工作頻寬為約77 GHz至約81 GHz時，貼片式天線的增益為10.4 dBi且貼片式天線的效率為88%。當厚度d 為100 μm且貼片式天線的工作頻寬為約77 GHz至約81 GHz時，貼片式天線的增益為10.5 dBi且貼片式天線的效率為89%。具有為約77 GHz至約81 GHz的工作頻寬的基線貼片式天線提供為10.5 dBi的增益，且所述基線貼片式天線的效率為90%。當厚度d 為20 μm且貼片式天線的工作頻寬為約57 GHz至約64 GHz時，貼片式天線的頻寬規格無效，貼片式天線的增益為3.95 dBi，且貼片式天線的效率為42.4%。當厚度d 為40 μm且貼片式天線的工作頻寬為約57 GHz至約64 GHz時，貼片式天線的增益為5.3 dBi且貼片式天線的效率為66.3%。當厚度d 為50 μm且貼片式天線的工作頻寬為約57 GHz至約64 GHz時，貼片式天線的增益為5.48 dBi且貼片式天線的效率為70.6%。當厚度d 為60 μm且貼片式天線的工作頻寬為約57 GHz至約64 GHz時，貼片式天線的增益為5.62 dBi且貼片式天線的效率為73.3%。當厚度d 為100 μm且貼片式天線的工作頻寬為約57 GHz至約64 GHz時，貼片式天線的增益為5.88 dBi且貼片式天線的效率為78.3%。具有為約57 GHz至約64 GHz的工作頻寬的基線貼片式天線提供為6.12 dBi的增益，且所述基線貼片式天線的效率為82%。
所有以上值均假設接地元件106A/饋電線106B具有恒定的面積A 。一般來說，還觀察到，減小接地元件106A/饋電線106B的面積A 也可使得能夠在仍實現期望效率的同時具有較小的厚度d 。
在圖1A中，將介電特徵116示出為單個介電層。在其他實施例中，介電特徵116可具有任何數目的包含不同材料的介電層。舉例來說，介電特徵116可具有兩個介電層116A及116B（例如，如由圖2A所示）或三個介電層116A、116B及116C（例如，如由圖2B所示）。介電特徵116內的介電層中的每一者可包含晶粒貼合膜、背側塗布膠帶（LC）、預浸體（prepreg，PP）材料、低介電常數材料、或類似材料。介電特徵116可具有與積體電路晶粒114相同的寬度（例如，在介電特徵116的相對的側壁之間測得）（例如，如由圖1A所示），具有比積體電路晶粒114大的寬度（例如，如由圖2C所示），或者具有比積體電路晶粒114小的寬度（例如，如由圖2D所示）。另外，介電層中的每一者（例如，介電層116A、116B、及/或116C）可具有相同的寬度（例如，如由圖2A、圖2B、圖2C、及圖2D所示）或者不同的寬度（例如，如由圖2E所示）。當介電特徵116包括多個介電層時，可使用主要介電層116A的厚度及/或k值作為近似值來計算厚度d 以減小寄生電容。主要介電層116A可為佔據整個介電特徵116的大部分體積（例如，大於50%（例如，大於約80%））的介電層。在其他實施例中，可使用k值及/或厚度的權重平均值來計算厚度d 以減小寄生電容。
半導體封裝250可還包括附加天線，例如輻射天線108。在一些實施例中，輻射天線108包括延伸穿過包封體130的導電特徵。輻射天線108通過重佈線結構170中的重佈線電連接到積體電路晶粒114。對輻射天線108的形狀及配置加以選擇以使得能夠向位於封裝250外部的其他裝置（圖中未示出）發送無線訊號以及從位於封裝250外部的其他裝置（圖中未示出）接收無線訊號。在其他實施例中，可省略輻射天線108。
圖3A、圖3B、及圖3C示出根據一些實施例的半導體封裝280的各種圖。圖3A示出半導體封裝280的剖視圖；圖3B示出接地元件106A的俯視圖，且圖3C示出饋電線106B及可選接地元件106C的俯視圖。封裝280實質上相似於封裝250，其中相同的參考編號表示相同的元件。在封裝280中，接地元件106A與饋電線106B設置在不同的層中。舉例來說，接地元件106A可沿與半導體封裝280的側表面垂直的線設置在饋電線106B與積體電路晶粒之間。在一些實施例中，可選附加接地元件106C（參見圖3C）可與饋電線106B設置在同一層中。
圖4至圖26B示出根據一些實施例的在用於形成半導體封裝250的製程期間的中間步驟的剖視圖。圖4示出載板基底100以及形成在載板基底100上的釋放層102。分別示出用於形成第一封裝及第二封裝的第一封裝區600及第二封裝區602。
載板基底100可為玻璃載板基底、陶瓷載板基底或類似基底。載板基底100可為晶圓，使得可在載板基底100上同時形成多個封裝。釋放層102可由聚合物類材料形成，所述聚合物類材料可與載板基底100一起從將在後續步驟中形成的上覆結構被移除。在一些實施例中，釋放層102是在受熱時會喪失其黏著性質的環氧樹脂類熱釋放材料，例如光熱轉換（light-to-heat-conversion，LTHC）釋放塗層。在其他實施例中，釋放層102可為在暴露至紫外光時會喪失其黏著性質的紫外光（ultra-violet，UV）膠。釋放層102可作為液體進行分配並進行固化，可為被疊層到載板基底100上的疊層膜（laminate film），或可為類似形式。釋放層102的頂表面可為齊平（leveled）且可具有高的共面度（degree of coplanarity）。
在圖5中，形成介電層104及金屬化圖案（例如，接地元件106A及饋電線106B）。如圖2所示，在釋放層102上形成介電層104。介電層104的底表面可接觸釋放層102的頂表面。在一些實施例中，介電層104是由例如以下聚合物形成：聚苯并噁唑（polybenzoxazole，PBO）、聚醯亞胺（polyimide）、苯并環丁烯（benzocyclobutene，BCB）。在其他實施例中，介電層104是由氮化物（例如，氮化矽）、氧化物（例如，氧化矽）、磷矽酸鹽玻璃（phosphosilicate glass，PSG）、硼矽酸鹽玻璃（borosilicate glass，BSG）、摻雜有硼的磷矽酸鹽玻璃（boron-doped phosphosilicate glass，BPSG）等形成。可通過例如以下任何可接受的沉積製程來形成介電層104：旋轉塗布（spin coating）、化學氣相沉積（chemical vapor deposition，CVD）、疊層、類似製程、或其組合。可將介電層104形成為提供實質上平坦的頂表面以形成後續特徵。
金屬化圖案可包括接地元件106A及饋電線106B，例如，如圖1A、圖1B、及圖1C所示。作為形成接地元件106A及饋電線106B的實例，在介電層104之上形成晶種層（圖中未示出）。在一些實施例中，晶種層是金屬層，所述金屬層可為單個層或為包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。可使用例如物理氣相沉積（physical vapor deposition，PVD）等來形成晶種層。接著在晶種層上形成光阻（photo resist）並將所述光阻圖案化。可通過旋轉塗布或類似製程來形成光阻且可將光阻暴露至光以進行圖案化。光阻的圖案對應於接地元件106A及饋電線106B。所述圖案化會形成穿過光阻的開口以暴露出晶種層。在光阻的開口中以及在晶種層的暴露的部分上形成導電材料。導電材料可通過鍍覆（例如，電鍍或無電鍍覆等）來形成。導電材料可包括金屬，如銅、鈦、鎢、鋁等。接著，移除光阻以及晶種層的上面未形成導電材料的部分。光阻可通過可接受的灰化製程（ashing process）或剝除製程（stripping process）來移除，例如使用氧電漿或類似製程等。一旦光阻被移除，便例如使用可接受的刻蝕製程（例如，通過濕刻蝕（wet etching）或乾刻蝕（dry etching））來移除晶種層的暴露部分。晶種層的剩餘部分與導電材料形成接地元件106A及饋電線106B。
介電層104及介電層104上形成的金屬化圖案（例如，接地元件106A及饋電線106B）可被稱為背側金屬化結構。如圖中所示，背側金屬化結構包括一個介電層104及一個金屬化圖案（接地元件106A及饋電線106B）。在其他實施例中，背側重佈線結構可包括任何數目的介電層、金屬化圖案、及通孔。舉例來說，當饋電線106B及接地元件106A設置在不同的層中時（例如，如由圖3A、圖3B、及圖3C所示），背側重佈線結構可包括形成在兩個介電層中的兩個金屬化圖案。在這些實施例中，可將接地元件106A形成在饋電線106B之上或下方。可通過重複進行所述形成介電層104、饋電線106B、及接地元件106A的製程而在背側金屬化結構中形成一個或多個額外的金屬化圖案及介電層。可在所述形成金屬化圖案期間通過在下伏介電層的開口中形成金屬化圖案的晶種層及導電材料來形成通孔。通孔因此可對各個金屬化圖案（例如，圖3A中的饋電線106B及接地元件106A）進行互連及電耦合。
接下來在圖6中，形成穿孔（導通孔110）及（可選地）形成輻射天線108。作為形成穿孔（導通孔110）及輻射天線108的實例，在背側重佈線結構（例如，所示介電層104、接地元件106A、及饋電線106B）之上形成晶種層。在一些實施例中，晶種層是金屬層，所述金屬層可為單個層或為包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。可使用例如物理氣相沉積等來形成晶種層。在晶種層上形成光阻並將所述光阻圖案化。可通過旋轉塗布或類似製程來形成光阻且可將光阻暴露至光以進行圖案化。光阻的圖案對應於穿孔。所述圖案化會形成穿過光阻以暴露出晶種層的開口。在光阻的開口中以及在晶種層的暴露的部分上形成導電材料。導電材料可通過鍍覆（例如，電鍍或無電鍍覆等）來形成。導電材料可包括金屬，如銅、鈦、鎢、鋁等。移除光阻以及晶種層的上面未形成導電材料的部分。光阻可通過可接受的灰化製程或剝除製程來移除，例如使用氧電漿或類似製程等。一旦光阻被移除，便例如使用可接受的刻蝕製程（例如，通過濕刻蝕或乾刻蝕）來移除晶種層的暴露部分。所述晶種層的剩餘部分與所述導電材料形成穿孔（導通孔110）及（可選地）形成輻射天線108。如圖中所示，可將穿孔（導通孔110）直接形成在接地元件106A的一些部分上。在一些實施例中，穿孔（導通孔110）及輻射天線108同時形成。在其他實施例中，穿孔（導通孔110）可在輻射天線108之前或之後形成。
在圖7中，通過介電特徵116將積體電路晶粒114黏著到背側重佈線結構（例如，接地元件106A/饋電線106B）。如圖7所示，將一個積體電路晶粒114黏著到第一封裝區600及第二封裝區602中的每一者中，且在其他實施例中，可在每一區中黏著更多或更少的積體電路晶粒114。積體電路晶粒114可為射頻晶粒、基頻晶粒、邏輯晶粒（例如，中央處理器（central processing unit）、微控制器等）、記憶體晶粒（例如，動態隨機存取記憶體（dynamic random access memory，DRAM）晶粒、靜態隨機存取記憶體（static random access memory，SRAM）晶粒等）、電力管理晶粒（例如，電力管理積體電路（power management integrated circuit，PMIC）晶粒）、感測器晶粒、微機電系統（micro-electro-mechanical-system，MEMS）晶粒、訊號處理晶粒（例如，數位訊號處理（digital signal processing，DSP）晶粒）、前端晶粒（例如，模擬前端（analog front-end，AFE）晶粒）、類似晶粒、或其組合。另外，在一些實施例中，積體電路晶粒114可為不同尺寸（例如，不同的高度及/或表面積），且在其他實施例中，積體電路晶粒114可為相同尺寸（例如，相同的高度及/或表面積）。
在黏著到介電層104之前，可根據適用於在積體電路晶粒114中形成積體電路的製造製程來加工積體電路晶粒114。舉例來說，積體電路晶粒114各自分別包括半導體基底118，例如經摻雜的或未經摻雜的矽、或絕緣體上半導體（semiconductor-on-insulator，SOI）基底的主動層。半導體基底可包含：其他半導體材料，例如鍺；化合物半導體，包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、及/或銻化銦；合金半導體，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、及/或GaInAsP；或其組合。也可使用例如多層式基底（multi-layered substrate）或梯度基底（gradient substrate）等其他基底。可在半導體基底118中及/或半導體基底118上形成例如電晶體、二極體、電容器、電阻器等裝置且所述裝置可通過由例如位於半導體基底118上的一個或多個介電層中的金屬化圖案形成的內連線結構120進行互連以形成積體電路。
積體電路晶粒114還包括進行外部連接的接墊122，例如鋁接墊。接墊122位於可被稱為積體電路晶粒114的相應主動側的位置上。保護膜（passivation film）124位於積體電路晶粒114上且位於接墊122的部分上。開口穿過保護膜124到達接墊122。例如導電柱（例如，包含例如銅等金屬）等可選晶粒連接件126位於穿過保護膜124的開口中，並且機械地耦合到且電耦合到相應的接墊122。晶粒連接件126可通過例如鍍覆等來形成。晶粒連接件126對積體電路晶粒114的相應的積體電路進行電耦合。
可選介電材料128位於積體電路晶粒114的主動側上，例如位於保護膜124及晶粒連接件126上。介電材料128在橫向上包封晶粒連接件126，且介電材料128在橫向上與相應的積體電路晶粒114相接。介電材料128可為：聚合物，例如聚苯并噁唑、聚醯亞胺、苯并環丁烯等；氮化物，例如，氮化矽等；氧化物，例如氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜有硼的磷矽酸鹽玻璃等；類似材料、或其組合，且介電材料128可例如通過旋轉塗布、層疊、化學氣相沉積或類似方法形成。
在其他實施例中，可不包括晶粒連接件126及介電材料128，且可將後續形成的重佈線結構直接形成在保護膜124及接墊122上。舉例來說，在這些實施例中，可直接將已完成的重佈線結構170（參見圖21）形成在保護膜124及接墊122上以使得重佈線結構170中的金屬化圖案（有時稱為重佈線）138（參見圖21）接觸接墊122。
介電特徵116位於積體電路晶粒114的背側上並將積體電路晶粒114黏著到背側重佈線結構（例如，圖式中的介電層104）。介電特徵116可包括由例如以下任何合適的材料形成的一個或多個層：晶粒貼合膜、低介電常數材料、預浸體材料、背側塗布膠帶、或類似材料。如以上參照圖1A、圖1B、及圖1C所論述，可對介電特徵116的厚度加以選擇以改善積體電路晶粒114與包括接地元件106A及饋電線106B的貼片式天線（例如，圖1A及圖1C所示貼片式天線210）之間的隔離。與將半導體封裝的各個層製作成盡可能薄的傳統期望相反，可增大介電特徵116的厚度以改善接地元件106A/饋電線106B與積體電路晶粒114之間的隔離。在各種實施例中，介電特徵116的厚度可根據貼片式天線的工作頻寬（例如，頻率）、貼片式天線的期望效率、介電特徵116的k值、以及接地元件106A在俯視圖中的面積、其組合等來加以選擇。舉例來說，介電特徵116可具有以上參照圖1A、圖1B、及圖1C所論述的與k值及/或工作頻寬對應的厚度d 中的任意者。厚度d 也可對應於積體電路晶粒114與接地元件106A/饋電線106B之間的距離。
另外，儘管介電特徵116被示出為具有與相應的積體電路晶粒114相同寬度的單個層，然而介電特徵116也可包括由不同的介電材料形成的多個層及/或可比積體電路晶粒114（例如，如以上參照圖2A、圖2B、圖2C、圖2D、及圖2E所闡述）寬或窄。可將介電特徵116施加到積體電路晶粒114的背側，例如施加到相應的半導體晶圓的背側或者可施加到載板基底100的表面之上。可例如通過鋸切或切割來將積體電路晶粒114單體化，且使用例如拾取及放置工具（pick-and-place tool）通過介電特徵116將積體電路晶粒114黏著到接地元件106A/饋電線106B。因此，在對積體電路晶粒114進行貼合之後，介電特徵116可填充接地元件106A與饋電線106B之間的空間。舉例來說，介電特徵116可延伸穿過接地元件106A中的開口到達介電層104。
在圖8中，在各種元件上形成包封體130。包封體130可為模塑化合物、環氧樹脂等，且可通過壓縮模塑（compression molding）、轉移模塑（transfer molding）等來施加。在固化之後，包封體130可經歷研磨製程（grinding process）以暴露出穿孔（導通孔110）、輻射天線108、及晶粒連接件126。在研磨製程之後，穿孔（導通孔110）的頂表面、輻射天線108的頂表面、晶粒連接件126的頂表面、及包封體130的頂表面是共面的。在一些實施例中，例如如果已暴露出穿孔（導通孔110）、輻射天線108、及晶粒連接件126，則可省略所述研磨。
在圖9至圖18中，形成前側重佈線結構170（參見圖18）。如將在圖18中示出，前側重佈線結構170包括介電層132、140、148、及156以及金屬化圖案（有時稱為重佈線層或重佈線）138、146、及154。
在圖9中，在包封體130、穿孔（導通孔110）、輻射天線108及晶粒連接件126上沉積介電層132。在一些實施例中，介電層132是由可使用微影罩幕（lithography mask）進行圖案化的聚合物形成，所述聚合物可為例如聚苯并噁唑、聚醯亞胺、苯并環丁烯等感光性材料。在其他實施例中，介電層132由以下材料形成：氮化物，例如氮化矽；氧化物，例如氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜有硼的磷矽酸鹽玻璃；或類似材料。介電層132可通過旋轉塗布、層疊、化學氣相沉積、類似方法、或其組合來形成。
在圖10中，接著對介電層132進行圖案化。所述圖案化會形成開口以暴露出穿孔（導通孔110）的一些部分、輻射天線108的一些部分、以及晶粒連接件126的一些部分。可通過例如以下可接受的製程來進行圖案化：當介電層132是感光性材料時將介電層132暴露至光；或者使用例如各向異性刻蝕（anisotropic etch）進行刻蝕。如果介電層132是感光性材料，則可在曝光之後對介電層132進行顯影。
在圖11中，在介電層132上形成具有通孔的金屬化圖案138。作為形成金屬化圖案138的實例，在介電層132之上以及在穿過介電層132的開口中形成晶種層（圖中未示出）。在一些實施例中，晶種層是金屬層，所述金屬層可為單個層或為包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。可例如利用物理氣相沉積等來形成所述晶種層。接著在晶種層上形成光阻並將所述光阻圖案化。可通過旋轉塗布或類似製程來形成光阻且可將光阻暴露至光以進行圖案化。光阻的圖案對應於金屬化圖案138。所述圖案化會形成穿過光阻的開口以暴露出晶種層。在光阻的開口中以及在晶種層的暴露的部分上形成導電材料。導電材料可通過鍍覆（例如，電鍍或無電鍍覆等）來形成。導電材料可包括金屬，如銅、鈦、鎢、鋁等。接著，移除光阻以及晶種層的上面未形成導電材料的部分。光阻可通過可接受的灰化製程或剝除製程來移除，例如使用氧電漿或類似製程等。一旦光阻被移除，便例如使用可接受的刻蝕製程（例如，通過濕刻蝕或乾刻蝕）來移除晶種層的暴露部分。晶種層的剩餘部分與導電材料形成金屬化圖案138及通孔。通孔形成在穿過介電層132而到達例如穿孔（導通孔110）、輻射天線108、及/或晶粒連接件126的開口中。
在圖12中，在金屬化圖案138及介電層132上沉積介電層140。在一些實施例中，介電層140是由可使用微影罩幕進行圖案化的聚合物形成，所述聚合物可為例如聚苯并噁唑、聚醯亞胺、苯并環丁烯等感光性材料。在其他實施例中，介電層140由以下材料形成：氮化物，例如氮化矽；氧化物，例如氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜有硼的磷矽酸鹽玻璃；或類似材料。介電層140可通過旋轉塗布、層疊、化學氣相沉積、類似方法或其組合來形成。
在圖13中，接著對介電層140進行圖案化。所述圖案化會形成開口以暴露出金屬化圖案138的一些部分。可通過例如以下可接受的製程來進行所述圖案化：當介電層是感光性材料時將介電層140暴露至光，或者使用例如各向異性刻蝕進行刻蝕。如果介電層140是感光性材料，則可在曝光之後對介電層140進行顯影。
在圖14中，在介電層140上形成具有通孔的金屬化圖案146。作為形成金屬化圖案146的實例，在介電層140之上以及在穿過介電層140的開口中形成晶種層（圖中未示出）。在一些實施例中，晶種層是金屬層，所述金屬層可為單個層或為包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。可使用例如物理氣相沉積等來形成晶種層。接著在晶種層上形成光阻並將所述光阻圖案化。可通過旋轉塗布或類似製程來形成光阻且可將光阻暴露至光以進行圖案化。光阻的圖案對應於金屬化圖案146。所述圖案化會形成穿過光阻的開口以暴露出晶種層。在光阻的開口中以及在晶種層的暴露的部分上形成導電材料。導電材料可通過鍍覆（例如，電鍍或無電鍍覆等）來形成。導電材料可包括金屬，如銅、鈦、鎢、鋁等。接著，移除光阻以及晶種層的上面未形成導電材料的部分。光阻可通過可接受的灰化製程或剝除製程來移除，例如使用氧電漿或類似製程等。一旦光阻被移除，便例如使用可接受的刻蝕製程（例如，通過濕刻蝕或乾刻蝕）來移除晶種層的暴露部分。晶種層的剩餘部分與導電材料形成金屬化圖案146及通孔。通孔形成在穿過介電層140而到達例如金屬化圖案138的一些部分的開口中。
在圖15中，在金屬化圖案146及介電層140上沉積介電層148。在一些實施例中，介電層148是由可使用微影罩幕進行圖案化的聚合物形成，所述聚合物可為例如聚苯并噁唑、聚醯亞胺、苯并環丁烯等感光性材料。在其他實施例中，介電層148由以下材料形成：氮化物，例如氮化矽；氧化物，例如氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜有硼的磷矽酸鹽玻璃；或類似材料。介電層148可通過旋轉塗布、層疊、化學氣相沉積、類似方法、或其組合來形成。
在圖16中，接著對介電層148進行圖案化。所述圖案化會形成開口以暴露出金屬化圖案146的部分。可通過例如以下可接受的製程來進行所述圖案化：當介電層是感光性材料時將介電層148暴露至光，或者使用例如各向異性刻蝕進行刻蝕。如果介電層148是感光性材料，則可在曝光之後對介電層148進行顯影。
在圖17中，在介電層148上形成具有通孔的金屬化圖案154。作為形成金屬化圖案154的實例，在介電層148之上以及在穿過介電層148的開口中形成晶種層（圖中未示出）。在一些實施例中，晶種層是金屬層，所述金屬層可為單個層或為包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。可使用例如物理氣相沉積等來形成晶種層。接著在晶種層上形成光阻並將所述光阻圖案化。可通過旋轉塗布或類似製程來形成光阻且可將光阻暴露至光以進行圖案化。光阻的圖案對應於金屬化圖案154。所述圖案化會形成穿過光阻的開口以暴露出晶種層。在光阻的開口中以及在晶種層的暴露的部分上形成導電材料。導電材料可通過鍍覆（例如，電鍍或無電鍍覆等）來形成。導電材料可包括金屬，如銅、鈦、鎢、鋁等。接著，移除光阻以及晶種層的上面未形成導電材料的部分。光阻可通過可接受的灰化製程或剝除製程來移除，例如使用氧電漿或類似製程等。一旦光阻被移除，便例如使用可接受的刻蝕製程（例如，通過濕刻蝕或乾刻蝕）來移除晶種層的暴露部分。晶種層的剩餘部分與導電材料形成金屬化圖案154及通孔。通孔形成在穿過介電層148而到達例如金屬化圖案146的一些部分的開口中。
在圖18中，在金屬化圖案154及介電層148上沉積介電層156。在一些實施例中，介電層156是由可使用微影罩幕進行圖案化的聚合物形成，所述聚合物可為例如聚苯并噁唑、聚醯亞胺、苯并環丁烯等感光性材料。在其他實施例中，介電層156由以下材料形成：氮化物，例如氮化矽；氧化物，例如氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜有硼的磷矽酸鹽玻璃；或類似材料。介電層156可通過旋轉塗布、層疊、化學氣相沉積、類似方法、或其組合來形成。
示出前側重佈線結構170作為實例。可在前側重佈線結構170中形成更多或更少的介電層及金屬化圖案。如果將形成更少的介電層及金屬化圖案，則可省略以上論述的步驟及製程。如果將形成更多介電層及金屬化圖案，則可重複以上論述的步驟及製程。所屬領域中的普通技術人員將易於理解哪些步驟及製程將被省略或重複進行。
在圖19中，接著對介電層156進行圖案化。所述圖案化會形成開口以暴露出金屬化圖案154的一些部分。可通過例如以下可接受的製程來進行所述圖案化：當介電層是感光性材料時將介電層156暴露至光，或者使用例如各向異性刻蝕進行刻蝕。如果介電層156是感光性材料，則可在曝光之後對介電層156進行顯影。
在圖20中，在前側重佈線結構170的外側上形成接墊162。接墊162用以耦合到導電連接件166（參見圖21），且可被稱為凸塊下金屬（under bump metallurgy）。在所示實施例中，穿過開口形成接墊162，所述開口穿過介電層156而到達金屬化圖案154。作為形成接墊162的實例，在介電層156之上形成晶種層（圖中未示出）。在一些實施例中，晶種層是金屬層，所述金屬層可為單一層或為包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。可使用例如物理氣相沉積等來形成晶種層。接著在晶種層上形成光阻並將所述光阻圖案化。可通過旋轉塗布或類似製程來形成光阻且可將光阻暴露至光以進行圖案化。光阻的圖案對應於接墊162。所述圖案化會形成穿過光阻的開口以暴露出晶種層。在光阻的開口中以及在晶種層的暴露的部分上形成導電材料。導電材料可通過鍍覆（例如，電鍍或無電鍍覆等）來形成。導電材料可包括金屬，如銅、鈦、鎢、鋁等。接著，移除光阻以及晶種層的上面未形成導電材料的部分。光阻可通過可接受的灰化製程或剝除製程來移除，例如使用氧電漿或類似製程等。一旦光阻被移除，便例如使用可接受的刻蝕製程（例如，通過濕刻蝕或乾刻蝕）來移除晶種層的暴露部分。晶種層的剩餘部分及導電材料形成接墊162。在其中接墊162以不同的方式形成的實施例中，可使用更多的光阻及圖案化步驟。
在圖21中，在接墊（可被稱為凸塊下金屬）162上形成導電連接件166。導電連接件166可為球柵陣列封裝（ball grid array，BGA）連接件、焊料球、金屬柱、受控塌陷晶片連接（controlled collapse chip connection，C4）凸塊、微凸塊、無電鍍鎳鈀浸金技術（electroless nickel-electroless palladium-immersion gold technique，ENEPIG）形成的凸塊等。導電連接件166可包含導電材料，例如，焊料、銅、鋁、金、鎳、銀、鈀、錫、類似材料、或其組合。在一些實施例中，通過使用例如蒸鍍（evaporation）、電鍍、印刷、焊料轉移（solder transfer）、植球（ball placement）或類似製程等常用方法初始地形成焊料層來形成導電連接件166。一旦已在結構上形成焊料層，便可執行回焊（reflow）以將所述材料塑形成期望凸塊形狀。在另一實施例中，導電連接件166為通過濺鍍、印刷、電鍍、無電鍍覆、化學氣相沉積或類似製程形成的金屬柱（例如銅柱）。所述金屬柱可不含有焊料且具有實質上垂直的側壁。在一些實施例中，在金屬柱連接件166的頂部上形成金屬蓋層（metal cap layer）（圖中未示出）。金屬蓋層可包含鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金、類似材料、或其組合，且可通過鍍覆製程來形成。
在圖22中，執行載板基底剝離（carrier substrate de-bonding）以使載板基底100從背側重佈線結構（例如，介電層104）分離（剝離）。根據一些實施例，所述剝離包括將例如雷射或紫外光等光投射在釋放層102上以使得釋放層102在光的熱量作用下分解，且可移除載板基底100。接著將所述結構翻轉並放置在膠帶190上。
在圖23中，在介電層104之上形成介電層200。在一些實施例中，介電層200包含耗散因數相對低的材料以實現具有適當效率的貼片式天線。舉例來說，介電層200的耗散因數可小於約0.01或者在一些實施例中甚至小於約0.001。另外，介電層200的k值可為約3至約4。在實施例中，介電層200的厚度與貼片式天線210的工作頻率相關。舉例來說，介電層200的厚度可與貼片式天線210工作頻率成反比。在實施例中，當貼片式天線210具有為至少60 GHz的工作頻率時，介電層200的厚度可處於約200 μm至約300 μm的範圍中。介電層200可使用任何合適的製程（例如，層疊）形成。在其他實施例中，也可使用其他沉積製程（例如，物理氣相沉積、化學氣相沉積、旋塗技術等）。
在圖24中，在介電層200之上形成貼片式天線的輻射元件204。在俯視圖中（例如，參見圖1C），輻射元件204可具有矩形形狀且與接地元件106A/饋電線106B交疊，但是在其他實施例中預期存在其他形狀。輻射元件204可包含任意合適的導電材料（例如，銅），但是在其他實施例中也可使用其他導電材料。輻射元件204可通過黏合劑202黏著在介電層200的表面上。在一些實施例中，黏合劑202可為環氧樹脂，所述環氧樹脂在黏著到介電層200上之前便被施加到輻射元件204。可接著將輻射元件204放置在介電層200上（例如，通過拾取及放置工具），並將黏合劑202活化（例如，通過加熱）以將輻射元件204黏合在介電層200上。在其他實施例中，不包含黏合劑202，且將輻射元件204直接黏著到介電層200。在其他實施例中，使用例如以下不同的方法在介電層200上形成輻射元件204：沉積晶種層；在晶種層之上形成圖案化罩幕以界定輻射元件204的圖案；在圖案化罩幕的開口中對輻射元件進行鍍覆；以及移除圖案化罩幕及晶種層的凹陷部分。也可對輻射元件204進行其他沉積製程。在一實施例中，可於輻射元件204上方加上一層可見或不可見的介電層（此處，所述可見或不可見介電層根據其厚度與材料染色與否決定），以防止輻射元件204的氧化。
輻射元件204電耦合到下伏的接地元件106A及饋電線106B以發射及接收無線訊號。由此，形成貼片式天線210（包括接地元件106A、饋電線106B、介電層200的一些部分、及輻射元件204）。將貼片式天線210中的每一者集成在與積體電路晶粒114及可選輻射天線108相同的半導體封裝中。介電特徵116將積體電路晶粒114中的每一者從相應的貼片式天線210分離並有助於將積體電路晶粒114中的每一者從相應的貼片式天線210隔離，以提高貼片式天線210的效率。
在形成輻射元件204之後，通過沿例如位於相鄰的區600與區602之間的切割道區212進行鋸切來執行單體化製程。所述鋸切將第一封裝區600從第二封裝區602單體化以形成半導體封裝250。
圖25示出在將半導體封裝250安裝到基底400之後的半導體封裝250。基底400可被稱為封裝基底400。使用導電連接件166將封裝250安裝到封裝基底400。
封裝基底400可由例如矽、鍺、金剛石等半導體材料製成。作為另外一種選擇，也可使用化合物材料，例如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、磷化鎵砷、磷化鎵銦、其組合等。另外，封裝基底400可為絕緣體上半導體（semiconductor-on-insulator，SOI）基底。一般來說，絕緣體上半導體基底包括由例如以下半導體材料形成的層：磊晶矽、鍺、矽鍺、絕緣體上半導體、絕緣體上矽鍺（silicon germanium-on-insulator，SGOI）、或其組合。在一個替代實施例中，封裝基底400是基於絕緣芯體，例如玻璃纖維加強型樹脂芯體。一種示例性芯體材料是玻璃纖維樹脂，例如FR4。芯體材料的替代形式包括雙馬來醯亞胺三氮雜苯（BT）樹脂，或作為另外一種選擇，包括其他印刷電路板材料或膜。可對封裝基底400使用例如味之素構成膜（Ajinomoto build-up film，ABF）等構成膜或其他層疊體。
封裝基底400可包括主動裝置及被動裝置（圖25中未示出）。所屬領域中的普通技術人員應認識到，可使用各種各樣的裝置（例如，電晶體、電容器、電阻器、其組合等）來實現半導體封裝500的設計的結構性及功能性要求。可利用任何適合的方法來形成所述裝置。
封裝基底400也可包括金屬化層及通孔（圖中未示出）以及位於所述金屬化層及通孔之上的結合接墊402。金屬化層可形成在主動裝置及被動裝置之上且被設計成連接各種裝置，以形成功能性電路系統。金屬化層可利用對導電材料層進行內連的通孔而由交替的介電質（例如，低介電常數介電材料）層與導電材料（例如，銅）層形成，且可通過任何適合的製程（例如，沉積、鑲嵌（damascene）、雙鑲嵌（dual damascene）等）來形成。在一些實施例中，封裝基底400實質上不含有主動裝置及被動裝置。
在一些實施例中，可對導電連接件166進行回焊以將封裝250貼合到結合接墊402。導電連接件166將基底400（包括位於基底400中的金屬化層）電耦合及/或實體耦合至第一封裝250。在一些實施例中，可在將被動裝置（例如，表面安裝裝置（surface mount devices，SMD），圖中未示出）安裝到基底400上之前，將被動裝置貼合到封裝250（例如，結合到接墊162）。在這些實施例中，可將被動裝置結合到封裝250的與導電連接件166所結合的表面相同的表面。
在導電連接件166被回焊之前，導電連接件166上可形成有環氧樹脂焊劑（圖中未示出），在將封裝250貼合到基底400之後所述環氧樹脂焊劑的至少一些環氧樹脂部分會餘留。這些餘留的環氧樹脂部分可充當底部填充劑，以減小由對導電連接件166進行回焊而引起的應力並保護因對導電連接件166進行回焊而產生的接縫。在一些實施例中，可在第一封裝250與基底400之間以及環繞導電連接件166來形成底部填充劑（圖中未示出）。所述底部填充劑可在對封裝250進行貼合之後通過毛細管流動製程（capillary flow process）形成，或可在對封裝250進行貼合之前通過合適的沉積方法形成。
已參照具體上下文，即在包括積體電路晶粒114以及一個或多個集成天線（例如，貼片式天線210）的封裝的上下文中，闡述了各種以上實施例。在積體電路晶粒114與貼片式天線的接地特徵及/或訊號線（被稱為饋電線）之間設置有介電特徵116以減少干擾。然而，可對其他類型的封裝應用各種實施例，所述其他類型的封裝可包括或可不包括集成天線。
舉例來說，圖26A及圖26B示出根據一些其他實施例的半導體封裝500的各種圖。圖26A示出封裝500的剖視圖，而圖26B示出封裝500的俯視圖。圖26A/圖26B所示封裝500可實質上相似於圖25所示封裝500，其中相同的參考編號表示相同的元件。
然而，不同於圖25所示的封裝500，圖26A/圖26B所示的封裝500不包括貼片式天線210。而是，圖26A/圖26B示出封裝500包括共面波導（coplanar waveguide，CPW）510。共面波導510包括訊號線502及接地線504。在一些實施例中，接地線504為訊號線502提供遮罩（例如，電磁遮罩）。舉例來說，在俯視圖中，訊號線502可設置在兩條接地線504之間並被兩條接地線504包夾（參見圖26B）。接地線504可通過導通孔110而電連接到積體電路晶粒114及重佈線結構170的導電特徵。在一些實施例中，訊號線502是高頻訊號線，所述高頻訊號線電連接到積體電路晶粒114以及重佈線結構170的導電特徵。在一些實施例中，訊號線502通過導通孔110（圖26A中未示出）而電連接到積體電路晶粒114以及重佈線結構170的導電特徵，導通孔110可設置在與圖26A不同的橫截面中。
在俯視圖中，共面波導510可與積體電路晶粒114交疊。另外，共面波導510可通過介電特徵116而從積體電路晶粒114實體分離。介電特徵116可有助於將共面波導510從由共面波導510與積體電路晶粒114之間的交疊造成的干擾隔離。在一些實施例中，介電特徵116的厚度是基於共面波導510的工作頻寬、介電特徵的k值、共面波導510的各種特徵的面積、共面波導510的期望效率、其組合等來加以選擇。
如圖26A所示，封裝500可還包括可選天線（例如，輻射天線108）。在其他實施例中，可不包含天線108。在一些實施例中，可將另一個封裝組件600A結合到封裝500的與基底400相對的一側。封裝元件600A可為積體電路晶粒或另一種封裝（例如，包括經包封的積體電路晶粒以及電路由（electrical routing））。舉例來說，封裝元件600A可為經封裝記憶體模組，例如，低功率雙倍數據速率1（low-power double data rate 1，LPDDR1）記憶體模組、低功率雙倍數據速率2記憶體模組、低功率雙倍數據速率3記憶體模組、低功率雙倍數據速率4記憶體模組等。預期也存在其他類型的封裝組件600A。
可通過連接件602A（例如，與上述連接件166相似）將封裝元件600A結合到封裝500，連接件602A延伸穿過封裝500的介電層512。介電層512可設置在封裝500的與基底400相對的外側處。封裝元件600A可通過導通孔110而電連接到共面波導510、積體電路晶粒114、及重佈線結構170的導電特徵。在一些實施例中，封裝元件600A也可電連接到可選天線108。
也可包括其他特徵及製程。舉例來說，可包括測試結構，以說明對三維（three dimensional，3D）封裝或三維積體電路（three dimensional integrated circuit，3DIC）裝置進行驗證測試。所述測試結構可例如包括在重佈線層中或在基底上形成的測試接墊（test pad），以允許對三維封裝或三維積體電路進行測試、對探針及/或探針卡（probe card）進行使用等。可對中間結構以及最終結構執行驗證測試。另外，可將本文中所公開的結構及方法與包括對已知良好晶粒進行中間驗證的測試方法結合使用，以提高良率並降低成本。
在各種實施例中，在俯視圖中，裝置（例如，貼片式天線或共面波導）的一些部分與至少一個半導體晶片交疊，且如果不能得到解決，則這種交疊可能會在裝置中造成干擾並造成裝置的效率降低。因此，各種實施例通過在半導體晶片與裝置（例如，裝置的訊號線及接地元件）之間設置介電特徵來提高裝置的效率並減少來自半導體晶片的干擾。對介電特徵的厚度加以選擇以實現裝置的期望效率。所述厚度可進一步對應於裝置與半導體晶片之間的距離。舉例來說，已觀察到，相對厚的介電特徵可在裝置與半導體晶片之間提供改善的隔離。在一些實施例中，介電特徵的厚度是基於裝置的工作頻寬、介電特徵的k值、裝置的各種特徵的面積、裝置的期望效率、其組合等來加以選擇。
根據實施例，一種封裝包括：積體電路晶粒，包封在包封體中；裝置，位於所述積體電路晶粒之上；以及介電特徵，設置在所述積體電路晶粒與所述裝置之間。所述裝置在俯視圖中與所述積體電路晶粒交疊。所述裝置包括訊號線及接地元件。所述介電特徵的厚度是根據所述裝置的工作頻寬。
在一些實施例中，所述介電特徵的所述厚度進一步根據所述介電特徵的k值、所述裝置的面積、所述裝置的效率、或其組合。
在一些實施例中，當所述裝置的所述工作頻寬為60 gHz且所述介電特徵的所述k值為至少3時，所述介電特徵的所述厚度為至少100 mm；當所述裝置的所述工作頻寬為60 gHz且所述介電特徵的所述k值小於3時，所述介電特徵的所述厚度為至少30 mm；當所述裝置的所述工作頻寬為77 gHz且所述介電特徵的所述k值為至少3時，所述介電特徵的所述厚度為至少50 mm；以及當所述裝置的所述工作頻寬為77 gHz且所述介電特徵的所述k值小於3時，所述介電特徵的所述厚度為至少15 mm。
在一些實施例中，所述裝置是貼片式天線，且其中所述貼片式天線包括輻射元件，所述輻射元件位於所述接地元件及所述訊號線之上且電耦合到所述接地元件及所述訊號線，其中在所述訊號線與所述輻射元件之間設置有第一介電層。
在一些實施例中，所述介電特徵將所述接地元件從所述積體電路晶粒在實體上分離，且其中所述介電特徵的所述厚度是作為所述接地元件與所述積體電路晶粒之間的距離來測量。
在一些實施例中，所述接地元件及所述訊號線設置在第二介電層中，且其中所述訊號線設置在延伸穿過所述接地元件的開口中。
在一些實施例中，所述接地元件設置在第二介電層中，且其中所述訊號線設置在位於所述第二介電層之上的第三介電層中。
在一些實施例中，所述裝置是共面波導，且其中在俯視圖中，所述訊號線設置在所述接地元件與附加接地元件之間。
根據實施例，一種方法包括：將積體電路晶粒包封在包封體中；以及在所述包封體中形成導通孔，並將所述積體電路晶粒電連接到貼片式天線。所述貼片式天線包括：接地元件；饋電線；以及輻射元件，電耦合到所述接地元件及所述饋電線。所述方法還包括形成將所述接地元件從所述積體電路晶粒在實體上分離的介電特徵。所述介電特徵的厚度是根據以下中的至少一者加以選擇：所述貼片式天線的工作頻寬，所述介電特徵的k值，所述貼片式天線的面積，以及所述貼片式天線的效率。
在一些實施例中，所述介電特徵包括第一介電層及第二介電層，其中所述第一介電層包含與所述第二介電層不同的材料。
在一些實施例中，所述介電特徵還包括第三介電層，所述第三介電層包含與所述第一介電層及所述第二介電層中的至少一者不同的材料。
在一些實施例中，所述介電特徵的側壁與所述積體電路晶粒的側壁具有共同的末端。
在一些實施例中，所述介電特徵具有與所述積體電路晶粒不同的寬度。
在一些實施例中，還包括形成輻射天線，所述輻射天線延伸穿過所述包封體且電連接到所述積體電路晶粒。
根據實施例，一種方法包括：在載板之上形成貼片式天線的接地元件及饋電線；以及使用介電特徵將積體電路晶粒貼合到所述貼片式天線的所述接地元件。所述介電特徵的厚度是根據所述貼片式天線的工作頻寬、所述介電特徵的k值、所述貼片式天線的面積、所述貼片式天線的效率、或其組合來加以選擇。所述方法還包括：形成電連接到所述接地元件及所述饋電線的導通孔；包封所述積體電路晶粒及所述導通孔；使用重佈線層將所述導通孔電連接到所述積體電路晶粒。所述重佈線層設置在所述積體電路晶粒的與所述接地元件相對的側上。所述方法還包括將所述貼片式天線的輻射元件電耦合到所述接地元件及所述饋電線。
在一些實施例中，還包括：移除所述載板；在移除所述載板後，在所述接地元件及所述饋電線之上形成介電層；以及在所述介電層之上形成所述輻射元件。
在一些實施例中，形成所述輻射元件包括將所述輻射元件黏著到所述介電層。
在一些實施例中，還包括：在形成所述導通孔的同時，形成鄰近所述導通孔的輻射天線；將所述輻射天線與所述導電孔及所述積體電路晶粒包封在一起；以及使用所述重佈線層將所述輻射天線電連接到所述積體電路晶粒。
在一些實施例中，形成所述接地元件及所述饋電線包括同時形成所述接地元件與所述饋電線。
在一些實施例中，形成所述接地元件及所述饋電線包括在不同的介電層中形成所述接地元件及所述饋電線。
以上概述了若干實施例的特徵，以使所屬領域中的技術人員可更好地理解本發明的各個方面。所屬領域中的技術人員應知，他們可容易地使用本發明作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員還應認識到，這些等效構造並不背離本發明的精神及範圍，而且他們可在不背離本發明的精神及範圍的條件下對其作出各種改變、代替、及變更。
1A-1A‧‧‧線
100‧‧‧載板基底
102‧‧‧釋放層
104‧‧‧介電層
106A‧‧‧接地元件
106B‧‧‧饋電線
106C‧‧‧接地元件
108‧‧‧天線
110‧‧‧導通孔
114‧‧‧積體電路晶粒
116‧‧‧介電特徵
116A‧‧‧介電層
116B、116C‧‧‧介電層
118‧‧‧半導體基底
120‧‧‧內連線結構
122‧‧‧接墊
124‧‧‧保護膜
126‧‧‧晶粒連接件
128‧‧‧介電材料
130‧‧‧包封體
132、140、148、156、200、512‧‧‧介電層
138、146、154‧‧‧金屬化圖案
162‧‧‧接墊
166‧‧‧連接件
170‧‧‧重佈線結構
190‧‧‧膠帶
202‧‧‧黏合劑
204‧‧‧輻射元件
206‧‧‧訊號
208‧‧‧無線訊號
210‧‧‧貼片式天線
212‧‧‧切割道區
250、280、500‧‧‧封裝
400‧‧‧基底
402‧‧‧結合接墊
502‧‧‧訊號線
504‧‧‧接地線
510‧‧‧共面波導
600、602‧‧‧區
600A‧‧‧封裝組件
602A‧‧‧連接件
d‧‧‧厚度
L‧‧‧長度
W‧‧‧寬度
結合附圖閱讀以下詳細說明，會最好地理解本發明的各個方面。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。 圖1A、圖1B、及圖1C示出根據一些實施例的半導體封裝的各種圖。 圖2A、圖2B、圖2C、圖2D及圖2E示出根據一些實施例的半導體封裝的一部分的剖視圖。 圖3A、圖3B、及圖3C示出根據一些替代實施例的半導體封裝的各種圖。 圖4、圖5、圖6、圖7、圖8、圖9、圖10、圖11、圖12、圖13、圖14、圖15、圖16、圖17、圖18、圖19、圖20、圖21、圖22、圖23、圖24、及圖25示出根據一些實施例的製造半導體封裝的各個中間階段的剖視圖。 圖26A及圖26B示出根據一些替代實施例的半導體封裝的各種圖。

Claims (1)

  1. 一種封裝，包括： 積體電路晶粒，包封在包封體中； 裝置，位於所述積體電路晶粒之上，其中所述裝置在俯視圖中與所述積體電路晶粒交疊，且其中所述裝置包括接地元件及訊號線；以及 介電特徵，設置在所述積體電路晶粒與所述裝置之間，其中所述介電特徵的厚度是根據所述裝置的工作頻寬。
TW106143032A 2017-02-24 2017-12-08 封裝、半導體封裝及封裝結構的形成方法 TWI708363B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201762463445P 2017-02-24 2017-02-24
US62/463,445 2017-02-24
US15/725,677 US10354964B2 (en) 2017-02-24 2017-10-05 Integrated devices in semiconductor packages and methods of forming same
US15/725,677 2017-10-05

Publications (2)

Publication Number Publication Date
TW201832343A true TW201832343A (zh) 2018-09-01
TWI708363B TWI708363B (zh) 2020-10-21

Family

ID=63246512

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106143032A TWI708363B (zh) 2017-02-24 2017-12-08 封裝、半導體封裝及封裝結構的形成方法

Country Status (3)

Country Link
US (4) US10354964B2 (zh)
CN (1) CN108511426B (zh)
TW (1) TWI708363B (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI707408B (zh) * 2019-04-10 2020-10-11 力成科技股份有限公司 天線整合式封裝結構及其製造方法
TWI724706B (zh) * 2018-12-26 2021-04-11 台灣積體電路製造股份有限公司 經封裝裝置及其形成方法
TWI743900B (zh) * 2020-07-23 2021-10-21 力晶積成電子製造股份有限公司 封裝結構及其製作方法

Families Citing this family (64)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107424974A (zh) * 2016-05-24 2017-12-01 胡迪群 具有埋入式噪声屏蔽墙的封装基板
US11625523B2 (en) 2016-12-14 2023-04-11 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips
TWI765944B (zh) 2016-12-14 2022-06-01 成真股份有限公司 標準大宗商品化現場可編程邏輯閘陣列（ｆｐｇａ）積體電路晶片組成之邏輯驅動器
JP6809600B2 (ja) * 2017-04-03 2021-01-06 株式会社村田製作所 高周波モジュール
TWI663701B (zh) * 2017-04-28 2019-06-21 矽品精密工業股份有限公司 電子封裝件及其製法
US11416050B2 (en) * 2017-05-08 2022-08-16 Octavo Systems Llc Component communications in system-in-package systems
US10460987B2 (en) * 2017-05-09 2019-10-29 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package device with integrated antenna and manufacturing method thereof
US10944180B2 (en) * 2017-07-10 2021-03-09 Viasat, Inc. Phased array antenna
US10447274B2 (en) 2017-07-11 2019-10-15 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips using non-volatile memory cells
US10957679B2 (en) 2017-08-08 2021-03-23 iCometrue Company Ltd. Logic drive based on standardized commodity programmable logic semiconductor IC chips
CN111095536A (zh) 2017-09-11 2020-05-01 莱新科技股份有限公司 电子电路装置和电子电路装置的制造方法
US10630296B2 (en) 2017-09-12 2020-04-21 iCometrue Company Ltd. Logic drive with brain-like elasticity and integrality based on standard commodity FPGA IC chips using non-volatile memory cells
US11031342B2 (en) * 2017-11-15 2021-06-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
US10573609B2 (en) * 2017-12-04 2020-02-25 Sj Semiconductor (Jiangyin) Corporation Fan-out antenna packaging structure and preparation thereof
US10468355B2 (en) * 2017-12-08 2019-11-05 Taiwan Semiconductor Manufacturing Company, Ltd. EMI Shielding structure in InFO package
US10424550B2 (en) * 2017-12-19 2019-09-24 National Chung Shan Institute Of Science And Technology Multi-band antenna package structure, manufacturing method thereof and communication device
US10608642B2 (en) 2018-02-01 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile radom access memory cells
US10623000B2 (en) 2018-02-14 2020-04-14 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
US20190348747A1 (en) * 2018-05-14 2019-11-14 Mediatek Inc. Innovative air gap for antenna fan out package
US11043730B2 (en) 2018-05-14 2021-06-22 Mediatek Inc. Fan-out package structure with integrated antenna
US11024954B2 (en) 2018-05-14 2021-06-01 Mediatek Inc. Semiconductor package with antenna and fabrication method thereof
US10608638B2 (en) 2018-05-24 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
US11081453B2 (en) 2018-07-03 2021-08-03 Mediatek Inc. Semiconductor package structure with antenna
WO2020014627A1 (en) 2018-07-13 2020-01-16 Viasat, Inc. Multi-beam antenna system with a baseband digital signal processor
KR102145218B1 (ko) * 2018-08-07 2020-08-18 삼성전자주식회사 팬-아웃 반도체 패키지
US11605877B2 (en) * 2018-09-07 2023-03-14 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US10892011B2 (en) 2018-09-11 2021-01-12 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
US11309334B2 (en) 2018-09-11 2022-04-19 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
KR102066904B1 (ko) * 2018-09-18 2020-01-16 삼성전자주식회사 안테나 모듈
US10937762B2 (en) 2018-10-04 2021-03-02 iCometrue Company Ltd. Logic drive based on multichip package using interconnection bridge
US10720399B2 (en) * 2018-10-25 2020-07-21 Taiwan Semiconductor Manufacturing Co., Ltd. Semicondcutor package and manufacturing method of semicondcutor package
US11616046B2 (en) 2018-11-02 2023-03-28 iCometrue Company Ltd. Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
TWI695472B (zh) * 2018-11-07 2020-06-01 欣興電子股份有限公司 晶片封裝結構及其製造方法
US11211334B2 (en) 2018-11-18 2021-12-28 iCometrue Company Ltd. Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
US10825782B2 (en) * 2018-12-27 2020-11-03 Micron Technology, Inc. Semiconductor packages and associated methods with solder mask opening(s) for in-package ground and conformal coating contact
DE102019124237A1 (de) * 2018-12-28 2020-07-02 Taiwan Semiconductor Manufacturing Co., Ltd. Heterogene antenne im fan-out-package
US12015191B2 (en) 2019-02-08 2024-06-18 Texas Instruments Incorporated Antenna-on-package integrated circuit device
US11258161B2 (en) 2019-02-08 2022-02-22 Texas Instmments Incorporated Antenna-on-package integrated circuit device
CN111816645A (zh) * 2019-04-10 2020-10-23 力成科技股份有限公司 天线整合式封装结构及其制造方法
JP7371882B2 (ja) 2019-04-12 2023-10-31 株式会社ライジングテクノロジーズ 電子回路装置および電子回路装置の製造方法
CN110491864B (zh) * 2019-04-17 2022-01-11 联发科技股份有限公司 半导体封装结构
US11196146B2 (en) * 2019-05-14 2021-12-07 Texas Instruments Incorporated Grounded BGA wave-guiding interface between an on-package signal launch and an external waveguide
CN112335036A (zh) 2019-05-16 2021-02-05 莱新科技股份有限公司 电子电路装置以及电子电路装置的制造方法
US10777518B1 (en) * 2019-05-16 2020-09-15 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of manufacturing the same
GB2584106B (en) * 2019-05-21 2024-03-27 Pragmatic Printing Ltd Flexible electronic structure
WO2020250795A1 (ja) * 2019-06-10 2020-12-17 株式会社ライジングテクノロジーズ 電子回路装置
CN112151459B (zh) * 2019-06-26 2023-03-24 庆鼎精密电子（淮安）有限公司 封装电路结构及其制作方法
US10985154B2 (en) 2019-07-02 2021-04-20 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cryptography circuits
US11227838B2 (en) 2019-07-02 2022-01-18 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cooperating or supporting circuits
US11887930B2 (en) 2019-08-05 2024-01-30 iCometrue Company Ltd. Vertical interconnect elevator based on through silicon vias
CN110429068A (zh) * 2019-08-09 2019-11-08 芯光科技新加坡有限公司 一种天线封装结构及其制备方法、通信设备
US11637056B2 (en) 2019-09-20 2023-04-25 iCometrue Company Ltd. 3D chip package based on through-silicon-via interconnection elevator
KR20210072938A (ko) * 2019-12-10 2021-06-18 삼성전기주식회사 안테나 기판 및 이를 포함하는 안테나 모듈
KR20210083830A (ko) * 2019-12-27 2021-07-07 삼성전자주식회사 반도체 패키지 및 그의 제조 방법
US11145610B2 (en) * 2019-12-30 2021-10-12 Unimicron Technology Corp. Chip package structure having at least one chip and at least one thermally conductive element and manufacturing method thereof
US11600526B2 (en) 2020-01-22 2023-03-07 iCometrue Company Ltd. Chip package based on through-silicon-via connector and silicon interconnection bridge
US11716117B2 (en) * 2020-02-14 2023-08-01 Texas Instruments Incorporated Circuit support structure with integrated isolation circuitry
CN111446176B (zh) * 2020-05-19 2022-03-15 华进半导体封装先导技术研发中心有限公司 天线集成封装方法及结构
KR20210157595A (ko) 2020-06-22 2021-12-29 삼성전자주식회사 반도체 패키지
KR20220004449A (ko) 2020-07-03 2022-01-11 삼성전자주식회사 반도체 패키지 및 반도체 패키지의 제조 방법
KR20220021755A (ko) 2020-08-14 2022-02-22 삼성전자주식회사 안테나를 포함하는 반도체 패키지
US11894357B2 (en) * 2020-09-10 2024-02-06 Sj Semiconductor (Jiangyin) Corporation System-level packaging structure and method for LED chip
CN113178697B (zh) * 2021-04-09 2023-11-10 维沃移动通信有限公司 电路板及电子设备
TWI843071B (zh) * 2021-06-04 2024-05-21 群創光電股份有限公司 電子裝置

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4345610B4 (de) * 1992-06-17 2013-01-03 Micron Technology Inc. Verfahren zur Herstellung einer Hochfrequenz-Identifikationseinrichtung (HFID)
WO2006039699A2 (en) * 2004-10-01 2006-04-13 De Rochemont L Pierre Ceramic antenna module and methods of manufacture thereof
US7518221B2 (en) 2006-01-26 2009-04-14 International Business Machines Corporation Apparatus and methods for packaging integrated circuit chips with antennas formed from package lead wires
US20090058731A1 (en) * 2007-08-30 2009-03-05 Gm Global Technology Operations, Inc. Dual Band Stacked Patch Antenna
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US9111949B2 (en) 2012-04-09 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of wafer level package for heterogeneous integration technology
US9711465B2 (en) * 2012-05-29 2017-07-18 Taiwan Semiconductor Manufacturing Co., Ltd. Antenna cavity structure for integrated patch antenna in integrated fan-out packaging
US9275950B2 (en) * 2012-05-29 2016-03-01 Taiwan Semiconductor Manufacturing Co., Ltd. Bead for 2.5D/3D chip packaging application
US9252491B2 (en) * 2012-11-30 2016-02-02 Taiwan Semiconductor Manufacturing Company, Ltd. Embedding low-k materials in antennas
US9166284B2 (en) * 2012-12-20 2015-10-20 Intel Corporation Package structures including discrete antennas assembled on a device
US9431714B2 (en) * 2013-01-03 2016-08-30 Taiwan Semiconductor Manufacturing Co., Ltd. Antenna structures
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US10319688B2 (en) * 2013-12-09 2019-06-11 Intel Corporation Antenna on ceramics for a packaged die
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9472859B2 (en) * 2014-05-20 2016-10-18 International Business Machines Corporation Integration of area efficient antennas for phased array or wafer scale array antenna applications
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
US9843106B2 (en) * 2014-10-09 2017-12-12 Taiwan Semicondcutor Manufacturing Company, Ltd. Integrated fan out antenna and method of forming the same
US9899248B2 (en) * 2014-12-03 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor packages having through package vias
CN106024727B (zh) * 2015-03-27 2018-10-26 台湾积体电路制造股份有限公司 具有ubm的封装件及其形成方法
US9484227B1 (en) * 2015-06-22 2016-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Dicing in wafer level package
US10770795B2 (en) * 2016-05-27 2020-09-08 Taiwan Semiconductor Manufacturing Co., Ltd. Antenna device and method for manufacturing antenna device
US10594019B2 (en) * 2016-12-03 2020-03-17 International Business Machines Corporation Wireless communications package with integrated antenna array

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI724706B (zh) * 2018-12-26 2021-04-11 台灣積體電路製造股份有限公司 經封裝裝置及其形成方法
US11183487B2 (en) 2018-12-26 2021-11-23 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
TWI707408B (zh) * 2019-04-10 2020-10-11 力成科技股份有限公司 天線整合式封裝結構及其製造方法
US11532575B2 (en) 2019-04-10 2022-12-20 Powertech Technology Inc. Integrated antenna package structure and manufacturing method thereof
TWI743900B (zh) * 2020-07-23 2021-10-21 力晶積成電子製造股份有限公司 封裝結構及其製作方法

Also Published As

Publication number Publication date
US20210225786A1 (en) 2021-07-22
US11749626B2 (en) 2023-09-05
US20190341363A1 (en) 2019-11-07
US20230369259A1 (en) 2023-11-16
CN108511426A (zh) 2018-09-07
US10354964B2 (en) 2019-07-16
TWI708363B (zh) 2020-10-21
US20180247905A1 (en) 2018-08-30
US10971460B2 (en) 2021-04-06
CN108511426B (zh) 2022-11-11

Similar Documents

Publication Publication Date Title
TWI708363B (zh) 封裝、半導體封裝及封裝結構的形成方法
US11996372B2 (en) Semiconductor device and method of manufacture
TWI710086B (zh) 半導體封裝及其形成方法
US11742254B2 (en) Sensor package and method
US10629537B2 (en) Conductive vias in semiconductor packages and methods of forming same
US20210143131A1 (en) Device and Method for UBM/RDL Routing
US11929318B2 (en) Package structure and method of forming the same
TW201916304A (zh) 半導體封裝
TW201923984A (zh) 半導體封裝及其形成方法
TW201804591A (zh) 具有整合式天線或電感器的積體扇出型封裝
KR102501418B1 (ko) 패키지 및 이의 형성 방법
TW202209600A (zh) 封裝結構及其製造方法
US20230352357A1 (en) Sensor packages
US12074148B2 (en) Heat dissipation in semiconductor packages and methods of forming same
US20240250046A1 (en) Semiconductor device and method of manufacture
TW202310093A (zh) 形成半導體裝置的方法
US20230387039A1 (en) Semicondcutor packages and methods of forming thereof
US20230266528A1 (en) Package and method of forming same