CN111816644A - 天线整合式封装结构及其制造方法 - Google Patents

天线整合式封装结构及其制造方法 Download PDF

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CN111816644A
CN111816644A CN201910664026.9A CN201910664026A CN111816644A CN 111816644 A CN111816644 A CN 111816644A CN 201910664026 A CN201910664026 A CN 201910664026A CN 111816644 A CN111816644 A CN 111816644A
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antenna
dielectric substrate
chip
conductive
package structure
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CN111816644B (zh
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林汉文
徐宏欣
张简上煜
林南君
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Powertech Technology Inc
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Powertech Technology Inc
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Abstract

本发明提供一种天线整合式封装结构及其制造方法，天线整合式封装结构包括芯片、线路层、密封体、耦合端、绝缘层、导电连接件、介电基板以及天线。线路层电性连接于芯片。密封体位于线路层上且包覆芯片。天线位于密封体上。绝缘层覆盖天线。绝缘层未暴露于外部。导电连接件贯穿密封体。天线通过导电连接件电性连接至线路层。介电基板位于密封体上且覆盖天线。耦合端配置于介电基板上。

Description

天线整合式封装结构及其制造方法
技术领域
本发明涉及一种封装结构及其制造方法，尤其涉及一种天线整合式封装结构及其制造方法。
背景技术
随着科技进步，电子产品的功能越来越丰富，例如是目前的行动通讯装置，为了在一台行动通讯装置中配置不同功能的电子元件，各个电子元件的尺寸都要很小，才有办法将所有电子元件都配置于符合轻、薄概念的行动通讯装置中。
现有的电子元件中的天线与芯片封装结构分开，且天线需通过电路板上的线路而与封装结构中的芯片电性连接，导致整个电子元件的体积难以缩小，因此，目前亟需一种解决上述问题的方法。
发明内容
本发明提供一种天线整合式封装结构及其制造方法，其体积可以较小且良率可以较高。
本发明的天线整合式封装结构包括芯片、线路层、密封体、耦合端、绝缘层、导电连接件、介电基板以及天线。线路层电性连接于芯片。密封体位于线路层上且包覆芯片。天线位于密封体上。绝缘层覆盖天线。绝缘层未暴露于外部。导电连接件贯穿密封体。天线通过导电连接件电性连接至线路层。介电基板位于密封体上且覆盖天线。耦合端配置于介电基板上。
本发明的天线整合式封装结构的制造方法包括以下步骤。提供介电基板。介电基板具有第一表面及相对于第一表面的第二表面。形成耦合端于介电基板的第一表面上。形成天线于介电基板的第二表面上。形成导电连接件于介电基板的第二表面上。导电连接件电性连接于天线。配置芯片于介电基板的第二表面上。形成密封体于介电基板的第二表面上。密封体包覆芯片。形成线路层于密封体上。线路层电性连接于芯片及导电连接件。
本发明的天线整合式封装结构的制造方法包括以下步骤。提供载板。形成导电连接件于载板上。配置芯片于载板上。形成密封体于载板上。密封体包覆芯片且暴露出导电连接件。形成天线于密封体上。天线电性连接至导电连接件。配置介电基板于天线上。形成耦合端于介电基板上。于配置介电基板之后，移除载板。在移除载板之后，形成线路层。线路层电性连接于芯片及导电连接件。
基于上述，本发明的天线整合式封装结构及其制造方法，其体积可以较小且良率可以较高。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
图1A至图1G是依照本发明的第一实施例的一种天线整合式封装结构的部分制造方法的部分剖视示意图。
图1H是依照本发明的第一实施例的一种天线整合式封装结构的部分剖视示意图。
图2A是依照本发明的第二实施例的一种天线整合式封装结构的部分制造方法的部分剖视示意图。
图2B是依照本发明的第二实施例的一种天线整合式封装结构的部分剖视示意图。
图3A至图3I是依照本发明的第三实施例的一种天线整合式封装结构的部分制造方法的部分剖视示意图。
图3J是依照本发明的第三实施例的一种天线整合式封装结构的部分剖视示意图。
图4A是依照本发明的第四实施例的一种天线整合式封装结构的部分制造方法的部分剖视示意图。
图4B是依照本发明的第四实施例的一种天线整合式封装结构的部分剖视示意图。
附图标记说明
100、200、300、400：天线整合式封装结构
110：介电基板
110a：第一表面
110b：第二表面
110T：厚度
120：耦合端
121：保护层
124：沟渠
130、330：天线
131、331：绝缘层
132：绝缘开口
133、333：侧壁
134、334：沟渠
140、340：导电连接件
140a、340a：上表面
341：导电芯层
342：绝缘壳层
150、350：芯片
150a、350a：主动面
150b、350b：背面
151：金属凸块
151a：上表面
152：粘着层
160、360：密封体
160a、360a：上表面
170：线路层
171：导电层
172：绝缘层
173：导电通孔
174：导电端子
280、480：屏蔽层
390：粘着层
30：载板
31：离型膜
具体实施方式
本文所使用的方向用语(例如，上、下、右、左、前、后、顶部、底部)仅作为参看所绘附图使用且不意欲暗示绝对定向。
除非另有明确说明，否则本文所述任何方法绝不意欲被解释为要求按特定顺序执行其步骤。
参照本实施例的附图以更全面地阐述本发明。然而，本发明亦可以各种不同的形式体现，而不应限于本文中所述的实施例。附图中的层或区域的厚度、尺寸或大小会为了清楚起见而放大。相同或相似的参考号码表示相同或相似的元件，以下段落将不再一一赘述。
图1A至图1G是依照本发明的第一实施例的一种天线整合式封装结构的部分制造方法的部分剖视示意图。图1H是依照本发明的第一实施例的一种天线整合式封装结构的部分剖视示意图。
请参照图1A，提供介电基板110。介电基板110具有第一表面110a及第二表面110b。第二表面110b相对于第一表面110a。
在本实施例中，对于介电基板110并无特别的限制，只要介电基板110可以适于承载形成于其上膜层或配置于其上的元件，并可以适于后续的制程中的温度或温差即可。另外，介电基板110可以具有较低的介电常数(dielectric constant；Dk)及具有较低的耗散因子(dissipation factor；Df)，以适于电磁信号穿透。
在一实施例中，介电基板110的材质可以是无机(inorganic)材料。无机材料的物理性质或化学性质稳定。
在一实施例中，介电基板110可以板状体，且介电基板110的厚度110T可以大于100微米(micrometer，μm)。换句话说，介电基板110可以不为通过蒸镀、溅镀、沉积或涂布的方式所形成的膜层(film layer)。
在一实施例中，介电基板110可以是均质材料(homogeneous material)，且前述的均质材料无法再通过机械方法(如：破碎、剪、切、锯、磨等方式)将元件拆离成不同的单一材料。换句话说，在介电基板110内可以不具有因不同材质或不同制程所形成的介面(interface)。
在一实施例中，介电基板110的材质可以包括硅酸盐材料。举例而言，介电基板110可以是玻璃基板、陶瓷基板或石英基板。
请继续参照图1A，形成耦合端120于介电基板110的第一表面110a上。耦合端120可以通过蒸镀、溅镀、沉积、网印或其他适宜的方式所形成，在本发明并不加以限制。另外，耦合端120的图案可以依设计上的需求而进行调整，在本发明并不加以限制。
在本实施例中，耦合端120可以与介电基板110的第一表面110a直接接触。一般而言，基于导电性的考量，耦合端120的材质可以是金属。
在本实施例中，可以于耦合端120上形成保护层(cover layer)121，但本发明不限于此。保护层121可以具有多个沟渠124。沟渠124可以暴露出介电基板110的第一表面110a。在后续的步骤中，可以延着保护层121的沟渠124进行单一化制程(singulation process/dicing process)。
请参照图1B，形成天线130于介电基板110的第二表面110b上。天线130可以通过蒸镀、溅镀、沉积、网印或其他适宜的方式所形成，在本发明并不加以限制。另外，天线130的图案可以依设计上的需求而进行调整，于本发明并不加以限制。
值得注意的是，在本发明中对于耦合端120与天线130的形成顺序并不加以限制。
在本实施例中，可以如图1A所示出地先形成耦合端120，然后再将如图1A所示出的结构上下翻转(flip upside down)，以在介电基板110的第二表面110b上形成天线130。
在一未示出的实施例中，可以先在介电基板110的第二表面110b上形成天线130，然后再于介电基板110的第一表面110a上形成耦合端120。
在本实施例中，天线130可以与介电基板110的第二表面110b直接接触。一般而言，基于导电性的考量，天线130的材质可以是金属。
在本实施例中，可以于天线130上形成绝缘层131。绝缘层131可以具有多个沟渠134及绝缘开口132。沟渠134可以暴露出介电基板110的第二表面110b。绝缘开口132可以暴露出部分的天线130。在后续的步骤中，可以延着绝缘层131的沟渠134进行单一化制程。
请参照图1B至图1C，在形成天线130之后，形成导电连接件140于介电基板110的第二表面110b上。导电连接件140电性连接于天线130。
在一实施例中，导电连接件140例如可以通过微影(photolithography)、沉积及电镀的方式所形成，但本发明不限于此。在另一实施例中，导电连接件140可以是预先形成(pre-form)的导电柱。
请参照图1B及图1D，在形成天线130之后，配置芯片150于介电基板110的第二表面110b上。芯片150可以是通讯芯片或具有通讯模块(communication module)的芯片。
在本实施例中，芯片150可以是以其背面150b面向介电基板110的方式配置于介电基板110的第二表面110b上。
值得注意的是，在本实施例中对于形成导电连接件140与配置芯片150的顺序并不加以限制。
在本实施例中，可以如图1C所示出地先形成导电连接件140，然后再如图1D所示出地配置芯片150。
在一未示出的实施例中，可以先配置芯片150，然后再形成导电连接件140。
在本实施例中，芯片150的主动面150a上具有多个金属凸块(metal bumps)151。在后续的步骤中，金属凸块151可能可以降低对芯片150的主动面150a造成的损伤。
在本实施例中，芯片150的背面150b上可以具有粘着层152。粘着层152例如是芯片粘着层(die attach film；DAF)。芯片150可以通过粘着层152固定于介电基板110的第二表面110b上。
请参照图1E，在形成导电连接件140及配置芯片150之后，形成密封体160于介电基板110的第二表面110b上。密封体160包覆芯片150，且密封体160暴露出导电连接件140。
举例而言，可以于介电基板110的第二表面110b上形成模封材料。并且，在将模封材料固化之后，可以进行平整化制程。于进行平整化制程之后，密封体160可以暴露出导电连接件140。换句话说，密封体160的上表面160a可以与导电连接件140的上表面140a共面(coplaner)。
在本实施例中，密封体160可以填入绝缘层131的沟渠134(示出于图1D)内。也就是说，密封体160可以直接接触介电基板110的第二表面110b以及绝缘层131的侧壁133。
在本实施例中，密封体160可以更暴露出位于芯片150的主动面150a上的金属凸块151。一般而言，平整化制程例如可以是研磨制程(grinding process)或抛光制程(polishing process)。因此，在前述的平整化制程中，金属凸块151可能可以降低对芯片150的主动面150a造成的损伤。
在本实施例中，密封体160的上表面140a、导电连接件140的上表面140a与金属凸块151的上表面151a共面(coplaner)。换句话说，密封体160的上表面140a及导电连接件140的上表面140a不与芯片150的主动面150a、芯片150上的连接垫(conatact pad)(未示出)和/或芯片150上的钝化层(passivation layer)(未示出)共面。
请参照图1E至图1F，在形成密封体160之后，形成线路层170于密封体160上。芯片150可以通过线路层170中对应的线路电性连接至导电连接件140。
线路层170可以通过一般的半导体制程来形成，故于此不加以赘述。举例而言，线路层170可以包括导电层171、绝缘层172及导电通孔173。对应的导电层171和/或对应的导电通孔173可以构成对应的线路。于附图中，线路层170中的线路只是在其中一个剖面上部分地示例性示出，线路层170中的线路可以依设计上的需求而进行调整。换句话说，在附图中未相连的部分线路在其他剖面上是可以通过其他对应的线路或连接件(如：对应的导电通孔或对应的导电层)而电性连接。
在一实施例中，线路层170可以被称为重布线路层(Redistribution Layer；RDL)，但本发明不限于此。
请参照图1F至图1G，在形成线路层170之后，形成多个导电端子174于线路层170上。导电端子174与线路层170中对应的线路电性连接。导电端子174例如可以通过植球制程(ball placement process)以和/或回焊制程(reflow process)所形成。举例而言，导电端子174可以为焊球。
请参照图1F至图1G，在形成线路层170之后，可以进行单一化制程。单一化制程例如是沿着保护层121的沟渠124(示出于图1D)及绝缘层131的沟渠134(示出于图1D)进行切割。单一化制程例如包括以旋转刀片或激光光束进行切割。
在本实施例中，由于可以延着保护层121的沟渠124(示出于图1D)及绝缘层131的沟渠134(示出于图1D)进行切割。因此，可以降低保护层121及绝缘层131从介电基板110的表面剥离(peeling)的可能。
值得注意的是，在本实施例中对于形成导电端子174与进行单一化制程的顺序并不加以限制。
值得注意的是，在进行单一化制程之后，相似的元件符号将用于单一化后的元件。举例而言，芯片150(如图1F所示)于单体化后可以为多个芯片150(如图1G所示)，线路层170(如图1F所示)于单体化后可以为多个线路层170(如图1G所示)，密封体160(如图1F所示)于单体化后可以为多个密封体160(如图1G所示)，天线130(如图1F所示)于单体化后可以为多个天线130(如图1G所示)，绝缘层131(如图1F所示)于单体化后可以为多个绝缘层131(如图1G所示)，多个导电连接件140(如图1F所示)于单体化后可以为多个导电连接件140(如图1G所示)，介电基板110(如图1F所示)于单体化后可以为多个介电基板110(如图1G所示)，耦合端120(如图1F所示)于单体化后可以为多个耦合端120(如图1G所示)，诸如此类。其他单体化后的元件将依循上述相同的元件符号规则，于此不加以赘述或特别示出。
经过上述制程后即可大致上完成一个或多个天线整合式封装结构100的制作。请参照图1H，天线整合式封装结构100包括芯片150、线路层170、密封体160、天线130、绝缘层131、导电连接件140、介电基板110以及耦合端120。线路层170电性连接于芯片150。密封体160位于线路层170上且包覆芯片150。天线130位于密封体160上。绝缘层131覆盖天线130。绝缘层131未暴露于外部。导电连接件140贯穿密封体160。天线130通过导电连接件140电性连接至线路层170。介电基板110位于密封体160上且覆盖天线130。耦合端120配置于介电基板110上。
在本实施例中，绝缘层131覆盖天线130，且密封体160覆盖绝缘层131。如此一来，可以使天线130受到较佳的保护，而可以降低天线130受潮或氧化的可能。
在本实施例中，介电基板110在天线整合式封装结构100的制造方法的过程中并未被移除。因此，在天线整合式封装结构100的制造方法中，介电基板110需要具有良好的支撑性、物理稳定性及化学性质稳定。举例而言，在常用的沉积制程或回焊制程中，可能会有对应的加热或降温步骤；在常用的微影制程或电镀制程中，可能会用到对应的酸液、碱液或溶剂。因此，介电基板110的材质可以选用物理性质或化学性质较为稳定的无机材料。
在本实施例中，介电基板110的玻璃转化温度(glass transition temperature；Tg)大于导电端子174的熔点。
在天线整合式封装结构100中，耦合端120与天线130之间具有介电基板110。因此，耦合端120与天线130在结构上彼此分隔。并且，耦合端120与天线130之间可以通过电感耦合(inductive coupling)的方式进行电磁信号的传递。一般而言，介电基板110的介电常数(dielectric constant)小于或等于4，且大于或等于3。并且，介电基板110于一般通讯领域中常用的频率(如：28GHz、39GHz、77GHz、79GHz，或其他介于20～80GHz的适宜范围)下的耗散因子(dissipation factor)可以小于或等于0.005，但本发明不限于此。
在一实施例中，介电基板110为玻璃基板、陶瓷基板或石英基板。在一实施例中，玻璃基板于一般通讯领域中常用的频率下的耗散因子可以小于或等于0.005。
图2A至图2B是依照本发明的第二实施例的一种天线整合式封装结构的部分制造方法的部分剖视示意图。图2B是依照本发明的第二实施例的一种天线整合式封装结构的部分剖视示意图。在本实施例中，天线整合式封装结构200的制造方法与第一实施例的天线整合式封装结构100的制造方法相似，其类似的构件以相同的标号表示，且具有类似的功能、材质或形成方式，并省略描述。具体而言，图2A示出接续图1B的步骤的天线整合式封装结构的制造方法的部分剖面示意图。
接续图1B，请参照图2A，在本实施例中，在形成天线130之后，在介电基板110的第二表面110b上形成导电连接件140及屏蔽层280。值得注意的是，在本发明中对于导电连接件140与屏蔽层280的形成顺序并不加以限制。
在一实施例中，屏蔽层280例如可以通过微影及沉积的方式所形成。在一实施例中，屏蔽层280例如可以通过沉积、微影及蚀刻的方式所形成。在另一实施例中，屏蔽层280可以是导电贴片(conductive patch)或导电膏(conductive paste)。本发明对于屏蔽层280的形成方式并不限于此。
在形成屏蔽层280之后，类似于图1D所示出的步骤，配置芯片150于屏蔽层280上。值得注意的是，于本实施例中对于形成导电连接件140与配置芯片150的顺序并不加以限制。
之后，类似于图1D至图1G所示出的步骤，即可大致上完成一个或多个天线整合式封装结构200的制作。
请参照图1H及图2B，在本实施例的天线整合式封装结构200与第一实施例的天线整合式封装结构100相似，其类似的构件以相同的标号表示，且具有类似的功能，并省略描述。请参照图2B，天线整合式封装结构200包括芯片150、线路层170、密封体160、天线130、绝缘层131、导电连接件140、介电基板110、耦合端120以及屏蔽层280。屏蔽层280位于介电基板110与芯片150之间。
在本实施例中，屏蔽层280可以位于天线130与芯片150之间。屏蔽层280可以降低天线130与芯片150之间的信号干扰。
在一实施例中，屏蔽层280可以接地，但本发明不限于此。
图3A至图3I是依照本发明的第三实施例的一种天线整合式封装结构的部分制造方法的部分剖视示意图。图3J是依照本发明的第三实施例的一种天线整合式封装结构的部分剖视示意图。
请参照图3A，提供载板30。在本实施例中，对于载板30并无特别的限制，只要载板30可以适于承载形成于其上膜层或配置于其上的元件，并可以适于后续的制程中的温度或温差即可。
在本实施例中，载板30上可以具有离型膜(release film)31，以于后续的制程中可以使载板30较容易与位于其上的元件或膜层分离。
请继续参照图3A，形成导电连接件340于载板30上。
在本实施例中，导电连接件340可以包括预先形成的导电柱，但本发明不限于此。
在本实施例中，导电连接件340可以包括导电芯层341以及绝缘壳层342。绝缘壳层342围绕导电芯层341。举例而言，导电连接件340例如是印刷电路板，绝缘壳层342例如是印刷电路板的芯层(core layer)，且导电芯层341例如是印刷电路板的镀覆孔(plated-through hole；PTH)。
请参照图3B，配置芯片350于载板30上。芯片350可以是通讯芯片或具有通讯模块的芯片。
在本实施例中，芯片350可以是以其主动面350a向载板30的方式配置于载板30上。
值得注意的是，在本实施例中对于形成导电连接件340与配置芯片350的顺序并不加以限制。
在本实施例中，可以类似于图1A所示出地先形成导电连接件340，然后再类似于图1B所示出地配置芯片350。
在一未示出的实施例中，可以先配置芯片350，然后再形成导电连接件340。
请参照图3C，在形成导电连接件340及配置芯片350之后，形成密封体360于载板30上。密封体360覆盖芯片350的背面350b，且密封体360暴露出导电连接件340。
举例而言，可以于载板30上形成模封材料。并且，在将模封材料固化之后，进行平整化制程，以使密封体360暴露出导电连接件340。换句话说，密封体360的上表面360a可以与导电连接件340的上表面340a共面(coplaner)。
请参照图3C至图3D，在形成密封体360之后，形成天线330于密封体360上。天线330电性连接至导电连接件340。天线330可以通过蒸镀、溅镀、沉积、网印或其他适宜的方式所形成，在本发明并不加以限制。另外，天线330的图案可以依设计上的需求而进行调整，于本发明并不加以限制。
请参照图3D，在形成天线330之后，可以于天线330上形成绝缘层331。绝缘层331可以具有多个沟渠334。沟渠334可以暴露出密封体360。在后续的步骤中，可以延着绝缘层331的沟渠334进行单一化制程。
请参照图3D至图3E，在形成绝缘层331之后，配置介电基板110于天线330上。
在本实施例中，可以在密封体360上形成粘着层390。粘着层390可以填入绝缘层331的沟渠334(示出于图3D)中。也就是说，粘着层390可以覆盖绝缘层331的侧壁333、密封体360的上表面360a以及介电基板110的第二表面110b。介电基板110可以通过粘着层390粘着于绝缘层331与密封体360。
在本实施例中，天线330可以不与介电基板110的第二表面110b直接接触。
请参照图3E至图3F，形成耦合端120于介电基板110的第一表面110a上。值得注意的是，在本实施例中对于形成耦合端120与将介电基板110配置于天线330上的顺序并不加以限制。
在本实施例中，可以如图3E所示出地先将介电基板110配置于天线330上，然后再如图1F所示出地将耦合端120形成于介电基板110的第一表面110a上。
在一未示出的实施例中，可以先将耦合端120形成于介电基板110的第一表面110a上，然后再将介电基板110配置于天线330上。
请参照图3F至图3G，在配置介电基板110之后，移除载板30(示出于图3F)及离型膜31(若有，示出于图3F)。在载板30及离型膜31(若有)被移除后，可以暴露出导电连接件340。
在本实施例中，在移除载板30及离型膜31(若有)之后，可以还暴露出芯片350的主动面350a
值得注意的是，在本实施例中对于形成耦合端120与移除载板30的顺序并不加以限制。
在本实施例中，可以如图3F所示出地先将耦合端120形成于介电基板110的第一表面110a上，然后再如图3G所示出地移除载板30。
在一未示出的实施例中，可以先移除载板30，然后再将耦合端120形成于介电基板110的第一表面110a上。
请参照图3G至图3H，在移除载板30(示出于图3F)之后，形成线路层170。芯片350可以通过线路层170中对应的线路电性连接至导电连接件340。
请参照图3H至图3I，在形成线路层170之后，形成多个导电端子174于线路层170上。导电端子174与线路层170中对应的线路电性连接。
请参照图3H至图3I，在形成线路层170之后，可以进行单一化制程。单一化制程例如是沿着保护层121的沟渠124(示出于图3H)及绝缘层331的沟渠334(示出于图3D)进行切割。单一化制程例如包括以旋转刀片或激光光束进行切割。
值得注意的是，在本实施例中对于形成导电端子174与进行单一化制程的顺序并不加以限制。
值得注意的是，在进行单一化制程之后，相似的元件符号将用于单一化后的元件。举例而言，芯片350(如图3I所示)于单体化后可以为多个芯片350(如图3J所示)，线路层170(如图3I所示)于单体化后可以为多个线路层170(如图3J所示)，密封体360(如图3I所示)于单体化后可以为多个密封体360(如图3J所示)，天线330(如图3I所示)于单体化后可以为多个天线330(如图3J所示)，绝缘层331(如图3I所示)于单体化后可以为多个绝缘层331(如图3J所示)，多个导电连接件340(如图3I所示)于单体化后可以为多个导电连接件340(如图3J所示)，介电基板110(如图3I所示)于单体化后可以为多个介电基板110(如图3J所示)，耦合端120(如图3I所示)于单体化后可以为多个耦合端120(如图3J所示)，诸如此类。其他单体化后的元件将依循上述相同的元件符号规则，于此不加以赘述或特别示出。
经过上述制程后即可大致上完成一个或多个天线整合式封装结构300的制作。请参照图3J，天线整合式封装结构300包括芯片350、线路层170、密封体360、天线330、绝缘层331、导电连接件340、介电基板110以及耦合端120。线路层170电性连接于芯片350。密封体360位于线路层170上且包覆芯片350。天线330位于密封体360上。绝缘层331覆盖天线330。绝缘层331未暴露于外部。导电连接件340贯穿密封体360。天线330通过导电连接件340电性连接至线路层170。介电基板110位于密封体360上且覆盖天线330。耦合端120配置于介电基板110上。
在本实施例中，天线整合式封装结构300可以还包括粘着层390。绝缘层331覆盖天线330，且黏着层390覆盖绝缘层331的侧壁333。如此一来，可以使天线330受到较佳的保护，而可以降低天线330受潮或氧化的可能。
图4A是依照本发明的第四实施例的一种天线整合式封装结构的部分制造方法的部分剖视示意图。图4B是依照本发明的第四实施例的一种天线整合式封装结构的部分剖视示意图。在本实施例中，天线整合式封装结构400的制造方法与第三实施例的天线整合式封装结构300的制造方法相似，其类似的构件以相同的标号表示，且具有类似的功能、材质或形成方式，并省略描述。具体而言，图4A示出接续图3C的步骤的天线整合式封装结构的制造方法的部分剖面示意图。
请参照图3C及图4A，在形成密封体360之后，形成天线330与屏蔽层480于密封体360上。天线330与屏蔽层480的材质或形成方式可以相同或相似。
在形成天线330与屏蔽层480之后，可以于天线330与屏蔽层480上形成绝缘层331。
之后，类似于图3D至图3I所示出的步骤，即可大致上完成一个或多个天线整合式封装结构400的制作。
请参照图3J及图4B，在本实施例的天线整合式封装结构400与第三实施例的天线整合式封装结构300相似，其类似的构件以相同的标号表示，且具有类似的功能，并省略描述。请参照图4B，天线整合式封装结构400包括芯片350、线路层170、密封体360、天线330、绝缘层331、导电连接件340、介电基板110、耦合端120以及屏蔽层480。屏蔽层480位于介电基板110与芯片350之间。屏蔽层480可以降低耦合端120与芯片350之间的信号干扰。
在一实施例中，屏蔽层480可以接地，但本发明不限于此。
综上所述，本发明的天线整合式封装结构及其制造方法，其体积可以较小且良率可以较高。
虽然本发明已以实施例揭示如上，然其并非用以限定本发明，任何所属技术领域中技术人员，在不脱离本发明的精神和范围内，当可作些许的更改与润饰，故本发明的保护范围当视权利要求所界定的为准。

Claims (10)

1.一种天线整合式封装结构，包括：
芯片；
线路层，电性连接于所述芯片；
密封体，位于所述线路层上且包覆所述芯片；
天线，位于所述密封体上；
绝缘层，覆盖所述天线，且所述绝缘层未暴露于外部；
导电连接件，贯穿所述密封体，且所述天线通过所述导电连接件电性连接至所述线路层；
介电基板，位于所述密封体上且覆盖所述天线；以及
耦合端，配置于所述介电基板上。
2.根据权利要求1所述的天线整合式封装结构，还包括：
多个导电端子，电性连接于所述线路层，所述线路层位于所述多个导电端子与所述芯片之间，且所述介电基板的玻璃转化温度大于所述多个导电端子的熔点。
3.根据权利要求1所述的天线整合式封装结构，其中：
所述介电基板的介电常数小于或等于4，且大于或等于3；且
所述介电基板于20～80GHz的电磁波频率下的耗散因子小于或等于0.005。
4.根据权利要求1所述的天线整合式封装结构，其中所述介电基板为玻璃基板、陶瓷基板或石英基板。
5.根据权利要求1所述的天线整合式封装结构，其中所述天线与所述耦合端分别与所述介电基板的相对两个表面直接接触。
6.根据权利要求1所述的天线整合式封装结构，其中所述密封体直接接触所述介电基板。
7.根据权利要求1所述的天线整合式封装结构，其中所述导电连接件包括：
导电芯层，电性连接所述天线及所述线路层；以及
绝缘壳层，围绕所述导电芯层。
8.根据权利要求1所述的天线整合式封装结构，还包括：
屏蔽层，位于所述介电基板与所述芯片之间。
9.一种天线整合式封装结构的制造方法，包括：
提供介电基板，具有第一表面及相对于所述第一表面的第二表面；
形成耦合端于所述介电基板的所述第一表面上；
形成天线于所述介电基板的所述第二表面上；
形成导电连接件于所述介电基板的所述第二表面上，且所述导电连接件电性连接于所述天线；
配置芯片于所述介电基板的所述第二表面上；
形成密封体于所述介电基板的所述第二表面上，且所述密封体包覆所述芯片；以及
形成线路层于所述密封体上，且所述线路层电性连接于所述芯片及所述导电连接件。
10.一种天线整合式封装结构的制造方法，包括：
提供载板；
形成导电连接件于所述载板上；
配置芯片于所述载板上；
形成密封体于所述载板上，所述密封体包覆所述芯片且暴露出所述导电连接件；形成天线于所述密封体上，且电性连接至所述导电连接件；
配置介电基板于所述天线上；
形成耦合端于所述介电基板上；
在配置介电基板之后，移除所述载板；以及
在移除所述载板之后，形成线路层，以电性连接于所述芯片及所述导电连接件。
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US20200328161A1 (en) 2020-10-15
TWI772736B (zh) 2022-08-01

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