TW202038420A - 晶片封裝結構及其製造方法 - Google Patents

晶片封裝結構及其製造方法 Download PDF

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TW202038420A
TW202038420A TW109100306A TW109100306A TW202038420A TW 202038420 A TW202038420 A TW 202038420A TW 109100306 A TW109100306 A TW 109100306A TW 109100306 A TW109100306 A TW 109100306A TW 202038420 A TW202038420 A TW 202038420A
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chip
conductive
layer
circuit layer
active surface
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TW109100306A
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TWI747127B (zh
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林南君
徐宏欣
張簡上煜
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力成科技股份有限公司
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Abstract

一種晶片封裝結構，其包括第一晶片、密封體、第一重佈線路層、第二重佈線路層、第二晶片以及第三晶片。第一晶片具有主動面、相對於主動面的背面、多個導電穿孔以及位於背面上的多個導電連接件。密封體覆蓋主動面、背面及多個導電連接件。密封體具有第一密封面以及相對於第一密封面的第二密封面。第一重佈線路層位於第一密封面上。第二重佈線路層位於第二密封面上。第二晶片配置於第二重佈線路層上。第三晶片配置於第二重佈線路層上。一種晶片封裝結構的製造方法亦被提出。

Description

晶片封裝結構及其製造方法
本發明是有關於一種晶片封裝結構及其製造方法，且特別是有關於一種具有多個晶片的晶片封裝結構及其製造方法。
為了使得電子產品能達到輕薄短小的設計，半導體封裝技術亦跟著日益進展，以發展出符合小體積、重量輕、高密度以及在市場上具有高競爭力等要求的產品。
而在具有多個晶片的晶片封裝結構中，如何提升晶片與晶片之間訊號傳輸品質或效率，實已成目前亟欲解決的課題。
本發明提供一種晶片封裝結構及晶片封裝結構的製造方法，其具有較佳的訊號傳輸品質或效率。
本發明的晶片封裝結構包括第一晶片、密封體、第一重佈線路層、第二重佈線路層、第二晶片以及第三晶片。第一晶片具有第一主動面、相對於第一主動面的第一背面、多個導電穿孔以及位於第一背面上的多個第一導電連接件。密封體覆蓋第一晶片的第一主動面、第一背面及多個第一導電連接件。密封體具有第一密封面以及相對於第一密封面的第二密封面。第一重佈線路層位於密封體的第一密封面上。第二重佈線路層位於密封體的第二密封面上。第二晶片配置於第二重佈線路層上。第三晶片配置於第二重佈線路層上。
本發明的晶片封裝結構的製造方法包括以下步驟：形成第一重佈線路層於載板上；配置第一晶片於第一重佈線路層上，其中第一晶片具有第一主動面、相對於主動面的第一背面、多個導電穿孔以及位於第一背面上的多個第一導電連接件，且多個第一導電連接件電性連接於第一重佈線路層；形成密封體於第一重佈線路層上，且覆蓋第一晶片的第一主動面、第一背面及多個第一導電連接件；形成第二重佈線路層於密封體上；配置第二晶片於第二重佈線路層上；以及配置第三晶片於第二重佈線路層上。
基於上述，本發明的晶片封裝結構及晶片封裝結構的製造方法可以具有較佳的訊號傳輸品質或效率。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
除非另有明確說明，本文所使用之方向用語（例如，上、下、左、右、前、後、頂部、底部）僅作為參看所繪圖式使用且不意欲暗示絕對定向。
除非另有明確說明，否則本文所述任何方法絕不意欲被解釋為要求按特定順序執行其步驟。
參照本實施例之圖式以更全面地闡述本發明。然而，本發明亦可以各種不同的形式體現，而不應限於本文中所述之實施例。圖式中的層或區域的厚度、尺寸或大小會為了清楚起見而放大。相同或相似之參考號碼表示相同或相似之元件，以下段落將不再一一贅述。
圖1A至圖1G是依照本發明的第一實施例的一種晶片封裝結構的部分製造方法的部分剖視示意圖。圖1H是依照本發明的第一實施例的一種晶片封裝結構的部分上視示意圖。圖1I是依照本發明的第一實施例的一種晶片封裝結構的部分製造方法的部分剖視示意圖。圖1H可以是圖1G的上視示意圖。圖1I可以是圖1C中區域R的放大示意圖。
請參照圖1A，形成第一重佈線路層160於載板191上。本發明對於載板191並無特別的限制，只要載板191可以適於承載形成於其上膜層或配置於其上的元件即可。
在一未繪示的實施例中，載板191上可以具有光熱轉換（light to heat conversion；LTHC）黏著層或其他類似的離型層。
在本實施例中，第一重佈線路層160可以包括絕緣層161以及導電層162。最頂的絕緣層161a（即，最遠離載板191的絕緣層161）可以具有多個開口161b，且開口161b可以暴露出最頂的導電層162a（即，最遠離載板191的導電層162）。第一重佈線路層160可以藉由一般常用的半導體製程（如：沉積製程、微影製程及/或蝕刻製程）形成，故於此不加以贅述。
請參照圖1B，在本實施例中，可以配置多個第三導電連接件150於第一重佈線路層160上。第三導電連接件150可以嵌入最頂的絕緣層161a的開口161b（標示於圖1A）內，以電性連接於最頂的導電層162a中對應的部分。
在一實施例中，第三導電連接件150可以包括預先成型（pre-formed）的導電件。舉例而言，第三導電連接件150可以包括預先成型的導電柱（pre-formed conductive pillar），但本發明不限於此。
在一實施例中，第三導電連接件150可以藉由一般常用的半導體製程（如：微影製程、濺鍍製程、電鍍製程及/或蝕刻製程）形成，但本發明不限於此。舉例而言，第三導電連接件150可以包括鍍覆核心層（plating core layer）及環繞鍍覆核心層的種子層（seed layer），但本發明不限於此。
請參照圖1C，配置第一晶片110於第一重佈線路層160上。
第一晶片110包括基材113。基材113的一側具有元件區（未繪示），而元件區所位於的表面可以被稱為主動面。也就是說，第一晶片110具有第一主動面111及第一背面112，且第一背面112相對於第一主動面111。
在本實施例中，第一晶片110可以包括多個連接墊116、線路結構114、多個第一導電連接件117、多個第二導電連接件118以及多個導電穿孔115。連接墊116位於第一主動面111。多個第一導電連接件117位於第一背面112上。多個第二導電連接件118位於第一主動面111上。多個導電穿孔115貫穿基材113。並且，在將第一晶片110配置於第一重佈線路層160上之後，可以使多個第一導電連接件117電性連接於第一重佈線路層160。
值得注意的是，於圖1C及後續的圖式中，僅示例性地繪示了部分的剖面。在一般晶片設計中，元件區內的元件（如：第一晶片110的元件區內的元件）可以藉由對應的後段金屬內連線（Back End of Line Interconnect）電性連接於對應的連接墊（如：第一晶片110的部分連接墊116）。
在本實施例中，第一導電連接件117的其中之一與第二導電連接件118的其中之一可以藉由對應的連接墊116、對應的導電穿孔115以及線路導電層114b中對應的部分而電性連接。在一實施例中，導電穿孔115可以藉由對應的後段金屬內連線電性連接於對應的連接墊116。
在本實施例中，連接墊116例如為鋁墊或銅墊，但本發明不限於此。在一實施例中，連接墊116可以被保護層（passivation layer）119部分覆蓋。
在本實施例中，線路結構114可以包括線路絕緣層114a、114c以及線路導電層114b。線路絕緣層114a可以位於線路導電層114b與基材113之間。線路絕緣層114c可以覆蓋線路導電層114b。
在本實施例中，導電穿孔115可以包括穿孔絕緣層115a及穿孔導電層115b。穿孔絕緣層115a可以位於穿孔導電層115b與基材113之間。
在一實施例中，穿孔導電層115b可以為多層的結構。舉例而言，穿孔導電層115b可以包括阻障層（barrier layer）、晶種層（seed layer）以及鍍覆層（plating layer），但本發明不限於此。
在本實施例中，最接近基材113的線路絕緣層114a與穿孔絕緣層115a可以是相同的膜層，且最接近基材113的線路導電層114b與穿孔導電層115b可以是相同的膜層。
在一實施例中，基材113可以為矽基材，且導電穿孔115可以被稱為矽穿孔（through silicon via；TSV），但本發明不限於此。
請參照圖1D，在本實施例中，可以形成密封材料149於第一重佈線路層160上。密封材料149覆蓋第一晶片110的第一主動面111、第一背面112、多個第一導電連接件117、多個第二導電連接件118以及多個第三導電連接件150。
請參照圖1E，在本實施例中，可以移除部分的密封材料149（標示於圖1D），以形成密封體140。密封體140可以覆蓋第一晶片110的第一主動面111、第一背面112、多個第一導電連接件117的側壁117s、多個第二導電連接件118的側壁118s以及多個第三導電連接件150的側壁150s。密封體140可以暴露出部分的第二導電連接件118以及部分的第三導電連接件150。
在一實施例中，可以進行研磨（grinding）、拋光（polishing）或其他適宜的平整化步驟，以使密封體140的第二表面142、第二導電連接件118的頂面118a以及第三導電連接件150的頂面150a構成一共面的平整面。
在一實施例中，由於第一晶片110的第一主動面111上具有第二導電連接件118，因此，在進行前述平整化步驟時可以降低對元件區的元件或連接墊116（標示於圖1I）造成損傷的可能。
請參照圖1F，形成第二重佈線路層170於密封體140上。
在本實施例中，第二重佈線路層170可以包括絕緣層171以及導電層172。第二重佈線路層170可以藉由一般常用的半導體製程（如：沉積製程及/或微影製程）形成，故於此不加以贅述。
請繼續參照圖1F，配置第二晶片120於第二重佈線路層170上，且使第二晶片120電性連接於導電層172中對應的部分及對應的第三導電連接件150。
在本實施例中，第二晶片120與第二重佈線路層170之間可以具有多個第一導電端子181以及多個第二導電端子182。第二晶片120可以藉由對應的第一導電端子181電性連接於第一晶片110。第二晶片120可以藉由對應的第二導電端子182電性連接於對應的第三導電連接件150。
請繼續參照圖1F，配置第三晶片130於第二重佈線路層170上，且使第三晶片130電性連接於導電層172中對應的部分及對應的第三導電連接件150。
在本實施例中，第三晶片130與第二重佈線路層170之間可以具有多個第三導電端子183以及多個第四導電端子184。第三晶片130可以藉由對應的第三導電端子183電性連接於第一晶片110。第三晶片130可以藉由對應的第四導電端子184電性連接於對應的第三導電連接件150。
在一實施例中，第一導電端子181、第二導電端子182、第三導電端子183及/或第四導電端子184可以包括銲球，但本發明不限於此。
在一實施例中，第一導電端子181、第二導電端子182、第三導電端子183及/或第四導電端子184可以藉由一般常用的植球製程形成，故於此不加以贅述。
值得注意的是，本發明並未限制將第二晶片120配置於第二重佈線路層170上及將第三晶片130配置於第二重佈線路層170上的順序。
在一未繪示的實施例中，可以於第二晶片120與第二重佈線路層170之間及/或於第三晶片130與第二重佈線路層170之間形成底膠（underfill）。
請參照圖1G，於形成第二重佈線路層170之後，可以移除載板191（標示於圖1F），以暴露出第一重佈線路層160。
值得注意的是，本發明並未限制將第二晶片120配置於第二重佈線路層170上、將第三晶片130配置於第二重佈線路層170上的順序及移除載板191的順序。在本實施例中，可以先將第二晶片120及第三晶片130配置於第二重佈線路層170上，然後再移除載板191。在一未繪示的實施例中，可以先移除載板191，然後再將第二晶片120或第三晶片130配置於第二重佈線路層170上。
請繼續參照圖1G，於暴露出第一重佈線路層160之後，可以於第一重佈線路層160上形成第五導電端子185。
在一實施例中，第五導電端子185可以包括銲球，但本發明不限於此。
在一實施例中，第五導電端子185可以藉由一般常用的植球製程形成，故於此不加以贅述。
經過上述製程後即可大致上完成本實施例之晶片封裝結構100的製作。請參照圖1G及圖1H，晶片封裝結構100包括第一晶片110、密封體140、第一重佈線路層160、第二重佈線路層170、第二晶片120以及第三晶片130。第一晶片110具有第一主動面111、第一背面112、多個導電穿孔115以及多個第一導電連接件117。第一背面112相對於第一主動面111。第一導電連接件117位於第一背面112上。密封體140覆蓋第一晶片110的第一主動面111、第一背面112及第一導電連接件117。密封體140具有第一密封面141以及第二密封面142。第二密封面142相對於第一密封面141。第一重佈線路層160位於密封體140的第一密封面141上。第二重佈線路層170位於密封體140的第二密封面142上。第二晶片120配置於第二重佈線路層170上。第三晶片130配置於第二重佈線路層170上。
在本實施例中，第一晶片110可以更具有位於第一主動面111上的多個第二導電連接件118。密封體140更覆蓋多個第二導電連接件118。
在本實施例中，第一晶片110可以更具有位於第一背面112上的線路結構114，且第一導電連接件117藉由線路結構114對應的部分電性連接於對應的導電穿孔115。
在本實施例中，多個導電穿孔115可以包括穿孔絕緣層115a（標示於圖1I）及穿孔導電層115b（標示於圖1I），線路結構114可以包括線路絕緣層114a（標示於圖1I）及線路導電層114b（標示於圖1I），穿孔絕緣層115a及線路絕緣層114a可以為相同的膜層，且穿孔導電層115b及線路導電層114b可以為相同的膜層。
在本實施例中，晶片封裝結構100可以更包括多個第三導電連接件150。第三導電連接件150貫穿密封體140。第三導電連接件150電性連接於部分的第一重佈線路層160及部分的第二重佈線路層170。第三導電連接件150的徑寬（如：最小徑寬150w）大於導電穿孔115的徑寬（如：最小徑寬115w；標示於圖1I）。
在一實施例中，第三導電連接件150的最小徑寬150w大於導電穿孔115的最小徑寬115w（標示於圖1I）。也就是說，第三導電連接件150的最大傳輸電流值可以大於導電穿孔115的最大傳輸電流值。因此，第三導電連接件150可以適於（但不限於）用於電源供應、接地端等較大電流（相較於導電穿孔115的最大傳輸電流值）的傳輸，而導電穿孔115可以適於（但不限於）用於訊號等較小電流（相較於第三導電連接件150的最大傳輸電流值）的傳輸。
在本實施例中，晶片封裝結構100可以更包括多個第一導電端子181以及多個第二導電端子182。第一導電端子181位於第二晶片120與第二重佈線路層170之間，且第一導電端子181與第一晶片110重疊。第二導電端子182位於第二晶片120與第二重佈線路層170之間，且第二導電端子182與第一晶片110不重疊。相鄰的兩個第一導電端子181之間具有的第一間距P1，相鄰的兩個第二導電端子182之間具有的第二間距P2，且第一間距P1小於第二間距P2。
在本實施例中，於俯視狀態下（如圖1H所示），各個第一導電端子181的投影面積可以小於各個第二導電端子182的投影面積。舉例而言，各個第一導電端子181投影於第二密封面142（或平行於第一密封面141的一虛擬面）上的投影面積可以小於各個第二導電端子182投影於第二密封面142（或平行於第一密封面141的一虛擬面）上的投影面積。
在一實施例中，第一導電端子181電性連接於對應的導電穿孔115，且第二導電端子182電性連接於對應的第三導電連接件150。並且，第三導電連接件150的最小徑寬150w大於導電穿孔115的最小徑寬115w，且各個第二導電端子182的投影面積大於各個第一導電端子181的投影面積。因此，第三導電連接件150及對應的第二導電端子182可以適於（但不限於）用於電源供應、接地端等較大電流的傳輸，而導電穿孔115及對應的第一導電端子181可以適於（但不限於）用於訊號等較小電流的傳輸。
在本實施例中，晶片封裝結構100可以更包括多個第三導電端子183以及多個第四導電端子184。第三導電端子183位於第三晶片130與第二重佈線路層170之間，且第三導電端子183與第一晶片110重疊。第四導電端子184位於第三晶片130與第二重佈線路層170之間，且第四導電端子184與第一晶片110不重疊。相鄰的兩個第三導電端子183之間具有的第三間距P3，相鄰的兩個第四導電端子184之間具有的第四間距P4，且第三間距P3小於第四間距P4。
在本實施例中，於俯視狀態下（如圖1H所示），各個第三導電端子183的投影面積可以小於各個第四導電端子184的投影面積。舉例而言，第三導電端子183投影於第二密封面142（或平行於第一密封面141的一虛擬面）上的投影面積可以小於第四導電端子184投影於第二密封面142（或平行於第一密封面141的一虛擬面）上的投影面積。
在一實施例中，第三導電端子183電性連接於對應的導電穿孔115，且第四導電端子184電性連接於對應的第三導電連接件150。並且，第三導電連接件150的最小徑寬150w大於導電穿孔115的最小徑寬115w，且各個第四導電端子184的投影面積大於各個第三導電端子183的投影面積。因此，第三導電連接件150及對應的第四導電端子184可以適於用於電源供應、接地端等較大電流的傳輸，而導電穿孔115及對應的第三導電端子183可以適於用於訊號等較小電流的傳輸。
在本實施例中，第一晶片110的第一主動面111、第二晶片120的第二主動面121及第三晶片130的第三主動面131可以面向第二重佈線路層170。如此一來，可以降低第一晶片110與第二晶片120之間及第一晶片110與第三晶片130之間的訊號傳輸路徑，而可以提升訊號傳輸的品質或效率。
在一實施例中，第二晶片120及第三晶片130之間可以是同質的（homogeneous）晶片也可以是異質的（heterogeneous）晶片，於本發明並不加以限制。舉例而言，第二晶片120及第三晶片130可以是具有相同或不同功能（function）的晶粒（die）、封裝後晶片（packaged chip）、堆疊式的晶片封裝件（stacked chip package）或是特殊應用積體電路（Application-Specific Integrated Circuit；ASIC），但本發明不限於此。
圖2A至圖2F是依照本發明的第二實施例的晶片封裝結構的部分製造方法的部分剖面示意圖。在本實施例中，晶片封裝結構200的製造方法與第一實施例的晶片封裝結構100的製造方法相似，其類似的構件以相同的標號表示，且具有類似的功能、材質或形成方式，並省略描述。具體而言，圖2A至圖2F繪示接續圖1A的步驟的晶片封裝結構的部分製造方法的部分剖面示意圖。
接續圖1A，請參照圖2A，在本實施例中，配置第一晶片110於第一重佈線路層160上。
請參照圖2B，在本實施例中，可以形成密封材料249於第一重佈線路層160上。密封材料249覆蓋第一晶片110的第一主動面111、第一背面112、多個第一導電連接件117的側壁117s以及多個第二導電連接件118的側壁118s。
在本實施例中，密封材料249可以更覆蓋第二導電連接件118相對於載板191的一端，但本發明不限於此。在一未繪示的實施例中，密封材料249可以暴露出第二導電連接件118相對於載板191的一端。
請參照圖2C，在本實施例中，可以藉由雷射鑽孔、蝕刻或其他適宜的方式，移除部分的密封材料249以形成多個開口249b，且開口249b可以暴露出部分的最頂的導電層162a。
請參照圖2D，在本實施例中，可以藉由一般常用的半導體製程（如：沉積製程及/或鍍覆製程）以將導電材料259填入開口249b（標示於圖2C）內。填入開口249b內的導電材料259可以電性連接於部分的最頂的導電層162a。
在本實施例中，導電材料259可以更覆蓋密封材料249相對於載板191的表面，但本發明不限於此。在一未繪示的實施例中，導電材料259可以暴露出密封材料249相對於載板191的表面。
請參照圖2E，在本實施例中，若導電材料259（標示於圖2D）完全覆蓋密封材料249（標示於圖2D）相對於載板191的表面，則可以藉由蝕刻、研磨、拋光或其他適宜的方式移除部分的導電材料259，以暴露出密封材料249相對於載板191的表面。
請繼續參照圖2E，在本實施例中，若密封材料249（標示於圖2C）完全覆蓋第二導電連接件118相對於載板191的一端，則可以藉由蝕刻、研磨、拋光或其他適宜的方式，以暴露出第二導電連接件118相對於載板191的一端。
在本實施例中，若導電材料259（標示於圖2C）完全覆蓋密封材料249（標示於圖2C）相對於載板191的表面，且密封材料249完全覆蓋第二導電連接件118相對於載板191的一端，則可以藉由前述的步驟以形成多個第三導電連接件250及覆蓋多個第三導電連接件250的側壁250s的密封體240。
在一實施例中，第三導電連接件250可以被稱為塑模穿孔（Through Mold Via；TMV），但本發明不限於此。
在形成第三導電連接件250及密封體240之後，可以藉由類似於圖1F至圖1G所繪示的步驟，以形成圖2F所示的晶片封裝結構200。
請參照圖2F，晶片封裝結構200可以包括第一晶片110、密封體240、第一重佈線路層160、第二重佈線路層170、第二晶片120、第三晶片130以及多個第三導電連接件250。第三導電連接件250貫穿密封體240。第三導電連接件250電性連接於部分的第一重佈線路層160及部分的第二重佈線路層170。
在本實施例中，第三導電連接件250的徑寬（如：最小徑寬250w）可以大於導電穿孔115的徑寬（如：最小徑寬115w；標示於圖1I）。
在本實施例中，第二導電端子182可以電性連接於對應的第三導電連接件250，且第四導電端子184電性連接於對應的第三導電連接件250。
前述實施例之線路層或線路結構（如：線路結構114、第一重佈線路層160及/或第二重佈線路層170）的佈線設計（layout design）可以依據應用上的需求進行調整。也就是說，在圖示中未直接相連的線路可能在其他的剖面上或其他的區域藉由其他的結構（如：導電通孔）或元件而電性連接。
綜上所述，本發明的晶片封裝結構及晶片封裝結構的製造方法可以具有較佳的訊號傳輸品質或效率。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
100、200:晶片封裝結構 110:第一晶片 111:第一主動面 112:第一背面 113:基材 114:線路結構 114a、114c:線路絕緣層 114b:線路導電層 115:導電穿孔 115a:穿孔絕緣層 115b:穿孔導電層 115w:徑寬 116:連接墊 117:第一導電連接件 117s:側壁 118:第二導電連接件 118a:頂面 118s:側壁 119:保護層 120:第二晶片 121:第二主動面 130:第三晶片 131:第三主動面 149、249:密封材料 249b:開口 140、240:密封體 141:第一密封面 142:第二密封面 259:導電材料 150、250:第三導電連接件 150a:頂面 150s、250s:側壁 150w、250w:徑寬 160:第一重佈線路層 161、161a:絕緣層 161b:開口 162、162a:導電層 170:第二重佈線路層 171:絕緣層 172:導電層 181:第一導電端子 P1:第一間距 182:第二導電端子 P2:第二間距 183:第三導電端子 P3:第三間距 184:第四導電端子 P4:第四間距 185:第五導電端子 191:載板 R:區域
圖1A至圖1G是依照本發明的第一實施例的一種晶片封裝結構的部分製造方法的部分剖視示意圖。 圖1H是依照本發明的第一實施例的一種晶片封裝結構的部分上視示意圖。 圖1I是依照本發明的第一實施例的一種晶片封裝結構的部分製造方法的部分剖視示意圖。 圖2A至圖2F是依照本發明的第二實施例的一種晶片封裝結構的部分製造方法的部分剖視示意圖。
100:晶片封裝結構
110:第一晶片
111:第一主動面
112:第一背面
114:線路結構
115:導電穿孔
117:第一導電連接件
118:第二導電連接件
120:第二晶片
121:第二主動面
130:第三晶片
131:第三主動面
140:密封體
141:第一密封面
142:第二密封面
150:第三導電連接件
150w:徑寬
160:第一重佈線路層
170:第二重佈線路層
181:第一導電端子
182:第二導電端子
183:第三導電端子
184:第四導電端子
185:第五導電端子

Claims (10)

  1. 一種晶片封裝結構，包括： 第一晶片，具有第一主動面、相對於所述第一主動面的第一背面、多個導電穿孔以及位於所述第一背面上的多個第一導電連接件； 密封體，覆蓋所述第一晶片的所述第一主動面、所述第一背面及所述多個第一導電連接件，且所述密封體具有第一密封面以及相對於所述第一密封面的第二密封面； 第一重佈線路層，位於所述密封體的所述第一密封面上； 第二重佈線路層，位於所述密封體的所述第二密封面上； 第二晶片，配置於所述第二重佈線路層上；以及 第三晶片，配置於所述第二重佈線路層上。
  2. 如申請專利範圍第1項所述的晶片封裝結構，其中所述第一晶片更具有位於所述第一主動面上的多個第二導電連接件，且所述密封體更覆蓋所述多個第二導電連接件。
  3. 如申請專利範圍第1項所述的晶片封裝結構，更包括： 多個第三導電連接件，貫穿所述密封體且電性連接於部分的所述第一重佈線路層及部分的所述第二重佈線路層，其中所述多個第三導電連接件的徑寬大於所述多個導電穿孔的徑寬。
  4. 如申請專利範圍第1項所述的晶片封裝結構，更包括： 多個第一導電端子，位於所述第二晶片與所述第二重佈線路層之間；以及 多個第二導電端子，位於所述第二晶片與所述第二重佈線路層之間，其中： 所述多個第一導電端子與所述第一晶片重疊； 所述多個第二導電端子與所述第一晶片不重疊； 所述多個第一導電端子的間距小於所述多個第二導電端子的間距；且 於俯視狀態下，各個所述多個第一導電端子的投影面積小於各個所述多個第二導電端子的投影面積。
  5. 如申請專利範圍第1項所述的晶片封裝結構，更包括： 多個第三導電端子，位於所述第三晶片與所述第二重佈線路層之間；以及 多個第四導電端子，位於所述第三晶片與所述第二重佈線路層之間，其中： 所述多個第三導電端子與所述第一晶片重疊； 所述多個第四導電端子與所述第一晶片不重疊； 所述多個第三導電端子的間距小於所述多個第四導電端子的間距；且 於俯視狀態下，各個所述多個第三導電端子的投影面積小於各個所述多個第四導電端子的投影面積。
  6. 如申請專利範圍第1項所述的晶片封裝結構，其中： 所述第二晶片具有第二主動面； 所述第三晶片具有第三主動面；且 所述第一晶片的所述第一主動面、所述第二晶片的所述第二主動面及所述第三晶片的所述第三主動面面向所述第二重佈線路層。
  7. 如申請專利範圍第1項所述的晶片封裝結構，其中所述第一晶片更具有位於所述第一背面上的線路結構，且所述多個第一導電連接件藉由所述線路結構電性連接於對應的所述多個導電穿孔。
  8. 如申請專利範圍第7項所述的晶片封裝結構，其中所述多個導電穿孔包括穿孔絕緣層及穿孔導電層。
  9. 如申請專利範圍第8項所述的晶片封裝結構，其中： 所述線路結構包括線路絕緣層及線路導電層； 所述穿孔絕緣層及所述線路絕緣層為相同的膜層；且 所述穿孔導電層及所述線路導電層為相同的膜層。
  10. 一種晶片封裝結構的製造方法，包括： 形成第一重佈線路層於載板上； 配置第一晶片於所述第一重佈線路層上，所述第一晶片具有第一主動面、相對於所述主動面的第一背面、多個導電穿孔以及位於所述第一背面上的多個第一導電連接件，且所述多個第一導電連接件電性連接於所述第一重佈線路層； 形成密封體於所述第一重佈線路層上，且覆蓋所述第一晶片的所述第一主動面、所述第一背面及所述多個第一導電連接件； 形成第二重佈線路層於所述密封體上； 配置第二晶片於所述第二重佈線路層上；以及 配置第三晶片於所述第二重佈線路層上。
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