TW202006923A - 半導體封裝及其製造方法 - Google Patents

半導體封裝及其製造方法 Download PDF

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TW202006923A
TW202006923A TW107146392A TW107146392A TW202006923A TW 202006923 A TW202006923 A TW 202006923A TW 107146392 A TW107146392 A TW 107146392A TW 107146392 A TW107146392 A TW 107146392A TW 202006923 A TW202006923 A TW 202006923A
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conductive
semiconductor
semiconductor die
shell
semiconductor package
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TW107146392A
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English (en)
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江家緯
方立志
范文正
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力成科技股份有限公司
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Publication of TW202006923A publication Critical patent/TW202006923A/zh

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Abstract

提供一種半導體封裝及其製造方法。半導體封裝包括導電殼、半導體晶粒、導電連接件、絕緣密封體、重佈線路結構以及第一導電端子。導電殼具有凹槽。半導體晶粒配置於導電殼的凹槽內。導電連接件位於導電殼的周圍。絕緣密封體包覆導電連接件、半導體晶粒以及凹槽。重佈線路結構位於絕緣密封體上，且重佈線路結構電性連接至導電連接件與半導體晶粒。第一導電端子位於重佈線路結構的開口內，且第一導電端子為物理性接觸部份的導電殼。

Description

半導體封裝及其製造方法
本發明提供一種半導體封裝及其製造方法，且特別是有關於一種具有導電殼（conductive casing）的半導體封裝及其製造方法。
近年來半導體封裝技術聚焦於較小傳送、有著高密度堆疊元件的高緊密產品，導致半導體元件之間距離變短。高密度的電子元件導致元件產生的熱的累積，且半導體元件間的較短的距離導致較大交互電磁波干擾（electromagnetic interference）。若未充分解決，則此兩項因素將導致半導體元件效能降低。因此，為了維持半導體封裝與半導體封裝內的半導體晶粒的高效能，在持續縮小半導體封裝時，充分地散熱與屏蔽電磁干擾是為本領域技術人員的一項挑戰。
本發明提供一種半導體封裝及其製造方法，且半導體封裝能有效地散熱及減少半導體封裝中的半導體晶粒的電磁波干擾的影響。
本發明提供一種半導體封裝，其包括導電殼、半導體晶粒、導電連接件、絕緣密封體、重佈線路結構以及第一導電端子。導電殼具有凹槽。半導體晶粒配置於導電殼的凹槽內。導電連接件位於導電殼的周圍。絕緣密封體包覆導電連接件、半導體晶粒以及凹槽。重佈線路結構位於絕緣密封體上，且重佈線路結構電性連接至導電連接件與半導體晶粒。第一導電端子位於重佈線路結構的開口內，且第一導電端子為物理性接觸部份的導電殼。
在本發明的一實施例中，半導體封裝更包括晶粒黏著層。晶粒黏著層位於導電殼的凹槽內，且介於半導導體晶粒與導電殼之間。
在本發明的一實施例中，導電殼的所述凹槽被所述絕緣密封體所填入，以使所述絕緣密封體包覆所述半導體晶粒。
在本發明的一實施例中，半導體封裝更包括第二導電端子。第二導電端子位於相對於半導體晶粒的重佈線路結構上且位於重佈線路結構的開口外部，其中第二導電端子電性耦合至重佈線路結構。
在本發明的一實施例中，第一導電端子的表面基本上對齊第二導電端子的表面。
本發明提供一種半導體封裝的製造方法。本方法包括至少以下步驟。配置半導體晶粒於導電殼的凹槽內。形成導電連接件於導電殼的周圍。形成絕緣密封體以包覆導電殼、半導體晶粒以及凹槽。形成重佈線路結構於在絕緣密封體上，其中重佈線路結構電性耦合至導電連接件與半導體晶粒。形成第一導電端子於重佈線路結構的開口內，以物理連接至部份的導電殼。
在本發明的一實施例中，在形成導電蓋之後，絕緣密封體暴露出導電蓋，且絕緣密封體包覆導電側壁。
在本發明的一實施例中，導電連接件形成於導電層上，且在形成導電蓋之後，移除連接於導電連接件的導電層。
在本發明的一實施例中，提供的半導體晶粒具有晶粒黏著層，且配置半導體晶粒於導電殼的凹槽內之後，半導體晶粒藉由晶粒黏著層接觸導電殼。
在本發明的一實施例中，其中形成絕緣密封體的步驟包括形成絕緣材料，以覆蓋導電殼、半導體晶粒以及導電連接件；以及減少絕緣材料的厚度，以形成絕緣密封體，其中絕緣密封體暴露出至少一部份的半導體晶粒、至少一部份的導電殼以及至少一部份的導電連接件。並且，其中在減少絕緣材料的厚度之後，絕緣密封體的表面共面於半導體晶粒的頂面以及導電殼暴露出的表面。
在本發明的一實施例中，半導體封裝的製造方法更包括：形成第二導電端子於相對於半導體晶粒的重佈線路結構上且位於重佈線路結構的開口的外部，其中第二導電端子電性耦合至重佈線路結構。並且，其中在形成第一導電端子與第二導電端子之後，第一端子的表面基本上對齊第二端子的表面。
基於上述，半導體封裝中的導電殼可有效地散出半導體封裝結構中的半導體晶粒與封裝件中其他電路所產生的熱。此外，導電殼可屏壁半導體晶粒以降低外部的電磁波干擾。此外，藉由貫穿重佈線路結構的第一端子連接至導電殼，可以構成直接的路徑，而將導電殼所擷取到的電子雜訊傳輸到接地端。如此一來，半導體封裝的效能可以進一步地提升。導電連接件提供進一步連接至配置於半導體封裝結構上的半導體封裝件，因而能夠實現封裝疊層（Package on Package；PoP）堆疊排列的半導體封裝。因此，可進一步提升封裝疊層排列的效能。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。在本文的附圖中，相同或相似的符號表示相同或相似的元件。
圖1A至圖1J是依據本發明一些實施例的半導體封裝的製造方法的剖面示意圖，圖2是圖1B的上方透視示意圖，且圖3是圖1I的上視示意圖。如圖1A所示，提供臨時載板100。臨時載板100可以由玻璃、塑膠、金屬、陶瓷或其他適宜的材料所製成，只要前述的材料能夠於後續的製程中，承載形成於其上的封裝結構。
在一些實施例中，所提供的臨時載板100可以具有離形層102及位於其上的導電層112。離形層102位於導電層112與臨時載板100之間，以暫時增加黏著性。當於之後移除臨時載板100時，離形層102有助於分離。離形層102可以為光熱轉換（light to heat conversion；LTHC）離型塗層及使用當暴露在輻射源下可降低黏著性的相關黏著劑的膜層。然而，本發明不限於此。在一些替代實施例中，可以使用其他適宜的離型層。導電層112包括位於臨時載板100上的銅箔。在一些實施例中，在形成銅箔前，選擇性地將晶種層（未圖式）形成於離形層102上。晶種層可以為單一導電層或包含數層不同材料的複合層（如：Ti/Cu層）。
請參照圖1B與圖2，可以在導電層112上形成導電側壁114。導電側壁114可以是藉由取放製程（pick and place）配置於導電層112上。導電側壁114可以是透過導電黏著劑（未繪示）接觸導電層112。在另一實施例中，導電側壁114可以是由沉積製程、塗佈製程或是其他適宜技術所形成。導電側壁114可以是如圖2所示的封閉環（例如矩形環形、環形、多邊形環形等其他環形），以藉由導電側壁114定義出凹槽C。導電層112形成於凹槽C底部。多個導電側壁114可以是以陣列的方式排列在臨時載板100上。為求簡潔，於實施例的圖式中僅示例性地繪示出了一個導電側壁114。導電層112的材質可以與導電側壁114的材質相同或不同。導電側壁114的材質可以包括銅、金屬合金、鋼、上述材質的組合或是其他適宜的導電材料。
請參照圖1C，配置半導體晶粒120於導電層112上。半導體晶粒120可以配置於凹槽C內。可以藉由取放製程或是其他適宜的方法來配置半導體晶粒120。凹槽C可以是用於容納半導體晶粒的區域。在一些實施例中，當將半導體晶粒120配置於凹槽C內，在半導體晶粒120與導電側壁114之間可以具有空隙。在一些實施例中，晶粒黏著層DA可以位於半導體晶粒120的背面RS與導電層112之間，以使半導體晶粒120接觸於導電層112，且提供低的晶粒位移。晶粒黏著層DA可以是晶粒黏著膜（die attach film；DAF）或是其他適宜的黏著材料。在一些實施例中，晶粒黏著層DA可以包括熱界面材料（thermal interface material；TIM），以提供良好的散熱。
在一些實施例中，半導體晶粒120可以包括半導體基板121、位於半導體基板121上的多個導電接墊122、電性連接至多個導電接墊122的多個導電凸塊124以及部分覆蓋導電接墊122的鈍化層126。在一些實施例中，半導體基板121可以是具有主動元件及選擇性地具有被動元件形成於其上的矽基板。半導體晶粒120可以是數位晶粒、類比晶粒或是綜合訊號晶粒，例如為特殊應用積體電路（Application-Specific Integrated Circuit；ASIC）晶粒、邏輯晶粒或是其他半導體元件。
請參照圖1D，多個導電連接件130可以是藉由微影、鍍析、光阻去除或其他適宜製程形成於凹槽C外的導電層112上。導電連接件130可以是由銅、鋁、鎳、金、上述材料的組合或其他適宜的導電材料製成。導電連接件130可以是藉由以下的步驟形成：形成具有開口的遮罩，其中前述的開口暴露至少一部份的導電層112；藉由電鍍或沉積的方式以將導電材料填入遮罩的開口；且移除遮罩以形成導電連接件130。每一個導電連接件130的寬度130W可以是相似、較窄或較寬於導電側壁114的寬度114W。在另一實施例中，多個導電連接件130可以是與導電側壁114同時形成。
請參照圖1E與圖1F，藉由覆模製程（over-molding process），以在導電層112上形成覆蓋導電側壁114、半導體晶粒120以及導電連接件130的絕緣材料142。絕緣材料142可以是形成在導電層112上，以填入凹槽C而包覆半導體晶粒120且包覆導電側壁114以及導電連接件130。絕緣材料142可以包括例如是聚合物、環氧樹脂、模塑化合物（molding compound）或是其他適宜樹脂。在形成絕緣材料142之後，絕緣材料142的厚度可以是藉由平坦化製程來減少，以形成絕緣密封體140。絕緣材料142可以是由化學機械研磨（chemical mechanical polish；CMP）、機械研磨或是其他適宜製程來平坦化。在對絕緣材料142進行平坦化時，可以移除部份的半導體晶粒120，以暴露出半導體晶粒120的導電凸塊124的頂面AS。在平坦化製程之後，絕緣密封體140暴露出導電連接件130的第一表面130a、導電側壁114的第一表面114a（即，暴露出的表面） 以及半導體晶粒120的頂面AS，且導電連接件130的第一表面130a、導電側壁114的第一表面114a以及半導體晶粒120的頂面AS可以基本上與絕緣密封體140的第一表面140a共面（coplannar）。絕緣密封體140可以覆蓋導電側壁114的側壁側面、半導體晶粒120以及導電連接件130。在一些實施例中，導電連接件130的高度基本上等於導電側壁114的高度。
在一些替代性實施例中，可以是在形成絕緣材料142之後，於絕緣材料142中藉由鑽孔製程（例如：雷射鑽孔、機械鑽孔或是其他適宜的技術）形成孔之後，才形成導電連接件130。接著，可以將導電材料以填入絕緣材料142的孔中。之後，可以平坦化絕緣材料142與導電材料，以形成絕緣密封體140及導電連接件130。導電連接件130可以是模塑穿孔（through molding vias；TMVs）。
請參照圖1G，在絕緣密封體140上形成重佈線路結構150。重佈線路結構150可以是直接接觸且電性連接至半導體晶粒120的導電凸塊124與導電連接件130。重佈線路結構150包括交替堆疊的至少一圖案化介電層151與至少一圖案化導電層152。圖案化導電層152可以是導電件（例如：導電線、導電接墊及/或導電通孔）。圖案化介電層151可以是由聚苯并惡唑（polybenzoxazole；PBO）、聚醯亞胺（polyimide；PI）、苯並環丁烯（benzocyclobutene；BCB）等有機介電材料、無機介電材料或其他適宜的電絕緣材料所製成。圖案化介電層151例如可以藉由旋轉塗佈製程（spin-on coating process）、沉積製程等其他適宜方法例來形成。
可以在絕緣密封體140、導電連接件130、導電側壁114以及半導體晶粒120上形成介電材料層。然後，可以藉由微影及蝕刻製程（lithography and etching process）或其他適宜的方法來移除部份的介電材料，以形成圖案化介電層151。圖案化介電層151可包括多個開口（未繪示），且開口暴露出部份的導電連接件130、導電側壁114以及半導體晶粒120的導電凸塊124，以用於進一步地電性連接。可以藉由沉積製程或其他適宜方法共形地（conformally）形成金屬層（未繪示）在圖案化介電層151上。在金屬層上可形成具有開口的圖案化光阻層（未繪示）。可以使用沉積、析鍍或其他適宜方法在圖案化光阻層的開口內的金屬層上沉積導電材質，導電材質可以包括銅、銅合金、鋁、鋁合金，或其上述材質的組合。之後，可以移除圖案化光阻層。可藉由蝕刻或其他適宜移除製程移除形成在圖案化光阻層下的金屬層。剩餘的部份金屬層與導電材料可形成圖案化導電層152。
在一些實施例中，可以不在導電側壁114上方的區域中形成圖案化導電層152。圖案化導電層152可以是在半導體晶粒120上方的第一佈線區域A1內形成，且可以與導電凸塊124物理性接觸。圖案化導電層152也可以在導電連接件130的上方第二佈線區域A2內形成，且可以與導電連接件130物理性接觸。介於第一佈線區域A1與第二佈線區域A2之間的間隙區域B對應於導電側壁114，且圖案化導電層152可以是不形成在間隙區域B內。
上述的步驟可以重覆執行多次，以形成電路設計所需的多層（multi-layered）重佈線路結構。頂部圖案化介電層151T可以具有開口151O，且開口151O暴露出至少一部份的頂部圖案化導電層152。頂部圖案化介電層151T的材料可以與在下方的介電材料不同。頂部圖案化介電層151T可包括焊料敏感材料，以在植球製程中保護圖案化導電層152。在一些實施例中，在圖案化介電層151的開口中形成的圖案化導電層152的一部分可以作為導電通孔，且在圖案化介電層151上形成的圖案化導電層152的多個部分可以作為導電線及導電接墊。導電接墊可以透過導電通孔電性連接至導電線。導電接墊在圖案化導電層152的頂部可以是凸塊底金屬（under-ball metallurgy；UBM）接墊。
請參照圖1H，重佈線路結構150包括位於間隙區域B內的至少一開口150b，且開口150b穿過圖案化介電層151以暴露出至少一部份的導電側壁114的第一表面114a。開口150b可以對應於封閉環型的導電側壁114的角或周圍。在一些實施例中，開口150b形成在圖案化介電層151中且遠離圖案化導電層152。如此一來，圖案化介電層151的絕緣介電材料位於開孔150b與圖案化導電層152之間，以避免圖案化導電層152與後續形成在開孔150b內的導電元件短路。重佈線路結構150的開口150b可以藉由雷射鑽孔、機械鑽孔、蝕刻或其他適宜的技術形成。在一些實施例中，可在相同的製程中形成頂部圖案化介電層151T的開口151O與開口150b。
請參照圖1I與圖3，在形成重佈線路結構150之後，於重佈線路結構150的開口150b內形成第一導電端子160，且於頂部圖案化介電層151T的開口151O內形成第二導電端子170。第一導電端子160可以是物理性及電性連接至導電側壁114。可以形成第一導電端子160以環繞半導體晶粒120。如圖3所示，可以在對應於封閉環型導電側壁114的周圍及/或角落上形成第一導電端子160。
第二導電端子170及/或第一導電端子160可以是藉由植球製程形成的球柵陣列（ball grid array，BGA）。在一些實施例中，可以使用兩種具有不同尺寸的孔洞的模版（未繪示）來形成第二導電端子170及第一導電端子160。第一模板的孔洞可以大於第二模板的孔洞。第一模板的孔洞可以對應於重佈線路結構150的開口150b。提供第一模板在重佈線路結構150上。接著，將焊料印刷在由第一模板的孔洞所暴露出的重佈線路結構150的開口150b上。之後，將第一導電球體（例如：焊球、金球、銅球、鎳球或類似球體）置放於第一模板上。藉由對第一導電球體施加特定的震盪頻率（vibration frequency），第一導電球體會掉入第一模板的孔洞中。之後，可以對第一導電球體進行迴焊（reflow）製程，以形成第一導電端子160。第一導電端子160可以是部分嵌入重佈線路結構150且接觸導電側壁114。部份的第一導電端子160可以凸出於重佈線路結構150，以進一步電性耦合至外部的電子裝置。第一導電端子160電性耦合至導電側壁114的方式可以是透過外部電子裝置接地或是直接接地。第一導電端子160連接至導電側壁114可以提供給電磁波干擾雜訊一個直接的路徑，以取代電磁波干擾雜訊通過重佈線路結構150的圖案化導電層152。
類似地，第二模板的孔洞可以對應於頂部圖案化介電層151T的開口150O。將助焊劑印在被頂部圖案化介電層151T及第二模板的孔洞所暴露出的圖案化導電層152上。此後，將第二導電球（其尺寸例如是小於第一導電球）放置於第二模版上，且經由施加特定的振動頻率以使第二導電球落入第二模版的孔洞中。之後，可以進行迴焊製程，以加強第二導電球以及重佈線路結構150之間的接合，並形成第二導電端子170。部份的第二導電端子170可以藉由重佈線路結構150電性耦合至導電連接件130，且另一部分的第二導電端子170可以藉由重佈線路結構150電性耦合至半導體晶粒120，以電性耦合導電連接件130與半導體晶粒至外部電子裝置（例如：印刷電路板（PCB）、半導體封裝等）。然而，第一導電端子160與第二導電端子170的形成順序於本發明中並不加以限制。
在一些替代實施例中，第一導電端子160及/或第二導電端子170可以是柱狀。可以藉由析鍍製程或其他適宜的形成方法來形成柱狀導電端子。然而，可以依據設計上的需求採用其他可能的類型與形狀的第一導電端子160及第二導電端子170。在一些實施例中，可以基於高度差基準線對齊每一個第一導電端子160的表面160a與每一個第二導電端子170的表面170a。
請參照圖1J，在形成第一導電端子160與第二導電端子170之後，可以移除臨時載板100與離型層102，以暴露出導電層112。可以藉由去黏合製程以從導電層112上分離臨時載板100。可以將紫外光雷射、可見光或熱等外部能量施加至離型層102，而使得導電層112與臨時載板100可以被分離。然後，結構可以被翻轉（flipped）（例如：將上側轉至下側）並放置到支撐物（未繪示）上以供後續製程。
可以藉由蝕刻製程或其他適宜的技術移除部份導電層112，以形成導電蓋116。導電側壁114具有第一表面114a及第二表面114b。第一表面114a耦合至第一導電端子160。第二表面114b相對於第一表面114a，且第二表面114b耦合至導電蓋116。導電蓋116與導電側壁114的集合體可以構成導電殼110。被移除的部份導電層112可以是覆蓋於導電連件130的部份導電層112。在移除時，可以暴露出導電連接件130的第二表面130b與部份的絕緣密封體140，導電連接件130第二表面130b相對於第一表面130a。如圖1J所示，在形成導電蓋116之後，可以進行單一化製程以形成多個半導體封裝10。
請參照圖1J，導電殼110位於重佈線路結構150上且包括由導電殼110的殼體及重佈線路結構150所包圍的凹槽C。導電殼110的凹槽C被絕緣密封體140填入。在凹槽C內的絕緣密封體140包覆半導體晶粒120與晶粒黏著層DA。導電殼110的總高度大於絕緣密封體140的厚度。半導體晶粒120配置在重佈線路結構150上且在導電殼110的凹槽C內，且導電殼110可以作為電磁波干擾屏蔽。
在一些其他的實施例中，可以提供沒有導電層形成於其上的替代臨時載板。導電側壁可以直接配置於替代臨時載板上。可在替代臨時載板上使用如圖1C至圖1I所描述的製程。在替代臨時載板移除之後，暴露出導電連接件130的第二表面130b、絕緣密封體140的第二表面140b以及導電側壁114的第二表面114b。絕緣密封體140的第二表面140b可以與導電連接件130的第二表面130b及導電側壁114的第二表面114b共面。可以使用沉積、微影、蝕刻、製程、積層或是任何其他適宜的方法，在導電側壁114上形成導電蓋116，以覆蓋凹槽C。
圖4是依據本發明一些實施例的半導體封裝10的應用的剖面示意圖。可以提供半導體裝置20，然後以相對於重佈線路結構150的方式配置在導電連接件130上，以形成封裝層疊結構30。在一些實施例中，半導體裝置20可以至少藉由導電連接件130與重佈線路結構150電性耦合至半導體晶粒120。導電殼110的導電蓋116可以位於半導體裝置20與半導體晶粒120之間。在一些實施例中，半導體裝置20可以藉由覆晶接合（flip chip bonding）技術及/或表面黏著技術（surface mount technology；SMT）接合在半導體封裝10上，且其彼此之間可以具有導電接頭。
半導體裝置20可以包括至少一半導體晶片210、重佈線路層220、絕緣體230以及外部端子240。重佈線路層220電性連接至半導體晶片210。絕緣體230配置在重佈線路層220上以包覆半導體晶片210。外部端子240電性連接至重佈線路層220且相對於半導體晶片210。半導體晶片210可以包括特殊應用積體電路晶片、微機電系統（Microelectromechanical systems ；MEMS）晶片、記憶體晶片、邏輯晶片。值得注意的是，圖4中的半導體晶片的數量僅為示例性說明，於本發明中對於半導體晶片的數量並不加以限制。在一些實施例中，半導體晶片210的主動面AS’與半導體晶粒120的頂部表面AS可以面向同一方向。在一些替代性的實施例中，半導體晶片210的主動面AS’與半導體晶粒120的頂部表面AS可以面向相對的方向。在將半導體裝置20配置在半導體封裝10上之後，外部端子240可以配置及/或位於半導體封裝10的導電連接件130上。可以使用迴焊製程來接合導電連接件130與半導體裝置20的外部端子240。可以使用另外的適宜方法以連接半導體裝置20在半導體封裝10上，以形成封裝層疊結構30。
綜上所述，導電殼可以是由剛性的材質形成，以提供半導體封裝的剛性與強度，因此增加了半導體封裝的可靠度（reliability）。此外，導電殼可由具有低熱容量（heat capacity）且高散熱的材料所製成，因而，導電殼可提供散熱的功能。另外，導電殼可有效地提供於導電殼中的電子裝置的電磁波干擾屏蔽的功能。在本文所述的實施例中，配置於導電殼中的半導體晶粒可以被屏蔽來自於導電殼外的電磁波干擾。此外，藉由貫穿重佈線路結構的第一端子連接至導電殼，可以構成直接的路徑，而將導電殼所擷取到的電子雜訊傳輸到接地端。如此一來，半導體封裝的效能可以進一步地提升。而且，半導體封裝的導電連接件可以實現封裝層疊排列的半導體封裝件，因此提供了多種產品設計的可能性。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
10‧‧‧半導體封裝20‧‧‧半導體裝置30‧‧‧封裝層疊結構100‧‧‧臨時載板102‧‧‧離型層110‧‧‧導電殼112‧‧‧導電層114‧‧‧導電側壁116‧‧‧導電蓋120‧‧‧半導體晶粒121‧‧‧半導體基板122‧‧‧導電接墊124‧‧‧導電凸塊126‧‧‧鈍化層130‧‧‧導電連接件114W、130W‧‧‧寬度140‧‧‧絕緣密封體114a、130a、140a‧‧‧第一表面114b、130b、140b‧‧‧第二表面142‧‧‧絕緣材料150‧‧‧重佈線路結構151‧‧‧圖案化介電層150b、151O‧‧‧開口151T‧‧‧頂部圖案化介電層152‧‧‧圖案化導電層160‧‧‧第一導電端子170‧‧‧第二導電端子160a、170a‧‧‧表面210‧‧‧半導體晶片220‧‧‧重佈線路層230‧‧‧絕緣體240‧‧‧外部端子A1‧‧‧第一佈線區域A2‧‧‧第二佈線區域AS‧‧‧頂面AS’‧‧‧主動面B‧‧‧間隙區域C‧‧‧凹槽DA‧‧‧晶粒黏著層RS‧‧‧後表面
圖1A至圖1J是依據本發明一些實施例的半導體封裝的製造方法的剖面示意圖。 圖2是圖1B的上方透視示意圖。 圖3是圖1I的上視示意圖。 圖4是依據本發明一些實施例的半導體封裝的應用的剖面示意圖。
10‧‧‧半導體封裝
110‧‧‧導電殼
114‧‧‧導電側壁
116‧‧‧導電蓋
120‧‧‧半導體晶粒
121‧‧‧半導體基板
122‧‧‧導電接墊
124‧‧‧導電凸塊
126‧‧‧鈍化層
130‧‧‧導電連接件
140‧‧‧絕緣密封體
114a、130a、140a‧‧‧第一表面
114b、130b、140b‧‧‧第二表面
150‧‧‧重佈線路結構
160‧‧‧第一導電端子
170‧‧‧第二導電端子
A2‧‧‧第二佈線區域
C‧‧‧凹槽
DA‧‧‧晶粒黏著層

Claims (10)

  1. 一種半導體封裝，包括： 導電殼，具有凹槽； 半導體晶粒，配置於所述導電殼的所述凹槽內； 導電連接件，位於所述導電殼的周圍； 絕緣密封體，包覆所述導電連接件、所述半導體晶粒以及所述凹槽； 重佈線路結構，位於所述絕緣密封體上，且所述重佈線路結構電性連接至所述導電連接件與所述半導體晶粒；以及 第一導電端子，位於所述重佈線路結構的開口內，且所述第一導電端子物理性接觸部份的所述導電殼。
  2. 如申請專利範圍第1項所述的半導體封裝，其中所述導電殼的所述凹槽由導電蓋與導電側壁所定義，所述導電側壁連接至所述導電蓋，所述絕緣密封體暴露出所述導電蓋，且所述絕緣密封體包覆所述導電側壁。
  3. 如申請專利範圍第2項所述的半導體封裝，其中： 所述導電側壁的高度基本上等於所述導電連接件的高度；且 所述導電殼的總高度大於所述絕緣密封體的厚度。
  4. 如申請專利範圍第1項所述的半導體封裝，其中所述半導體晶粒包括面向所述重佈線路結構的頂面，所述半導體晶粒的所述頂面基本上共面於所述導電殼的表面以及所述導電連接件的表面。
  5. 如申請專利範圍第1項所述的半導體封裝，更包括： 半導體裝置，配置相對於所述重佈線路結構的所述絕緣密封體上，且所述半導體裝置電性耦合至所述半導體晶粒。
  6. 一種半導體封裝的製造方法，包括： 配置半導體晶粒於導電殼的凹槽內； 形成導電連接件於所述導電殼的周圍； 形成絕緣密封體以包覆所述導電殼、所述半導體晶粒以及所述凹槽； 形成重佈線路結構於在所述絕緣密封體上，其中所述重佈線路結構電性耦合至所述導電連接件與所述半導體晶粒；以及 形成第一導電端子於所述重佈線路結構的開口內，以物理連接至部份的所述導電殼。
  7. 如申請專利範圍第6項所述的半導體封裝的製造方法，其中所述導電殼包括導電側壁與連接所述導電側壁的導電蓋，且所述半導體封裝的製造方法更包括： 在配置所述半導體晶粒之前，形成所述導電側壁於導電層上，以形成所述凹槽；以及 在形成所述第一導電端子之後，移除部份的所述導電層，以形成所述導電蓋。
  8. 如申請專利範圍第6項所述的半導體封裝的製造方法，其中形成所述絕緣密封體的步驟包括： 形成絕緣材料，以覆蓋所述導電殼、所述半導體晶粒以及所述導電連接件；以及 減少所述絕緣材料的厚度，以形成所述絕緣密封體，其中所述絕緣密封體暴露出至少一部份的所述半導體晶粒、至少一部份的所述導電殼以及至少一部份的所述導電連接件。
  9. 如申請專利範圍第6項所述的半導體封裝的製造方法，更包括： 形成第二導電端子於相對於所述半導體晶粒的所述重佈線路結構上且位於所述重佈線路結構的所述開口的外部，其中所述第二導電端子電性耦合至所述重佈線路結構。
  10. 如申請專利範圍第6項所述的半導體封裝的製造方法，更包括： 配置半導體裝置於相對於所述重佈線路結構的所述導電連接件上，其中所述半導體裝置電性耦合至所述半導體晶粒。
TW107146392A 2018-07-09 2018-12-21 半導體封裝及其製造方法 TW202006923A (zh)

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