CN110880457B - 半导体封装件及其形成方法 - Google Patents

半导体封装件及其形成方法 Download PDF

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Publication number
CN110880457B
CN110880457B CN201910831648.6A CN201910831648A CN110880457B CN 110880457 B CN110880457 B CN 110880457B CN 201910831648 A CN201910831648 A CN 201910831648A CN 110880457 B CN110880457 B CN 110880457B
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composite layer
forming
package
die
over
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CN110880457A (zh
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余振华
潘国龙
郭庭豪
蔡豪益
林修任
裴浩然
谢静华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US16/529,989 external-priority patent/US11309294B2/en
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Abstract

一种方法包括在载体上方形成复合材料层，该复合材料层包括结合到基底材料中的填充材料的颗粒，在复合材料层的第一侧上方形成一组通孔，将管芯附接在复合材料层的第一侧上方，管芯与该组通孔间隔开，在复合材料层的第一侧上方形成模制材料，模制材料最少横向密封管芯和该组通孔的通孔，在管芯和模制材料上方形成再分布结构，再分布结构电连接到通孔，在与第一侧相对的复合材料层的第二侧中形成开口，以及在开口中形成导电连接件，导电连接件电连接到通孔。本发明的实施例还涉及半导体封装件及其形成方法。

Description

半导体封装件及其形成方法
技术领域
本发明的实施例涉及半导体封装件及其形成方法。
背景技术
由于各种电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的不断改进，半导体工业经历了快速增长。在大多数情况下，集成密度的这种改进来自最小部件尺寸的反复减小，这允许将更多组件集成到给定区域中。随着最近对更小电子器件的需求增长，对半导体管芯的更小和更有创意的封装技术的需求不断增长。
这些封装技术的示例是封装叠层(POP)技术。在PoP封装件中，顶部半导体封装件堆叠在底部半导体封装件的顶部上，以实现高水平的集成和组件密度。另一个示例是多芯片模块(MCM)技术，其中多个半导体管芯封装在一个半导体封装件中以提供具有集成功能的半导体器件。
先进封装技术的高度集成使得能够生产具有增强功能和小占用面积的半导体器件，这对于诸如移动电话、平板电脑和数字音乐播放器的小型设备是有利的。另一个优点是连接半导体封装件内的互操作部分的导电路径的长度缩短。这改善了半导体器件的电性能，因为电路之间的互连的较短路由产生了更快的信号传播并降低了噪声和串扰。
发明内容
本发明的实施例提供了一种形成半导体封装件的方法，包括：在载体上方形成复合材料层，所述复合材料层包括结合到基底材料中的填充材料的颗粒；在所述复合材料层的第一侧上方形成一组通孔；将管芯附接在所述复合材料层的所述第一侧上方，所述管芯与所述一组通孔间隔开；在所述复合材料层的所述第一侧上方形成模制材料，所述模制材料最少横向密封所述管芯和所述一组通孔的通孔；在所述管芯和所述模制材料上方形成再分布结构，所述再分布结构电连接到所述通孔；在与所述第一侧相对的所述复合材料层的第二侧中形成开口；以及在所述开口中形成导电连接件，所述导电连接件电连接到所述通孔。
本发明的另一实施例提供了一种形成半导体封装件的方法，包括：形成器件封装件，其中，形成所述器件封装件包括：在复合层的第一表面上形成金属化图案，其中，所述复合层包括复合材料，并且其中，所述第一表面是凹陷的；在所述复合层和所述金属化图案上方形成第一介电层；在所述第一介电层上方形成导电柱，所述导电柱电连接到所述金属化图案；将第一半导体器件放置在所述第一介电层上，其中，所述第一半导体器件邻近所述导电柱并且与所述导电柱分隔开；用密封剂密封所述第一半导体器件和所述导电柱；和在所述密封剂上方形成再分布结构；在所述复合层的第二表面中形成开口以暴露所述金属化图案；以及使用导电连接件将顶部封装件附接到所述器件封装件，其中，所述导电连接件延伸穿过所述复合层中的所述开口。
本发明的又一实施例提供了一种半导体封装件，包括：下部封装件，包括：管芯，位于再分布结构上，所述管芯电连接到所述再分布结构；通孔，靠近所述管芯并且电连接到所述再分布结构；模制材料，位于所述再分布结构上方，所述模制材料插入在所述管芯和所述通孔之间；和复合层，位于所述管芯和所述通孔上方，所述复合层位于所述管芯的与所述再分布结构相对的一侧上方；以及顶部封装件，包括外部连接件，其中，所述外部连接件通过所述复合层连接到所述下部封装件。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该强调，根据工业中的标准实践，各个部件未按比例绘制并且仅用于说明的目的。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1示出了根据实施例的处于制造阶段的半导体封装件中的复合层的截面图。
图2至图13示出了根据实施例的处于各个制造阶段的半导体封装件的截面图。
图14示出了根据实施例的半导体封装件的截面图。
图15A至图15D示出了根据一些实施例的处于各个制造阶段的半导体封装件中的复合层的各种视图。
图16示出了根据实施例的半导体封装件的截面图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征不同的实施例或实例。下面描述了组件和布置的具体实施例或实例以简化本发明。当然这些仅是实例而不旨在限制。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。如本文使用的，在第二部件上形成第一部件是指形成与第二部件直接接触的第一部件。此外，本发明可以在各个示例中重复参考数字和/或字母。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
此外，为了便于描述，本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…上面”、“上部”等的空间关系术语，以描述如图中所示的一个元件或部件与另一元件或部件的关系。除了图中所示的方位外，空间关系术语旨在包括器件在使用或操作工艺中的不同方位。装置可以以其它方式定位(旋转90度或在其它方位)，并且在本文中使用的空间关系描述符可以同样地作相应地解释。
在半导体封装件和形成半导体封装件的方法的背景下讨论本发明的实施例，特别是集成扇出(InFO)半导体封装件。在载体上形成包括结合到介电材料(例如，聚合物)中的填充材料(例如，颗粒)的复合材料层，然后在复合材料上方形成一个或多个半导体管芯和/或导电柱。在载体上方和管芯周围以及导电柱周围形成模制材料。在模制材料、管芯和导电柱上方形成再分布结构。在一些情况下，使用复合材料层可以改善半导体封装件的结构刚度。复合材料层还可以减少由于其他层(诸如再分布结构的层)引起的翘曲或弯曲。另外，复合材料层可具有粗糙或凹陷的表面，该表面可改善随后沉积在复合材料上的材料的粘附性。
图1示出了根据实施例的处于制造阶段的封装结构500中的复合层110的截面图。图2至图13示出了根据实施例的处于各个制造阶段的封装结构500的截面图。图14示出了根据实施例的封装结构500的截面图。图15A至图15C示出了根据一些实施例的处于各个制造阶段的封装结构500中的复合层100的各种视图。图16示出了根据实施例的封装结构600的截面图。
参考图1，在载体101上方形成释放层103和复合层110。载体101可以是晶圆、面板结构等，并且可以由诸如硅、氧化硅、铝、氧化铝、聚合物、聚合物复合物、金属箔、陶瓷、玻璃、玻璃环氧树脂、氧化铍、带等、或它们的组合的材料制成。载体101为随后形成的结构提供支撑。
在一些实施例中，在形成复合层110之前，在载体101上方沉积或层压释放层103。释放层103可以由基于聚合物的材料形成，释放层103可以与载体101一起从后续步骤中形成的上面的结构去除。在一些实施例中，释放层103是基于环氧树脂的热释放材料，其在加热时失去其粘合性，诸如光热转换(LTHC)释放涂层。在其他实施例中，释放层103可以是光敏材料，诸如紫外(UV)胶，当暴露于UV光时，失去其粘合性。释放层103可以作为液体分配并固化，可以是层压在载体101上的层压膜等。释放层103的顶面可以是水平的并且可以具有高度的共面性。
仍然参考图1，复合层110形成在释放层103上方。图1还示出了复合层110的放大部分。在一些实施例中，复合层110是包括结合在基底材料113内的填充材料115的复合材料。填充材料115可以增加复合层110的机械强度或刚度，下面将更详细地描述。基底材料113可以是聚合物、环氧树脂、树脂、底部填充材料、材料的组合等。
复合层110的填充材料115可以包括颗粒、纤维等或它们的组合。在一些实施例中，填充材料115包括氧化硅、氧化铝等的颗粒或它们的组合。在一些实施例中，颗粒的直径为约0.5μm至约30μm，但在其他实施例中颗粒可具有其他直径。在一些实施例中，复合层110的填充材料115可以选择为具有特定的直径范围或具有平均直径。例如，在一些实施例中，填充材料115可以选择为具有在约0.5μm和约30μm之间的平均直径。在一些实施例中，复合层110内的填充材料115的体积可以是复合层110的总体积的约30％至约80％。在一些实施例中，填充材料115与基底材料113的体积比可以在约0.5：1和约3：1之间。可以选择填充材料115的特性以为复合层110提供特定的特性，诸如刚度。例如，具有较大平均直径的填充材料115的复合层110可以具有比具有较小平均直径的填充材料的复合层110更大的刚度(例如，更大的杨氏模量)。通过使用具有更大刚度的复合层110的材料，可以改善在其上形成的结构的刚度(例如，图14中的封装结构500)，并且可以减小结构的翘曲或弯曲(下面更详细地描述)。
在一些实施例中，复合层110是复合聚合物材料、底部填充材料、模塑料、环氧树脂、树脂、材料的组合等。在一些实施例中，复合层110可具有大于约10ppm/℃的热膨胀系数(CTE)，诸如约22ppm/℃。在一些实施例中，复合层110可具有大于约10GPa的杨氏模量，诸如约23GPa。在一些实施例中，复合层110可具有介于约10μm与约100μm之间的厚度，诸如约35μm。可以使用合适的沉积工艺在载体101上方形成复合层110，诸如旋涂、化学气相沉积(CVD)、层压等或它们的组合。在一些实施例中，在沉积之后使用固化工艺固化复合层110。固化工艺可以包括使用退火工艺或其他加热工艺将复合层110加热到预定温度达预定时间段。固化工艺还可以包括紫外(UV)曝光工艺、红外(IR)能量曝光工艺、其组合或与加热工艺的它们的组合。可选地，可以使用其他技术来固化复合层110。在一些实施例中，不包括固化工艺。
在一些情况下，复合层110的一个或多个表面可以是凹陷的，并且因此包括凹陷117，如图1所示。凹陷117可以由例如填充材料115的暴露的块引起，从基底材料113上脱落或以其他方式去除，留下凹陷117，填充材料115的块先前位于凹陷117中。例如，填充材料块115的暴露的块可能在随后的清洁工艺期间或在另一后续处理步骤期间脱落。在一些情况下，凹陷117中的一些可具有约等于或小于填充材料115的尺寸(例如，直径)的尺寸(例如，直径或深度)。例如，在一些实施例中，凹陷117中的一些可具有在约0.5μm和约30μm之间的直径或深度。然而，在一些情况下，一些凹陷117的尺寸可以小于填充材料115的尺寸或者大于填充材料115的尺寸。在一些情况下，凹陷117的存在可以改善上面的层(诸如图3中所示的介电层114)的粘附性。在一些情况下，凹陷117的存在可以使复合层110的表面具有介于约0.1μm和约10μm之间的粗糙度。在一些情况下，凹陷117可以覆盖复合层110的表面的约50％和约90％之间。
转到图2，在复合层110上形成金属化图案112。在一些实施例中，通过在复合层110上方形成晶种层(未示出)来形成金属化图案112。晶种层可以是金属层或其他类型的层，并且可以包括一种或多种不同材料的一层或多层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。然后在晶种层上形成并图案化光刻胶。可以通过旋涂等形成光刻胶，并且可以将光刻胶暴露于光用于图案化。光刻胶的图案对应于金属化图案112。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。导电材料可以通过镀形成，诸如电镀或化学镀等。导电材料可以包括金属，如铜、钛、钨、铝、组合等。然后，去除光刻胶和其上未形成导电材料的晶种层的部分。可以通过可接受的灰化或剥离工艺去除光刻胶，诸如使用氧等离子体等。在一些实施例中，一旦去除光刻胶，使用蚀刻工艺(诸如湿蚀刻工艺或干蚀刻工艺)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成金属化图案112。
在图3中，在金属化图案112和复合层110上形成介电层114。在一些实施例中，介电层114由聚合物形成，该聚合物可以是光敏材料，诸如可以使用光刻掩模图案化的PBO、聚酰亚胺、BCB等。在其他实施例中，介电层114由诸如氮化硅的氮化物、诸如氧化硅、PSG、BSG、BPSG的氧化物等形成。介电层114可以通过旋涂、层压、CVD等或它们的组合形成。图案化介电层114以暴露部分金属化图案112。可以使用可接受的工艺图案化介电层114，诸如在介电层114是光敏材料时通过将介电层114暴露于光。在一些实施例中，可以使用蚀刻掩模和诸如各向异性蚀刻工艺的合适的蚀刻工艺来图案化介电层114。在一些实施例中，可以使用类似技术在金属化图案112和介电层114上方的堆叠件中形成额外的金属化图案和介电层。
转到图4，在金属化图案112和介电层114上方形成通孔119。在一些实施例中，可以通过在介电层114上方形成晶种层以及然后在晶种层上方形成图案化的光刻胶来形成通孔119，其中图案化的光刻胶中的每个开口对应于待形成的通孔119的位置。使用诸如电镀或化学镀的合适技术，用诸如铜的导电材料填充介电层114中的开口。然后使用合适的工艺(诸如灰化或剥离工艺)去除光刻胶。然后可以使用合适的蚀刻工艺去除其上未形成通孔119的晶种层的部分。通孔119可以形成为在金属化图案112和介电层114之上延伸的导电柱。用于形成通孔119的其他技术也是可能的，并且完全旨在包括在本发明的范围内。
接下来，在图5中，将半导体管芯120(也可称为管芯或集成电路(IC)管芯)附接到介电层114的上表面。粘合膜118(诸如管芯附接膜(DAF))可用于将管芯120附接到介电层114。可以使用合适的工艺(诸如拾取和放置工艺)来附接管芯120。在一些实施例中，可以在附接管芯120之后固化DAF。
在粘附到介电层114之前，可以根据适用的制造工艺处理管芯120，以在管芯120中形成集成电路。例如，管芯120可以包括半导体衬底和一个或多个上面的金属化层，在图5中作为元件121共同示出。半导体衬底可以是例如掺杂或未掺杂的硅或绝缘体上半导体(SOI)衬底的有源层。半导体衬底可以包括其他半导体材料，诸如锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、氮化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；它们的组合等。也可以使用其他衬底，诸如多层或梯度衬底。管芯120可以包括在半导体衬底中和/或上形成的器件(未示出)，诸如晶体管、二极管、电容器、电阻器等，并且可以通过金属化层互连以形成集成电路。金属化层可以包括在半导体衬底上方的一个或多个介电层中的金属化图案(例如，作为再分布结构)。
管芯120还包括可以制成外部连接的焊盘126(例如，接触焊盘、铝焊盘等)。焊盘126可以位于管芯120的前侧(例如，“有源侧”)上。钝化膜127可以形成在管芯120的前侧上和焊盘126的部分上。开口可以形成为延伸穿过钝化膜127到焊盘126。管芯连接件128延伸到钝化膜127的开口中并且机械地和电气地耦合到相应的焊盘126。管芯连接件128可以是例如导电焊盘或导电柱。管芯连接件128可以包括一种或多种导电材料，诸如铜，并且可以使用诸如镀的合适工艺形成。管芯连接件128电耦合到管芯120的器件和/或集成电路。
介电材料129可以形成在管芯120的有源侧，诸如在钝化膜127和/或管芯连接件128上。介电材料129横向封装管芯连接件128，并且介电材料129与管芯120横向共末端。介电材料129可以是聚合物(诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB))、氮化物(诸如氮化硅等)、氧化物(诸如氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG))、组合等。例如，可以通过旋涂、层压、CVD等形成介电材料129。
接下来，在图6中，在介电层114上方形成模制材料130。模制材料横向围绕管芯120并横向围绕通孔119，将通孔119与管芯120分隔开并将通孔119彼此分隔开。作为示例，模制材料130可以包括环氧树脂、有机聚合物、添加或不添加基于二氧化硅或玻璃填料的聚合物、或其他材料。在一些实施例中，模制材料130包括液体模制化合物(LMC)，其在施加时是凝胶型液体。当施加时，模制材料130也可以包括液体或固体。可选地，模制材料130可以包括其他绝缘或密封材料。在一些实施例中，使用晶圆级模制工艺来施加模制材料130。模制材料130可以使用例如压缩模制、传递模制或其他技术模制。
在一些实施例中，可以使用固化工艺来固化模制材料130。固化工艺可以包括使用退火工艺或其他加热工艺将模制材料130加热至预定温度达预定时间段。固化工艺还可以包括紫外(UV)曝光工艺、红外(IR)能量曝光工艺、其组合等。可选地，可以使用其他技术来固化模制材料130。在一些实施例中，不执行固化工艺。
仍然参考图6，可以可选地执行平坦化工艺，诸如化学机械抛光(CMP)，以去除管芯120的前侧上方的模制材料130的多余部分。在平坦化工艺之后，模制材料130、通孔119和管芯连接件128可具有共面的顶面。
接下来参考图7和图8，根据一些实施例，再分布结构140形成在模制材料130、通孔119和管芯120的前侧上方。再分布结构140包括形成在一个或多个介电层(例如，介电层148)中的一层或多层导电部件(例如，包括导线143、通孔145等的金属化图案)。
在一些实施例中，一个或多个介电层(例如，介电层148)由聚合物形成，诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)、光敏聚合物等。在一些实施例中，一个或多个介电层可以包括其他材料，诸如氮化物(例如，氮化硅)、氧化物(例如，氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG))等。一个或多个介电层可以通过合适的沉积工艺形成，诸如旋涂、化学气相沉积(CVD)、层压等或它们的组合。
在图7中，介电层148形成在模制材料130、通孔119和管芯120的前侧上方，然后被图案化。图案形成开口以暴露通孔119和管芯120的管芯连接件128的部分。可以使用可接受的工艺图案化介电层148，诸如当介电层148是光敏材料时将介电层148暴露于光，并且在曝光后显影介电层148以形成开口。还可以通过使用例如各向异性蚀刻进行蚀刻来图案化介电层148。
仍然参考图7，在介电层148上形成包括导线143和通孔145的金属化图案。在一些实施例中，首先在介电层148上方和穿过介电层148的开口中形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和钛层上方的铜层。可以使用例如PVD等形成晶种层。然后在晶种层上形成并且图案化光刻胶。可以通过旋涂等形成光刻胶，并且可以将光刻胶暴露于光用于图案化。光刻胶的图案对应于金属化图案。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。导电材料可以通过镀形成，诸如电镀或化学镀等。导电材料可以包括金属，如铜、钛、钨、铝等。在形成导电材料之后，去除光刻胶和其上未形成导电材料的晶种层的部分。可以通过可接受的灰化或剥离工艺去除光刻胶，诸如使用氧等离子体等。一旦去除了光刻胶，就去除晶种层的暴露部分，例如使用可接受的蚀刻工艺，诸如湿蚀刻工艺或干蚀刻工艺。晶种层的剩余部分和导电材料形成导线143和通孔145。通孔145形成在穿过介电层148的开口中，以与介电层下面的部件(例如通孔119和/或管芯连接件128)形成电连接。
转到图8，可以在介电层148和导线143上方形成附加的介电层(未单独标记)和附加的导电部件(未单独标记)，形成再分布结构140。附加的介电层可以类似于介电层148，并且附加导电部件可以类似于导线143和通孔145。附加介电层或附加导电部件可以与介电层148或导线143和通孔145类似地形成。例如，可以通过在再分布结构140的介电层中形成开口以暴露下面的导电部件，在介电层上方和开口中形成晶种层(未示出)，在晶种层上方形成具有设计图案的图案化的光刻胶(未示出)，在所设计的图案中和在晶种层上方镀(例如，电镀或化学镀)导电材料，以去除光刻胶和其上未形成导电材料的晶种层的部分来形成导电部件。形成再分布结构140的其他方法也是可能的，并且完全旨在包括在本发明的范围内。
图8的再分布结构140中的介电层的数量和导电部件的层数仅仅是非限制性示例。其他数量的介电层和其他数量的导电部件的层也是可能的，并且完全旨在包括在本发明的范围内。
图8还示出了在再分布结构140上发形成并且电耦合到再分布结构140的凸块下金属化(UBM)结构147。在一些实施例中，通过首先在再分布结构140的最顶部介电层中形成开口以暴露再分布结构140的导电部件(例如，导线或焊盘)来形成UBM结构147。在形成开口之后，UBM结构147可以形成为与暴露的导电部件电接触。在实施例中，UBM结构147包括三层导电材料，诸如钛层、铜层和镍层。然而，有适合于形成UBM结构147的许多合适的材料和层的布置，诸如铬/铬铜合金/铜/金的布置、钛/钛钨/铜的布置或铜/镍/金的布置。可以用于UBM结构147的任何合适的材料或材料层完全旨在包括在本发明的范围内。
可以通过以下步骤形成UBM结构147：在最顶部介电层(例如，142)上方并且沿着最顶部介电层中的开口的内部形成晶种层；在晶种层上方形成图案化的掩模层(例如，光刻胶)；在图案化的掩模层的开口中和晶种层上方形成(例如，通过镀)导电材料；去除掩模层并且去除其上未形成导电材料的晶种层的部分。用于形成UBM结构147的其他方法是可能的，并且完全旨在包括在本发明的范围内。仅作为示例，图8中的UBM结构147的上表面示出为平坦的，UBM结构147的上表面可以不是平坦的。例如，如技术人员容易理解的，每个UBM结构147的部分(例如，外围部分)可以形成在最顶部介电层(例如，142)上方，并且每个UBM结构147的其他部分(例如，中心部分)可以沿着由相应的开口暴露的最顶部介电层的侧壁共形地形成。
接下来，在图9中，根据一些实施例，电子器件171附接到UBM结构147，并且连接件155形成在UBM结构147上方。电子器件171可以是器件、管芯、芯片或封装件，诸如集成无源器件(IPD)等。电子器件171通过导电连接件173通过UBM结构147电耦合到再分布结构140。导电连接件173可以是例如形成在电子器件171和再分布结构140之间的焊料连接件。导电连接件173可以是包括与连接件155相同的材料(例如，焊料)(见下文)。在一些实施例中，可以在放置电子器件171之前将焊剂材料(未示出)沉积在相关联的UBM结构147上。可以使用例如拾取和放置工艺来放置电子器件171。另外，底部填充材料175可以形成在电子器件171和再分布结构140之间的间隙中。电子器件171是可选的，并且在一些实施例中可以不包括电子器件171。
仍然参考图9，连接件155可以是焊球、金属柱、受控塌陷芯片连接(C4)凸块、微凸块、化学镀镍化学镀钯浸金技术(ENEPIG)形成的凸块、其组合(例如，具有附着有焊球的金属柱)等。连接件155可以包括导电材料，诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合。作为示例，在一些实施例中，连接件155包括共晶材料并且可以包括焊料凸块或焊球。焊料材料可以是例如铅基和无铅焊料，诸如用于铅基焊料的Pb-Sn组合物；包括InSb的无铅焊料；锡、银和铜(SAC)组合物；和其他具有共同熔点并在电气应用中形成导电焊料连接的共晶材料。作为示例，对于无铅焊料，可以使用不同组成的SAC焊料，诸如SAC 105(Sn 98.5％，Ag 1.0％，Cu 0.5％)、SAC 305和SAC 405。诸如焊球的无铅连接件也可以由SnCu化合物形成，而不使用银(Ag)。可选地，无铅焊料连接件可以包括锡和银Sn-Ag，而不使用铜。连接件155可以形成栅格，例如球栅阵列(BGA)。在一些实施例中，可以执行回流工艺，在一些实施例中使连接件155具有部分球形的形状。在一些情况下，可以对导电连接件173和连接件155执行回流工艺。可选地，连接件155可以包括其他形状。例如，连接件155还可以包括非球形导电连接件。在一些实施例中，在形成连接件155之前，可以在相关联的UBM结构147上方形成焊剂材料(未示出)。
在一些实施例中，连接件155包括金属柱(例如铜柱)，金属柱可以通过溅射、印刷、电镀、化学镀、CVD等形成，并且可以在其上形成或不形成焊料材料。金属柱可以是无焊料的并且具有基本垂直的侧壁或锥形侧壁。
图9中所示的结构是在载体101上方形成的单个器件封装件1100。本领域技术人员将理解，使用如图1至图9所示的类似处理步骤，可以在载体衬底(例如，载体101)上方形成许多封装件(例如，器件封装件1100)。图10至图14示出了根据一些实施例的图9的半导体封装件1100的进一步处理。使用在载体101上方形成的两个器件封装件(例如，1100A和1100B)示出了图10至图14的处理，应理解，在其他实施例中可以在载体101上方形成多于两个器件封装件。
图10示出了根据一些实施例的包括器件封装件1100A和器件封装件1100B的结构。器件封装件1100A和器件封装件1100B分别形成在载体101上方的区域100和200中。器件封装件1100A和1100B中的每个可以类似于图9中所示的器件封装件1100。
转到图11，根据一些实施例，翻转图10中所示的结构，并且外部连接件155附接到由框架157支撑的带159(例如，切割带)。接下来，通过合适的工艺(诸如蚀刻、研磨或机械剥离)将载体101从复合层110脱粘。在载体101和复合层110之间形成粘合剂层(例如，LTHC膜)的一些实施例中，可以通过将载体101暴露于激光或UV光来使载体101脱粘。激光或UV光破坏结合到载体101的粘合剂层的化学键，然后可以分离载体101。可以通过载体脱粘工艺去除粘合剂层。在使载体101脱粘之后，可以对复合层110执行清洁工艺以去除任何残留物(例如，从粘合剂层)。
转到图12，根据一些实施例，在使载体101脱粘之后，在复合层110中形成开口116以暴露金属化图案112。在一些实施例中，复合层110中的开口116可以使用合适的工艺形成，诸如激光钻孔工艺、蚀刻工艺等。在一些实施例中，蚀刻工艺是等离子体蚀刻工艺。在一些实施例中，在形成开口116之后执行清洁工艺以便去除任何残留物(例如，来自激光钻孔工艺)。尽管未示出，但是可以在开口116中形成焊膏以准备附接顶部封装件(参见图13)。可以使用焊膏印刷工艺或其他合适的工艺来形成焊膏。
接下来参考图13，根据一些实施例，顶部封装件160附接到器件封装件1100以形成封装结构500。在图13中，示例性顶部封装件160A和160B示出为附接到示例性器件封装件1100A和1100B，以分别形成示例性封装结构500A和500B。在一些实施例中，封装结构500可以是封装叠层(PoP)或集成扇出(InFO-PoP)结构。
如图13中所示，每个顶部封装件160(例如，160A，160B)包括衬底161和附接到衬底161的上表面的一个或多个半导体管芯162(例如，存储器管芯)。在一些实施例中，衬底161包括硅、砷化镓、绝缘体上硅(“SOI”)等或它们的组合。在一些实施例中，衬底161是多层电路板。在一些实施例中，衬底161由一种或多种材料形成，诸如双马来酰亚胺三嗪(BT)树脂、FR-4(由编织玻璃纤维布和具有阻燃性的环氧树脂粘合剂组成的复合材料)、陶瓷、玻璃、塑料、胶带、膜或其他支撑材料。衬底161可以包括形成在衬底161中或衬底161上的导电部件(例如，导线和通孔，未示出)。如图13所示，衬底161可以具有形成在衬底161的上表面和下表面上的导电焊盘163。导电焊盘163电耦合到衬底161的导电部件，诸如通孔或导线。一个或多个半导体管芯162通过例如接合线167电耦合到导电焊盘163。在衬底161上方和半导体管芯162周围形成模制材料165，模制材料165可以包括环氧树脂、有机聚合物、聚合物、密封剂等。在一些实施例中，模制材料165与衬底161共末端，如图13所示。
仍然参考图13，顶部封装件160可以通过导电焊盘163上的导电连接件168连接到器件封装件1100。导电连接件168在器件封装件1100的金属化图案112和顶部封装件160的导电焊盘163之间形成电连接。在一些实施例中，焊料材料170沉积在通过复合层110中的开口暴露的金属化图案112上方。导电连接件168附接到焊料材料170。在一些实施例中，导电连接件168包括焊料区域、导电柱(例如，在铜柱的至少端面上具有焊料区域的铜柱)等。在一些实施例中，执行回流工艺以将焊料材料170和导电连接件168接合。在回流工艺之后，可以执行烘烤工艺以去除湿气。
然后可以在顶部封装件160和相应的底部封装件1100之间的间隙中形成底部填充材料169。底部填充材料169可以使用例如针或喷射分配器分配到顶部封装件160和器件封装件1100之间的间隙中。在一些实施例中，可以执行固化工艺以固化底部填充材料169。尽管未在图13中示出，底部填充材料169可以在顶部封装件160的侧壁之间或沿着顶部封装件160的侧壁延伸。
接下来，在图14中，执行分割工艺以将封装结构500(例如，500A，500B)分成多个单独的封装结构。在完成分割工艺之后，形成多个单独的封装结构，诸如图14中所示的封装结构500。分割工艺可以例如使用锯切工艺、激光工艺、另一合适的工艺或工艺的组合。
在一些情况下，复合材料用于复合层110(先前参考图1描述)的使用可以提供诸如封装结构500的封装件的改善的刚度。复合层110在封装件(例如，封装结构500)中的使用可以减小该封装件的翘曲，诸如减小器件结构1100的翘曲和/或减小整个封装结构500的翘曲。例如，在一些情况下，再分布结构(例如，再分布结构140)可以赋予封装件上的弯曲力，该弯曲力导致封装件翘曲或弯曲。复合层110的刚度可以减轻由于这些弯曲力引起的翘曲，并因此减小封装件的整体翘曲。在一些情况下，使用诸如复合层110的复合层可以将翘曲的封装件的弯曲距离减小约0μm和约250μm之间。在一些情况下，复合层110的使用可允许封装结构具有小于约200μm的弯曲距离，诸如小于约80μm或小于约10μm。在一些情况下，使用复合层(诸如复合层110)可以将封装件的翘曲减小约50％至约100％。在一些实施例中，可以通过将复合层110和再分布结构140设置在管芯120的相对侧上来改善翘曲的减小。
转到图15A至图15D，根据一些实施例示出了复合层110的表面的说明性特写视图。图15A示出了图14中标记为“A”的区域的特写视图，其中底部填充材料169已经沉积在复合层110上方。如图15A所示，复合层110具有凹陷表面(以上也关于图1描述)。复合层110的凹陷表面可以提供底部填充材料169的改善的粘附性，这可以改善封装结构的整体刚度并减少分层的机会。图15B示出了图14中标记为“B”的区域的特写视图，包括复合层110的侧壁。如图15B所示，复合层110的侧壁也具有凹陷表面，该凹陷表面可以改善沉积在封装结构500上的其他材料(例如，模塑料、密封剂等，未在图中示出)的粘附性。图15C至图15D示出了图14中标记为“C”的区域的特写视图，包括复合层110中的开口，焊料材料170延伸穿过该开口(先前参照图12描述)。图15C示出了具有锥形开口的复合层110，图15D示出了具有基本垂直开口的复合层，但是在其他实施例中开口可以具有其他形状。如图15C至图15D所示，开口的侧壁可以是凹陷的，并且焊料材料170可以在沉积期间或在回流工艺期间流入凹陷中。以这种方式，焊料材料170可以具有对应于开口的侧壁中的凹陷的“凸块”。在一些情况下，凹陷可以提供焊料材料170与复合层110的更好的粘附。另外，在一些情况下，由于凹陷的存在，开口内的焊料材料170的增加的体积可以降低焊料材料170的电阻，并且因此改善了封装结构500的电性能。
接下来参考图16，示出了根据一些实施例的封装结构600。封装结构600包括顶部封装件160，顶部封装件160可以类似于先前描述的顶部封装件160(参见图13)。顶部封装件160附接到器件封装件1200以形成封装结构600。器件封装件1200类似于先前描述的器件封装件1100(参见图9)，除了未在复合层110(见图3)上方形成介电层114和金属化图案112之外。因此，通孔119和模制材料130直接形成在复合层110上。模制材料130的一些部分可以延伸到复合层110的凹陷表面的凹陷中。在一些情况下，复合层110的凹陷表面可以提供模制材料130的改善的粘附性。形成具有复合层110的封装结构的这些和其他变型旨在落入本发明的范围内。
实施例可以实现优点。通过在包括复合材料(例如，聚合物和填料)的层中形成具有导电元件(例如，焊料材料170)的封装件，可以提高封装件的刚度。以这种方式，可以减小封装件的翘曲，因此可以减少诸如与翘曲相关的破裂或分层的问题。另外，复合材料可以形成具有凹陷表面的层，这可以改善其他层与复合材料的粘附性，从而进一步提高封装件的可靠性和稳定性。
在实施例中，一种方法包括在载体上方形成复合材料层，该复合材料层包括结合到基底材料中的填充材料的颗粒，在复合材料层的第一侧上方形成一组通孔，将管芯附接在复合材料层的第一侧上方，管芯与该组通孔间隔开，在复合材料层的第一侧上方形成模制材料，模制材料最少横向密封管芯和该组通孔的通孔，在管芯和模制材料上方形成再分布结构，再分布结构电连接到通孔，在与第一侧相对的复合材料层的第二侧中形成开口，以及在开口中形成导电连接件，导电连接件电连接到通孔。在实施例中，填充材料的颗粒具有在0.5μm和30μm之间的平均直径。在实施例中，基底材料包括聚合物。在实施例中，填充材料包括氧化物。在实施例中，该方法包括在复合材料层上方形成介电层，其中介电层的材料不同于复合材料层的材料，并且其中该组通孔形成在介电层上。在实施例中，该方法包括在复合材料层上形成介电层之前在复合材料层上形成金属化图案。在实施例中，在复合材料层的第二侧中形成开口包括激光钻孔工艺。在实施例中，复合材料层的第二侧中的开口具有凹陷侧壁。在实施例中，导电连接件包括焊料材料，其中复合材料层内的导电连接件的侧壁包括横向延伸到复合材料层中的多个凸块。在实施例中，模制材料物理地接触复合材料层的第一侧。在实施例中，管芯物理地附接到复合材料层的第一侧。
在实施例中，一种方法包括形成器件封装件，其中形成器件封装件包括在复合层的第一表面上形成金属化图案，其中复合层包括复合材料，并且其中第一表面是凹陷的，在复合层和金属化图案上方形成第一介电层，在第一介电层上方形成导电柱，导电柱电连接到金属化图案，将第一半导体器件放置在第一介电层上，其中第一半导体器件邻近导电柱并且与导电柱分隔开，用密封剂密封第一半导体器件和导电柱，以及在密封剂上方形成再分布结构，在复合层的第二表面中形成开口以暴露金属化图案，并且使用导电连接件将顶部封装件附接到器件封装件，其中导电连接件延伸穿过复合层中的开口。在实施例中，复合层的杨氏模量在10GPa和50GPa之间。在实施例中，该方法包括在器件封装件和顶部封装件之间沉积底部填充物，底部填充物围绕导电连接件，其中底部填充物延伸到复合层的凹陷顶面的凹陷中。在实施例中，器件封装件具有小于80μm的弯曲距离。在实施例中，该方法包括分割器件封装件，其中器件封装件的侧壁表面包括多个凹陷。在实施例中，复合层包括结合到聚合物材料中的氧化铝。
在实施例中，半导体封装件包括下部封装件和顶部封装件，该下部封装件包括：管芯，位于再分布结构上，该管芯电连接到再分布结构；通孔，靠近管芯并且电连接到再分布结构；模制材料，位于该再分布结构上方，模制材料插入在管芯和通孔之间；以及复合层，位于管芯和通孔上方，复合层位于管芯的与再分布结构相对的一侧上方；顶部封装件包括外部连接件，其中外部连接件通过复合层连接到下部封装件。在实施例中，复合层的暴露侧壁具有凹陷表面。在实施例中，半导体封装件包括在复合层和顶部封装件之间延伸的底部填充材料，其中底部填充材料和复合层之间的界面是包括凹陷区域的表面。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基底来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并且不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (20)

1.一种形成半导体封装件的方法，包括：
在载体上方形成复合材料层，所述复合材料层包括结合到基底材料中的填充材料的颗粒；
在所述复合材料层的第一侧上方形成一组通孔；
将管芯附接在所述复合材料层的所述第一侧上方，所述管芯与所述一组通孔间隔开；
在所述复合材料层的所述第一侧上方形成模制材料，所述模制材料最少横向密封所述管芯和所述一组通孔的通孔；
在所述管芯和所述模制材料上方形成再分布结构，所述再分布结构电连接到所述通孔；
在与所述第一侧相对的所述复合材料层的第二侧中形成开口；以及
在所述开口中形成导电连接件，所述导电连接件电连接到所述通孔，
其中，所述复合材料层的所述第二侧中的所述开口具有凹陷侧壁。
2.根据权利要求1所述的方法，其中，所述填充材料的颗粒具有0.5μm至30μm的平均直径。
3.根据权利要求1所述的方法，其中，所述基底材料包括聚合物。
4.根据权利要求1所述的方法，其中，所述填充材料包括氧化物。
5.根据权利要求1所述的方法，还包括：在所述复合材料层上方形成介电层，其中，所述介电层的材料不同于所述复合材料层的材料，并且其中，所述一组通孔形成在所述介电层上。
6.根据权利要求5所述的方法，还包括：在所述复合材料层上形成所述介电层之前，在所述复合材料层上形成金属化图案。
7.根据权利要求1所述的方法，其中，在所述复合材料层的所述第二侧中形成所述开口包括激光钻孔工艺。
8.根据权利要求1所述的方法，其中，所述复合材料层具有介于10μm与100μm之间的厚度。
9.根据权利要求1所述的方法，其中，所述导电连接件包括焊料材料，其中，所述复合材料层内的所述导电连接件的侧壁包括横向延伸到所述复合材料层中的多个凸块。
10.根据权利要求1所述的方法，其中，所述模制材料物理地接触所述复合材料层的所述第一侧。
11.根据权利要求1所述的方法，其中，所述管芯物理地附接到所述复合材料层的所述第一侧。
12.一种形成半导体封装件的方法，包括：
形成器件封装件，其中，形成所述器件封装件包括：
在复合层的第一表面上形成金属化图案，其中，所述复合层包括复合材料，并且其中，所述第一表面是凹陷的；
在所述复合层和所述金属化图案上方形成第一介电层；
在所述第一介电层上方形成导电柱，所述导电柱电连接到所述金属化图案；
将第一半导体器件放置在所述第一介电层上，其中，所述第一半导体器件邻近所述导电柱并且与所述导电柱分隔开；
用密封剂密封所述第一半导体器件和所述导电柱；和
在所述密封剂上方形成再分布结构；
在所述复合层的第二表面中形成开口以暴露所述金属化图案；以及
使用导电连接件将顶部封装件附接到所述器件封装件，其中，所述导电连接件延伸穿过所述复合层中的所述开口。
13.根据权利要求12所述的方法，其中，所述复合层的杨氏模量在10GPa和50GPa之间。
14.根据权利要求12所述的方法，还包括：在所述器件封装件和所述顶部封装件之间沉积底部填充物，所述底部填充物围绕所述导电连接件，其中，所述底部填充物延伸到所述复合层的凹陷顶面的凹陷中。
15.根据权利要求12所述的方法，其中，所述器件封装件具有小于80μm的弯曲距离。
16.根据权利要求12所述的方法，还包括：分割所述器件封装件，其中，所述器件封装件的侧壁表面包括多个凹陷。
17.根据权利要求12所述的方法，其中，所述复合层包括结合到聚合物材料中的氧化铝。
18.一种半导体封装件，包括：
下部封装件，包括：
管芯，位于再分布结构上，所述管芯电连接到所述再分布结构；
通孔，靠近所述管芯并且电连接到所述再分布结构；
模制材料，位于所述再分布结构上方，所述模制材料插入在所述管芯和所述通孔之间；和
复合层，位于所述管芯和所述通孔上方，所述复合层位于所述管芯的与所述再分布结构相对的一侧上方；以及
顶部封装件，包括外部连接件，其中，所述外部连接件通过所述复合层连接到所述下部封装件，
其中，所述复合层的暴露侧壁具有凹陷表面。
19.根据权利要求18所述的半导体封装件，其中，所述凹陷具有在0.5μm和30μm之间的直径或深度。
20.根据权利要求19所述的半导体封装件，还包括：底部填充材料，在所述复合层和所述顶部封装件之间延伸，其中，所述底部填充材料和所述复合层之间的界面是包括凹陷区域的表面。
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